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* sh: sh2: remove CONFIG_SH2 definition from board configNobuhiro Iwamatsu2014-01-08-3/+0
| | | | | | | CONFIG_SH2 was already defined in arch/sh/sh2/config.mk. This removes CONFIG_SH2 from board config files of SH2. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* sh: sh2: Add CONFIG_SH2 definition to config.mk of SH2Nobuhiro Iwamatsu2014-01-08-1/+1
| | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* sh: delete redundant CONFIG_SH definitionMasahiro Yamada2014-01-08-21/+0
| | | | | | | | | | CONFIG_SH is defined in arch/sh/config.mk. It is not necessary to define it in each board header config header file. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-01-06-12/+59
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| * board/t1040qds: Enable memory reset controlPrabhakar Kushwaha2014-01-02-0/+6
| | | | | | | | | | | | | | Define QIXIS_RST_FORCE_MEM to reset on-board DDR-DIMM before start accessing it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * powerpc/b4860/pbl: fix rcw cfgShaohui Xie2014-01-02-1/+1
| | | | | | | | | | | | The BOOT_LOC setting in rcw cfg is wrong, set it to Memory complex 1. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
| * powerpc/t4240: enable NAND boot supportShaohui Xie2014-01-02-0/+1
| | | | | | | | Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
| * powerpc/cms700: limit NAND data structure sizeScott Wood2014-01-02-0/+3
| | | | | | | | | | | | | | This fixes a build break due to excessively large NAND data structures. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| * powerpc/t208x: fix macro CONFIG_SYS_FSL_NUM_USB_CTRLSShengzhou Liu2014-01-02-1/+1
| | | | | | | | | | | | | | CONFIG_SYS_FSL_NUM_USB_CTRLS is no longer used, update it to new CONFIG_USB_MAX_CONTROLLER_COUNT. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| * powerpc/B4860QDS: Define new nand_ecclayout structure macrosYork Sun2014-01-02-0/+2
| | | | | | | | | | | | | | | | | | | | Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to reduce the image size, by taking advantage of the new nand_ecclayout structure. Signed-off-by: York Sun <yorksun@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Scott Wood <scottwood@freescale.com>
| * powerpc/P1022DS: Define new nand_ecclayout structure macrosYork Sun2014-01-02-0/+2
| | | | | | | | | | | | | | | | | | | | Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to reduce the image size, by taking advantage of the new nand_ecclayout structure. Signed-off-by: York Sun <yorksun@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Scott Wood <scottwood@freescale.com>
| * powerpc/mpc85xx: Add support for single source clockingPriyanka Jain2014-01-02-2/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
| * board/t1040qds: Relax IFC FPGA timingsPrabhakar Kushwaha2014-01-02-1/+1
| | | | | | | | | | | | | | | | | | | | Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion) is 0 i.e. 0 ns hold time on writes. This may not work on higher clock freqencies. So, Increase TCH as 0x8 i.e. 8 ip_clk. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * board/freescale:Remove use of CONFIG_SPL_NAND_MINIMALPrabhakar Kushwaha2014-01-02-6/+9
| | | | | | | | | | | | | | | | | | CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary review purpose. So, use CONFIG_SPL_NAND_BOOT config. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * board/t1040qds: Fix typo in t1040_pbi.cfg filePrabhakar Kushwaha2014-01-02-1/+1
| | | | | | | | | | | | | | | | T1040QDS has 256KB SRAM. Comment is showing wrong information. So update the comment. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-onenandTom Rini2014-01-06-1/+7
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| * | mtd: onenand: Fix unaligned accessMarek Vasut2013-12-31-1/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix unaligned access in OneNAND core. The problem is that the ffchars[] array is an array of "unsigned char", but in onenand_write_ops_nolock() can be passed to the memcpy_16() function. The memcpy_16() function will treat the buffer as an array of "unsigned short", thus triggering unaligned access if the compiler decided ffchars[] to be not aligned. I managed to trigger the problem with regular ELDK 5.4 GCC compiler. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@ti.com>
* | PowerPC: Drop linkstation_HGLAN supportTom Rini2013-12-20-1135/+0
|/ | | | | | | | | With changes to the rtl8169 ethernet to improve cache support, we have needed additional cache functions for mpc8245. As the board maintainer has been unresponsive, remove this board. Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Tom Rini <trini@ti.com>
* ARM: Samsung: Change GONI and Universal_C210 maintainers.Łukasz Majewski2013-12-20-2/+2
| | | | | | | | Update boards.cfg entries for Samsung's GONI and Universal_C210 maintainers entry. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-12-19-14/+333
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| * driver: mtd: sf_ops: claim bus while doing memcpyPoddar, Sourav2013-12-19-0/+6
| | | | | | | | | | | | | | | | | | | | claim spi bus while doing memory copy, this will set up the spi controller device control register before doing a memory read. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Yebio Mesfin <ymesfin@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * config: dra7_evm: Add Bank Address Register(BAR) configPoddar, Sourav2013-12-19-0/+1
| | | | | | | | | | | | | | | | Add config to support bank address register. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Yebio Mesfin <ymesfin@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * spi: tegra: clear RDY bit prior to every transferYen Lin2013-12-19-13/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RDY bit indicates that a transfer is complete. This needs to be cleared by SW before every single HW transaction, rather than only at the start of each SW transaction (those being made up of n HW transactions). It seems that earlier HW may have cleared this bit autonomously when starting a new transfer, and hence this code was not needed in practice. However, this is generally a good idea in all cases. In Tegra124, the HW behaviour appears to have changed, and SW must explicitly clear this bit. Otherwise, SW will believe that transfers have completed when they have not, and may e.g. read stale data from the RX FIFO. Signed-off-by: Yen Lin <yelin@nvidia.com> [swarren, rewrote commit description, unified duplicate RDY clearing code and moved it right before the start of the HW transaction, unconditionally exit loop after reading RX data, rather than checking if TX FIFO is empty, since it is guaranteed to be] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * spi: Add support SH Quad SPI driverNobuhiro Iwamatsu2013-12-18-0/+316
| | | | | | | | | | | | | | | | | | This patch adds a driver for Renesas SoC's Quad SPI bus. This supports with 8 bits per transfer to use with SPI flash. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: probe: add support for MX25L2006ELuka Perkov2013-12-18-0/+1
| | | | | | | | | | | | | | Add support for Macronix MX25L2006E SPI flash. Signed-off-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sf: probe: Hex values are in lower caseLuka Perkov2013-12-18-1/+1
| | | | | | | | | | | | | | | | All other hex values in sf_probe.c are in lower case so we should fix this one too. Signed-off-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2013-12-18-48/+62
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| * | mtd: nand: omap: fix ecc ops assignment when changing eccNikita Kiryanov2013-12-17-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we change to software ecc and then back to hardware ecc, the nand ecc ops pointers are populated with incorrect function pointers. This is related to the way nand_scan_tail() handles assigning functions to ecc ops: If we are switching to software ecc/no ecc, it assigns default functions to the ecc ops pointers unconditionally, but if we are switching to hardware ecc, the default hardware ecc functions are assigned to ops pointers only if these pointers are NULL (so that drivers could set their own functions). In the case of omap_gpmc.c driver, when we switch to sw ecc, sw ecc functions are assigned to ecc ops by nand_scan_tail(), and when we later switch to hw ecc, the ecc ops pointers are not NULL, so nand_scan_tail() does not overwrite them with hw ecc functions. The result: sw ecc functions used to write hw ecc data. Clear the ecc ops pointers in omap_gpmc.c when switching ecc types, so that ops which were not assigned by the driver will get the correct default values from nand_scan_tail(). Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| * | mtd: nand: omap: fix sw->hw->sw ecc switchNikita Kiryanov2013-12-17-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When switching ecc mode, omap_select_ecc_scheme() assigns the appropriate values into the current nand chip's ecc.layout struct. This is done under the assumption that the struct exists only to store values, so it is OK to overwrite it, but there is at least one situation where this assumption is incorrect: When switching to 1 bit hamming code sw ecc, the job of assigning layout data is outsourced to nand_scan_tail(), which simply assigns into ecc.layout a pointer to an existing struct prefilled with the appropriate values. This struct doubles as both data and layout definition, and therefore shouldn't be overwritten, but on the next switch to hardware ecc, this is exactly what's going to happen. The next time the user switches to software ecc, they're going to get a messed up ecc layout. Prevent this and possible similar bugs by explicitly using the private-to-omap_gpmc.c omap_ecclayout struct when switching ecc mode. Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| * | nand_util.c: Use '%zd' for length in nand_unlock debug printTom Rini2013-12-17-1/+1
| | | | | | | | | | | | | | | | | | | | | length is size_t so needs to be '%zd' not '%d' to avoid warnings. Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Rini <trini@ti.com>
| * | mtd: nand: omap: fix HAM1_SW ecc using default value for ecc.sizeNikita Kiryanov2013-12-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit "mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform" (d016dc42cedbf6102e100fa9ecb58462edfb14f8) changed the way software ECC is configured, both during boot, and during ecc switch, in a way that is not backwards compatible with older systems: Older version of omap_gpmc.c always assigned ecc.size = 0 when configuring for software ecc, relying on nand_scan_tail() to select a default for ecc.size (256), while the new version of omap_gpmc.c assigns ecc.size = pagesize, which is likely to not be 256. Since 1 bit hamming sw ecc is only meant to be used by legacy devices, revert to the original behavior. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@ti.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Pekon Gupta <pekon@ti.com>
| * | mtd: nand: omap_gpmc: cosmetic: Fix indentationStefan Roese2013-12-17-43/+45
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pekon Gupta <pekon@ti.com> Cc: Scott Wood <scottwood@freescale.com> [scottwood@freescale.com: wrap some long lines] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | mtd: nand: omap: fix ecc-layout for HAM1 ecc-schemepekon gupta2013-12-17-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per OMAP3530 TRM referenced below [1] For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme - OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device - OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is: *for x8 NAND Device* +--------+---------+---------+---------+---------+---------+---------+ | xxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ... +--------+---------+---------+---------+---------+---------+---------+ *for x16 NAND Device* +--------+--------+---------+---------+---------+---------+---------+---------+ | xxxxx | xxxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | +--------+--------+---------+---------+---------+---------+---------+---------+ This patch fixes ecc-layout *only* for HAM1, as required by ROM-code For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices. [1] OMAP3530: http://www.ti.com/product/omap3530 TRM: http://www.ti.com/litv/pdf/spruf98x Chapter-25: Initialization Sub-topic: Memory Booting Section: 25.4.7.4 NAND Figure 25-19. ECC Locations in NAND Spare Areas Reported-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Tested-by: Stefan Roese <sr@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2013-12-18-9/+79
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| * | | usb: ehci: Fix register accessMarek Vasut2013-12-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the register access in EHCI HCD. We need to use address of the register as an ehci_writel() argument. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
| * | | usb: ehci: Do not de-init uninited controllersMarek Vasut2013-12-18-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case the controller is not initialized, we shall not de-initialize it. As the control structure will not be filled, we will produce a null ptr dereference if the controller is not inited. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
| * | | usb: ehci-pci: Clarify and cleanup the EHCI controller detectionMarek Vasut2013-12-18-3/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The detection function of the EHCI PCI controller was really cryptic, add a beefy comment and clean the portion of the code up a bit. No change in the logic of the code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
| * | | ARM: trats: dfu: Enable default Poll Timeout for Trats boardLukasz Majewski2013-12-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Provide default Poll Timeout value for Trats board. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
| * | | usb: f_dfu: cosmetic: Code cleanupLukasz Majewski2013-12-18-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Code cleanup for dfu_bind_config function Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
| * | | usb: dfu: f_dfu: Provide infrastructure to adjust DFU's Poll Timeout valueLukasz Majewski2013-12-18-3/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is necessary to deter the host from sending subsequent DFU_GETSTATUS request in the case of e.g. writing the buffer to medium. Here the timeout is increased when we fill up the whole buffer. This delay allows eMMC memory to perform its internal operations. Otherwise we end up with HOST's error regarding GET_STATUS receive timeout. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
| * | | dfu: Export allocated dfu buffer sizeLukasz Majewski2013-12-18-0/+6
| | |/ | |/| | | | | | | | | | | | | | | | The method for exporting size of allocated buffer is provided. It is afterwards used by USB's dfu function code. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
* | | Makefile: fix broken pipe error for lcd4_lwmon5 boardMasahiro Yamada2013-12-18-11/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, a broken pipe error sometimes happened when building lcd4_lwmon5 board with Buildman. This commit re-writes build rules of u-boot.spr and u-boot-img-spl-at-end.bin more simply without using a pipe. Besides fixing a broken pipe error, this commit gives us other advantages: - Do not generate intermidiate files, spl/u-boot-spl.img and spl/u-boot-spl-pad.img for creating u-boot.spr - Do not generate an intermidiate file, u-boot-pad.img for creating u-boot-img-spl-at-end.bin Such intermidiate files were not deleted by "make clean" or "make mrpropr". Nor u-boot-pad.img was ignored by git. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de>
* | | Makefile: fix the typo error for mrproperBo Shen2013-12-18-1/+1
|/ / | | | | | | | | | | | | Fix the typo error for mrproper from mkproper. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Simon Glass <sjg@chromium.org>
* | serial_sh: add support for SH7753Yoshihiro Shimoda2013-12-18-1/+3
| | | | | | | | | | Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | net: sh-eth: add support for SH7753Yoshihiro Shimoda2013-12-18-2/+6
| | | | | | | | | | | | | | | | SH7753 has two fast ethernet controllers and two gigabit ethernet controllers. It is similar to SH7757. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | sh: add support for sh7753evb boardYoshihiro Shimoda2013-12-18-0/+1368
|/ | | | | | | | | | | The SH7753 EVB board has SH7753, 512MB DDR3-SDRAM, SPI ROM, Gigabit Ethernet, and eMMC. This patch support the following functions: - 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Prepare v2014.01-rc2Tom Rini2013-12-16-1/+1
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2013-12-16-1/+1
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| * video: ipu_disp: Return a negative value on errorFabio Estevam2013-12-04-1/+1
| | | | | | | | | | | | We should return a negative error number (-EINVAL) on error. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-blackfinTom Rini2013-12-16-18/+36
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