| Commit message (Collapse) | Author | Age | Lines |
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Adjust POR_B settings on i.MX6ULL according to design
team's suggestion:
2'b00 : always PUP100K
2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL
2'b10 : always disable PUP100K
2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended setting
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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1 Add some APIs to operate BCB/command.
2 Add action to check the command of BCB.
It can cover the case that power down when do factory-reset\ota in recovery mode.
Signed-off-by: zhang sanshan <b51434@freescale.com>
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MXC_CCM_CCGR3_LDB_DI0_OFFSET should not be disabled for i.MX6SX.
Otherwise met compile error. And Discard the if else.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Support mx6ull ddr3 arm2 board.
DDR script version 1.1. Passed memtester on 3 boards.
Take mx6ul 14x14 ddr3 arm2 as reference.
Note:
LCD/NAND/ECSPI not tested, need hardware rework.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Since the mx6ull adds the AIPS3, so enable its initialization.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Update memory map address for mx6ull which uses AIPS3 and adjust UART8
to AIPS3 by replacing for ESAI.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Update CCM registers and clock settings according the mx6ull changes
Signed-off-by: Ye Li <ye.li@nxp.com>
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Since the work around is only for mx6ul TO1.0, so not use it for mx6ull.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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The PFD reset is not needed for mx6ull, since it uses runtime cpu id
checking here, add codes to skip it.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The MX6ULL has GPT with supporting OSC clock source, update the driver
accordingly.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The MX6ULL has two 128 bits fuse banks, bank 7 and bank 8, while other
banks use 256 bits. So we have to adjust the word and bank index when accessing
the bank 8.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Since iMX6ULL is derivative of iMX6UL, most of design are same, so enable
CONFIG_MX6UL to reduce duplicated effort.
We can use CONFIG_MX6ULL for the difference between these two chips.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add MXC_CPU_MX6ULL for i.MX6ULL CPU ID
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add iomux headers according the file SDK_IOMaps_i.MX6ULL_Headers_b151218.zip
Signed-off-by: Ye Li <ye.li@nxp.com>
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Partition name change from slotmeta to misc.
Read/write raw data on partition misc, not use ext4 file system.
Store meta in bootloader_message.slot_suffix, as defined in
bootable/recovery/bootloader.h
The first 4 bytes of boot_ctl are defined as magic number.
Also, modify code to remove warning in drivers/usb/gadget/bootctrl.c
warning: implicit declaration of function 'do_read'
Signed-off-by: fang hui <b31070@freescale.com>
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brillo need bootlader support boot control.
bootlader can choose which slot(partition) to boot based on
it's tactic.
The commit support boot control for evk6ul
Signed-off-by: fang hui <hui.fang@nxp.com>
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provide one config "CONFIG_NAND_MXS_BCH_LEGACY_GEO" to keep using legacy
bch geometry.
NOTICE: the feature must be enabled/disabled in both u-boot and kernel.
Signed-off-by: Han Xu <han.xu@nxp.com>
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From TO1.1, SNVS adds internal pull up control for POR_B,
the register filed is GPBIT[1:0], after system boot up,
it can be set to 2b'01 to disable internal pull up.
It can save about 30uA power in SNVS mode.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Q901 is PMOS, LCD_nPWREN should be at low voltage then output is 3V3.
If LCD_nPWREN is high, output is 2.4V which is not correct.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Fix 74LV OE gpio index. pinmux is correct, but gpio index
is wrong, so gpio output will not have effect, since we
use wrong GPIO5_IO18, but not correct GPIO5_IO8.
And at the end of the initialization of 74lv init, should
keep OE voltage level at LOW, but not high.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Need the CONFIG_MX6 for using the mx6_ecspi_fused funtion, otherwise will
break build for other platforms like MX7.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Some type style problems found by review-commits for previous patch
MLK-12483, fix them in this patch and re-check.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17]
for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit,
the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake
never clears.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Enable the configurations CONFIG_MODULE_FUSE and CONFIG_OF_SYSTEM_SETUP for
module fuse check. And modify board level codes for SD, FEC and EIM.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add the fuse checking in drivers, when the module is disabled in fuse,
the driver will not work.
Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C,
USB-EHCI, GIS, LCDIF.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Implement a functionality to read the soc fuses and check if any module
is fused. For fused module, we have to disable it in u-boot dynamically,
and change the its node in FDT to "disabled" status before starting the kernel.
In this patch, we implement the ft_system_setup for FDT fixup. This function will
be called during boot process or by "fdt systemsetup" command.
To enable the module fuse checking, two configurations must be defined:
CONFIG_MODULE_FUSE
CONFIG_OF_SYSTEM_SETUP
Signed-off-by: Ye Li <ye.li@nxp.com>
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When using ft_system_setup, the return value fdt_ret is not assigned,
so the fdt_strerror(fdt_ret) uses a uninitialized value.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The fdt command "fdt systemsetup" can't work because the do_fdt check the
start char 's' for command "fdt set". So the fdt systemsetup will also go into
the "fdt set" in fault. Fix this problem by checking the whole word "set" for
"fdt set" command.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Setup MMDC in two channel fixed mode
Initialize dram banks for two channel fixed mode
DRAM bank = 0x00000000
-> start = 0x10000000
-> size = 0x20000000
DRAM bank = 0x00000001
-> start = 0x80000000
-> size = 0x20000000
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
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TO1.1 already fixed this PMIC_STBY_REQ open drain issue.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Since DDR enter retention mode after kernel enter DSM mode, we have to exit DDR
retention mode before uboot boot, so add this in DCD and plugin code.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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enter retention
Since DDR enter retention mode after kernel enter DSM mode, we have to exit DDR
retention mode before uboot boot, so add this in DCD and plugin code. Meanwhile
correct the HW_ANADIG_SNVS_MISC_CTRL setting to avoid touching other bits.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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Adjust optimal valid clock cycles for 400Mhz operation
Adjust valid clock cycles before self-refresh exit tCKSRX
Adjust valid clock cycles after self-refresh entry tCKSRE
Set MMDC1_MPZQHWCCTRL upper 16 bits to default reset value
DDR calibration script
http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/040ee38ba9ad238fcb6053b663746d51321abb69
Test result: Stress test passed.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
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To simplify kernel clock management, we switch to use DRAM_PLL for
DRAM controller and DDR PHY, but not use DRAM_ALT_CLK_ROOT.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Since only DDR script changed, create build target for SD boot as example
to use TO1.0.
All default build target for 7D platforms are for TO1.1.
Signed-off-by: Ye Li <ye.li@nxp.com>
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On i.MX7D TO1.1, design team adds a mux cell at the CKE path to fix the suspend
mode reset issue, but seems it add extra delay on CKE path, so CKE-CK timing violated.
When DDR enters self-refresh or retention for long time(> 15seconds per testing on some boards),
DDR data corruption occured, not able to decrease CKE delay, so we have to add extra
delay on all other signals to balance it.
DDR script needs to be fine-tuned according to this hardware change.
For DDR3, since the timing margin is not good, we have to decrease the DDR frequency from
533Mhz to 400Mhz.
Compass link:
http://compass.freescale.net/livelink/livelink?func=ll&objid=235010235&objAction=browse&sort=name
Test:
Overnight tests passed on all changed boards.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Since the QSPI needs to rework on this board, at default the QSPI is disabled.
So bind the M4 QSPI boot with QSPI enabled u-boot image, set default
M4 boot to TCM. Need to use TCM m4 image at default.
Additional, on SDB there is only one QSPI flash. Considering the A7 QSPI boot
case, we have to move M4 image to 1M offset to give enough space for u-boot
and env.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The BOOTCFG value used by bmode for SABRESD eMMC boot are actually for SD card.
Fixed the value to correct one.
The issue was fixed in 2014.04 u-boot, but that patch seems missed during porting
to 2015.04.
Signed-off-by: Ye Li <ye.li@nxp.com>
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We have some vendor specific codes in board/freescale/common
which the picoimx configs also need them when Android or
Brillo configs is enabled.
So added the folder in Makefile to pass the compile.
Signed-off-by: Haoran Wang <Haoran.Wang@freescale.com>
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Modify the picosom to be suit for Brillo configurations.
Signed-off-by: Haoran Wang <Haoran.Wang@freescale.com>
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Imported the picosom boot codes and board
configs from technexion.
Signed-off-by: Tapani Utriainen <tapani@technexion.com>
Signed-off-by: Haoran Wang <Haoran.Wang@freescale.com>
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Define CONFIG_SYS_VSNPRINTF to use snprintf, but not sprintf.
Coverity ID: 17926.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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We support max 16 endpoints, but endpoint starts from 0.
So we need to use >= 16 but not > 16 to check whether we
already reach max endpoints or not.
Coverity ID 17955:
Out-of-bounds read (OVERRUN)
37. overrun-local: Overrunning array dev->config.if_desc[ifno].ep_desc of 16
9-byte elements at element index 16 (byte offset 144) using index epno
(which evaluates to 16).
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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We should use ARRAY_SIZE, but not directly sizeof, otherwise
we may access memory that is not belong the array env_flags_varaccess_mask.
Coverity ID: 17949
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Report Coverity log:
Destination buffer too small (STRING_OVERFLOW)
string_overflow: You might overrun the 1024 byte destination string
lastcommand by writing 1025 bytes from console_buffer
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Reported by coverity ID: 17900 17902
Using uninitialized value e. Field e.flags is uninitialized when calling hsearch_r
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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The list_first_entry always assumes the list is not empty, it won't return NULL pointer when
the list is empty. So the "if (pdesc == NULL)" becomes a dead code. Fix the issue by calling
the list_empty before the list_first_entry.
(Coverity CID 29934)
Signed-off-by: Ye.Li <ye.li@nxp.com>
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Fix a read from pointer after free issue in nand error handling path,
which was found by coverity.
Signed-off-by: Han Xu <han.xu@nxp.com>
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unsigned long long data might have strange data if first bit of u8 data
was 1. this patch cast it to (unsigned long long)
ex)
u8 data8;
u64 data64;
data8 = 0x80;
data64 = (data8 << 24); // 0xffffffff80000000
data64 = (((unsigned long long)data8) << 24); // 0x80000000;
(reported by Coverity)
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
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Before calling hsearch_r, initialize callback entry to NULL.
Coverity log:
"
Uninitialized scalar variable (UNINIT)
uninit_use_in_call: Using uninitialized value e.
Field e.callback is uninitialized when calling hsearch_r.
"
Reported-by: Coverity
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
(cherry picked from commit 5a6894397a657edec5d0cf4e20968cc66a368c51)
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