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* powerpc/mpc8xxx: take fdt_fixup_crypto_node() off the checkstack listKim Phillips2012-11-27-3/+3
| | | | | | | | | by moving compat_strlist into the .bss section. 0xfe004d80 fdt_fixup_crypto_node [u-boot]: 264 Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Temporary fix for spin table backward compatibilityYork Sun2012-11-27-1/+52
| | | | | | | | | | | | Once u-boot sets the spin table to cache-enabled memory, old kernel which uses cache-inhibit mapping without coherence will not work properly. We use this temporary fix until kernel has updated its spin table code. For now this fix is activated by default. To disable this fix for new kernel, set environmental variable "spin_table_compat=no". After kernel has updated spin table code, this default shall be changed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/P2041RDB: Fix Flash address LAW addressYork Sun2012-11-27-4/+10
| | | | | | | | | P2041RDB uses common corenet TLB and LAW. However it doesn't have promjet connector. It is necessary to use the same base address for correct LAW address. An offset is added for NOR flash. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/corenet_ds: Update DDR timing for single-rank DIMMsYork Sun2012-11-27-2/+2
| | | | | | | | Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed 800, 900, 1000, 1200, 1300MT/s. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: implement check for erratum A-004849 work-aroundTimur Tabi2012-11-27-0/+66
| | | | | | | | | | | | | | | | The work-around for erratum A-004849 ("CoreNet fabric (CCF) can exhibit a deadlock under certain traffic patterns causing the system to hang") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004849, we can do this by verifying that the values in the specific registers that the work-around says to update. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: add support for the Freescale P5040DS Superhydra reference boardTimur Tabi2012-11-27-7/+916
| | | | | | | | | The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of P3041DS/P5020DS ("Hydra") reference board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx/p5040: add CONFIG_SYS_PPC64, del CONFIG_SYS_FSL_ELBC_MULTIBIT_ECCTimur Tabi2012-11-27-1/+1
| | | | | | | | | | | | The P5040 has an e5500 core, so CONFIG_SYS_PPC64 should be defined in config_mpc85xx.h. This macro was absent in the initial P5040 patch because it crossed paths with the patch that introduced the macro. Also delete CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC, since it's not used in the upstream U-Boot. It's a holdover from the SDK. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/qoriq: Move FMAN microcode locationYork Sun2012-11-27-3/+3
| | | | | | | | | Move FMAN microcude from 0xEF000000 to 0xEFF40000 to free up the beginning of this virtual bank so that this bank can store RCW or be used together with other banks to store large images. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 8xxx: Change all 8*xx_DDR addresses to 8xxxAndy Fleming2012-11-27-72/+55
| | | | | | | | | | | | | | | | | | | | | | There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* Remove obsolete header filePantelis Antoniou2012-11-27-2/+0
| | | | | | | usbdescriptors.h conflicts with linux/usb/ch9.h Remove it. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2012-11-26-457/+980
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| * nand: Add torture featureBenoît Thébaudeau2012-11-26-0/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a NAND Flash torture feature, which is useful as a block stress test to determine if a block is still good and reliable (or should be marked as bad), e.g. after a write error. This code is ported from mtd-utils' lib/libmtd.c. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Scott Wood <scottwood@freescale.com> [scottwood@freescale.com: removed unnec. ifdef and unwrapped error strings] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * nand: Fix nand_erase_opts() offset checkBenoît Thébaudeau2012-11-26-2/+2
| | | | | | | | | | | | | | NAND Flash is erased by blocks, not by pages. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Scott Wood <scottwood@freescale.com>
| * nand: Clean up nand_utilBenoît Thébaudeau2012-11-26-32/+32
| | | | | | | | | | | | | | | | | | | | | | This patch cleans up nand_util.c: - Fix tabs. - Fix typos. - Remove space character before opening parenthesis in function calls. - Fix comments. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Scott Wood <scottwood@freescale.com>
| * nand: Move the sub-page read support enable to a flagJoe Hershberger2012-11-26-5/+11
| | | | | | | | | | | | | | | | | | Use a flag instead of a hard-coded macro so that sub-page reads can be enabled in other cases (such as on-die ecc). This is the same as a5ff4f102937a3492bca4a9ff0c341d78813414c in Linux Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
| * driver/mtd:IFC NAND:Initialise internal SRAM before any writePrabhakar Kushwaha2012-11-26-1/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for SRAM i.e. "byte select" is not supported. Hence Read Modify Write is implemented in IFC for any "system side write" into sram buffer. Reading an uninitialized memory results in ECC Error from sram wrapper. Hence we must initialize/prefill SRAM buffer by any data before writing anything in SRAM from system side. To initialize SRAM user can use "READID" NAND command with read bytes equal to SRAM size. It will be a one time activity post boot Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [scottwood@freescale.com: fix fsl_ifc_sram_init prototype] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * README: Reference nand monitor commands in U-Boot READMEKarl O. Pinc2012-11-26-0/+1
| | | | | | | | | | | | Reference nand monitor commands in U-Boot README Signed-off-by: Karl O. Pinc <kop@meme.com>
| * nand/fsl: add NAND_NO_SUBPAGE_WRITE to eLBC and IFC driversScott Wood2012-11-26-2/+2
| | | | | | | | | | | | These controllers can only do hardware ECC on full page transfers. Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL bootScott Wood2012-11-26-39/+54
| | | | | | | | | | | | | | | | | | | | | | | | This allows DDR configuration to be deferred to the final U-Boot image, which is able to make use of SPD data. The SPL itself cannot use SPD due to code size constraints. It previously used fixed register values for DDR configuration, and those values did not work on the p2020rdb-pca board I tested with. It's possible that different revisions of the board require different settings. Using SPD eliminates that problem. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx/p1_p2_rdb_pc: clean up memory mapScott Wood2012-11-26-14/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Sort by address, and fix column alignment - Don't label things as localbus that aren't. Instead, put chipselect info at the end of the description for localbus windows. Note that NAND/NOR have their chipselects swapped when booting from NAND, and CS2 can be either PMC or VSC7385 depending on hwconfig. - Shrink NAND to the 32K that's actually mapped in the localbus - Assign an address and size to L2 SRAM. Remove the similarly named but unintelligible "L2 SDRAM(REV.)". - Remove the untrue comment about L1 stack being mapped with TLB0. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx/p1_p2_rdb_pc: convert from nand_spl to new splScott Wood2012-11-26-300/+28
| | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * spl/nand: config symbol documentationScott Wood2012-11-26-6/+183
| | | | | | | | | | | | | | | | | | | | | | | | Document parameters used for specifying the NAND image to be loaded. Also fix the definition of CONFIG_SPL_NAND_SIMPLE -- it's only nand_spl_simple.c, not the entire nand directory. The word "simple" is there for a reason. :-) Signed-off-by: Scott Wood <scottwood@freescale.com> --- v2: updated for makefile changes earlier in patchset
| * spl/nand: introduce CONFIG_SPL_NAND_DRIVERS, _BASE, and _ECC.Scott Wood2012-11-26-8/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some small SPLs do not use nand_base.c, and a subset of those also require a special driver. Some SPLs need software ECC but others can't fit it. All existing boards that specify CONFIG_SPL_NAND_SUPPORT have these symbols added to preserve existing behavior. Signed-off-by: Scott Wood <scottwood@freescale.com> -- v2: use positive logic for including bits of NAND, rather than a MINIMAL symbol that excludes things.
| * powerpc/mpc85xx/p1_p2_rdb_pc: new SPL supportScott Wood2012-11-26-5/+160
| | | | | | | | | | | | | | Introduces CONFIG_SPL_RELOC_TEXT_BASE and CONFIG_SPL_RELOC_STACK. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * spl/85xx: new SPL supportScott Wood2012-11-26-10/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL and CONFIG_SPL_BUILD, respectively. CONFIG_NAND_SPL can be removed once the last mpc85xx nand_spl target is gone. CONFIG_RAMBOOT will need to remain for other use cases, but it doesn't seem right to overload it for meaning SPL as well as nand_spl does. Even if it's somewhat appropriate for the main u-boot, the SPL itself isn't (necessarily) ramboot, and we don't have separate configs for SPL and main u-boot. It was also inconsistent, as other platforms such as mpc83xx didn't use CONFIG_RAMBOOT in this way. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * spl/powerpc: introduce CONFIG_SPL_INIT_MINIMALScott Wood2012-11-26-15/+73
| | | | | | | | | | | | | | | | | | cpu_init_nand.c is renamed to spl_minimal.c as it is not really NAND-specific. Signed-off-by: Scott Wood <scottwood@freescale.com> --- v2: factor out START, and change cpu_init_nand.c to spl_minimal.c Cc: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: consistently use COBJS-yScott Wood2012-11-26-9/+10
| | | | | | | | | | | | | | | | A subsequent patch will conditionalize some of the files that are currently unconditional. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * spl/mpc85xx: rename cpu_init_nand.c to spl_minimal.cScott Wood2012-11-26-28/+28
| | | | | | | | | | | | | | There is nothing really NAND-specific about this file. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * spl: include resetvec and lib8xxxScott Wood2012-11-26-0/+21
| | | | | | | | | | | | The toplevel makefile hardcodes this stuff, so spl/Makefile needs to as well. Signed-off-by: Scott Wood <scottwood@freescale.com>
| * spl/mpc85xx: move udelay to cpu codeScott Wood2012-11-26-55/+20
| | | | | | | | | | | | | | | | | | It applies to non-Freescale 85xx boards as well as Freescale boards, so it doesn't belong in board/freescale. Plus, it needs to come out of nand_spl if it's to be used by the new SPL. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxxScott Wood2012-11-26-8/+8
| | | | | | | | | | | | | | | | | | | | | | It's arch code and not a driver, so move it where it belongs. When it originally went into drivers/misc there was no 8xxx CPU directory. This will make new-SPL support a little easier since we can keep the CPU stuff together and not need to pull stuff in from drivers/misc. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: fix TLB alignmentScott Wood2012-11-26-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the RAMBOOT/SPL case we were creating a TLB entry starting at CONFIG_SYS_MONITOR_BASE, and just hoping that the base was properly aligned for the TLB entry size. This turned out to not be the case with NAND SPL because the main U-Boot starts at an offset into the image in order to skip the SPL itself. Fix the TLB entry to always start at a proper alignment. We still assume that CONFIG_SYS_MONITOR_BASE doesn't start immediately before a large-page boundary thus requiring multiple TLB entries. Signed-off-by: Scott Wood <scottwood@frescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * powerpc: change .fixup test to a GCC version testScott Wood2012-11-26-6/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was introduced by commit 244615197469dd6fe75ae082f38424b97c79aeaf, but it fails in a minimal SPL build where the only thing in arch/powerpc/lib is cache.c, which apparently doesn't generate any fixup records. The problem is reported to occur with GCC 3.x, so insist on GCC 4.0 or newer. Patterned after checkthumb as suggested by Tom Rini. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Tom Rini <trini@ti.com> -- v2: test gcc version instead of testing nothing
| * spl: introduce CONFIG_SPL_TARGETScott Wood2012-11-26-0/+6
| | | | | | | | | | | | | | | | | | | | | | Currently the SPL target is specified in a CPU-specific makefile fragment. While some targets may need something more complicated than a simple target name, targets which don't need this shouldn't have to provide a makefile fragment just for this. Signed-off-by: Scott Wood <scottwood@freescale.com> --- v2: Removed default target as it's been pointed out to me how existing platforms cause the SPL to be built.
| * spl: rename u-boot-pad.bin to u-boot-with-spl.binScott Wood2012-11-26-4/+4
| | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| * Add u-boot-pad.bin target to the MakefileJosé Miguel Gonçalves2012-11-26-5/+6
| | | | | | | | | | | | | | | | | | | | | | Samsung's S3C24XX SoCs need this in order to generate a binary image with a padded SPL concatenated with U-Boot. Signed-off-by: José Miguel Gonçalves <jose.goncalves@inov.pt> [scottwood@freescale.com: fixed prereq of u-boot.ubl] Signed-off-by: Scott Wood <scottwood@freescale.com> -- v2: Removed spl/ prefix from u-boot.ubl prerequisite.
| * powerpc/mpc85xx: add comma before "already enabled"Scott Wood2012-11-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Now outputs like this: L2: 512 KB already enabled, moving to 0xf8f80000 rather than this: L2: 512 KB already enabledmoving to 0xf8f80000 Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@gmail.com>
| * powerpc/mpc85xx: move debug tlb entry after TLB is in known stateScott Wood2012-11-26-44/+40
| | | | | | | | | | | | | | | | | | | | | | | | Previously, in many if not all configs we were creating overlapping TLB entries which is illegal. This caused a crash during boot when moving p2020rdb NAND SPL into L2 SRAM. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Prabhakar Kushwaha <prabhakar@freescale.com> Cc: Andy Fleming <afleming@freescale.com> -- Prabhakar, please test that debug still works.
| * serial/ns16550: wait for TEMT before initializingScott Wood2012-11-26-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | TEMT is set when the transmitter is totally empty and all output has finished. This prevents output problems (including a loss of synchronization observed on p2020 that persisted for quite a while) if SPL has output still on its way out. Signed-off-by: Scott Wood <scottwood@freescale.com> -- v2: fixed typo in subject, and explained what the bit does in the changelog
| * serial/ns16550: don't build serial_ns16550 with MIN_FUNCTIONSScott Wood2012-11-26-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_NS16550_MIN_FUNCTIONS is used by small SPLs to gain access to basic ns16550 output code without pulling in things not needed by the SPL. This previously only worked with non-MULTI configs. Recently MULTI was made mandatory, and MIN_FUNCTIONS fails like this: drivers/serial/libserial.o: In function `calc_divisor.clone.0': serial_ns16550.c:(.text.calc_divisor.clone.0+0x24): undefined reference to `get_bus_freq' drivers/serial/libserial.o: In function `_serial_getc': (.text._serial_getc+0x30): undefined reference to `NS16550_getc' drivers/serial/libserial.o: In function `_serial_tstc': (.text._serial_tstc+0x30): undefined reference to `NS16550_tstc' drivers/serial/libserial.o: In function `_serial_setbrg': (.text._serial_setbrg+0x3c): undefined reference to `NS16550_reinit' make[1]: *** [/tmp/u-boot/spl/u-boot-spl] Error 1 make: *** [/tmp/u-boot/spl/u-boot-spl.bin] Error 2 With MIN_FUNCTIONS we don't need anything from this file, so don't build it. The conditional needs to be in the file itself rather than the makefile, because the config symbols are only imported to the makefiles once, not separately for the SPL phase of the build. Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fdtTom Rini2012-11-20-28/+461
|\ \
| * \ Merge branch 'next'Gerald Van Baren2012-11-19-28/+461
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| | * fdt: Remove fdtdec_find_alias_node() functionSimon Glass2012-11-12-23/+1
| | | | | | | | | | | | | | | | | | | | | This function is not needed, since fdt_path_offset() performs the same service. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * fdt: Set kernaddr if fdt indicates a kernel is presentSimon Glass2012-11-12-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If kernel-offset is specified in the fdt, set an environment variable so that scripts can access the attached kernel. This can be used by a packaging program to tell U-Boot about a kernel that has been downloaded alongside U-Boot. The value in the fdt is the offset of the kernel from the start of the U-Boot image, so we can find it just by adding CONFIG_SYS_TEXT_BASE. It is then fairly easy to put something like this in the environment variables in the board header file: "if test ${kernaddr} != \"\"; then "\ "echo \"Using bundled kernel\"; "\ "bootm ${kernaddr};" \ "fi; "\ /* rest of boot sequence follows here */ Signed-off-by: Simon Glass <sjg@chromium.org>
| | * fdt: Add option to default to most compatible conf in a fit imageGabe Black2012-11-12-0/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting a fit image with multiple configurations, the user either has to specify which configuration to use explicitly, or there has to be a default defined which is chosen automatically. This change adds an option to change that behavior so that a configuration can be selected explicitly, or the configuration which has the device tree that claims to be compatible with the earliest item in U-Boot's device tree. In other words, if U-Boot claimed to be compatible with A, B, and then C, and the configurations claimed to be compatible with A, D and B, D and D, E, the first configuration, A, D, would be chosen. Both the first and second configurations match, but the first one matches a more specific entry in U-Boot's device tree. The order in the kernel's device tree is ignored. Signed-off-by: Gabe Black <gabeblack@google.com> Commit-Ready: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * fdt: Allow device tree to specify secure bootingDoug Anderson2012-11-12-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When secure booting is chosen: * The u-boot shell is never invoked during boot--we just do a simple table lookup to find the command. This means we could even remove the shell parsing from u-boot and still be able to boot. * The boot command can't be interruped. * Failure doesn't cause us to fall back to the shell. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * fdt: Tell the FDT library where the device tree isGabe Black2012-11-12-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a call to set_working_fdt_addr near the end of u-boot initialization which tells the fdt command/library where the device tree is. This makes it possible to use the fdt command to look at the active device tree since otherwise there would be no way to know what address it was at to set things up manually. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * fdt: Load boot command from device treeChe-Liang Chiou2012-11-12-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | Load boot command from /config/bootcmd of device tree if present. Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * fdt: Add polarity-aware gpio functions to fdtdecSean Paul2012-11-12-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | Add get and set gpio functions to fdtdec that take into account the polarity field in fdtdec_gpio_state.flags. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * fdt: Add fdtdec_get_uint64 to decode a 64-bit value from a propertyChe-Liang Chiou2012-11-12-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | It decodes a 64-bit value from a property that is at least 8 bytes long. Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-12-27 22:29:29 +0000