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* Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2009-03-25-1807/+2107
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| * Blackfin: bf537-stamp: split post code out into dedicated post.cMike Frysinger2009-03-24-237/+245
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: add support for S25FL128 partsMike Frysinger2009-03-24-38/+47
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: overhaul SPI flash handling to speed things upMike Frysinger2009-03-24-6/+126
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: add support for SST SPI flashesMike Frysinger2009-03-24-29/+78
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: add hack for crappy m25p80Mike Frysinger2009-03-24-0/+7
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: bf537-stamp: increase monitor sizeMike Frysinger2009-03-24-1/+1
| | | | | | | | | | | | | | The new jffs2 code pushed the code size just over the limit, so increase the limit a bit more. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: bf537-stamp: bump default SCLK up to 125MHzMike Frysinger2009-03-24-1/+1
| | | | | | | | | | | | | | Since all of the bf537-stamp and bf537-ezkit boards out there can handle it, increase the speed of SCLK to 125MHz rather than 100MHz. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: bf537-stamp: rewrite MAC-in-flash handlingMike Frysinger2009-03-24-23/+84
| | | | | | | | | | | | | | Use the common net eth functions to setup the env/global data with the MAC address, and properly handle the case where CONFIG_SYS_NO_FLASH is defined. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: add clkin_hz= to default kernel command line for ADI boardsMike Frysinger2009-03-24-0/+1
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: bf533-stamp: bump up default clocksMike Frysinger2009-03-24-1/+1
| | | | | | | | | | | | | | Since the hardware can handle it, bump the default clocks from 80mhz SCLK and 398mhz CCLK to 100mhz SCLK and 498mhz CCLK. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: bf533-stamp: rewrite startup LED notificationsMike Frysinger2009-03-24-14/+73
| | | | | | | | | | | | | | Again, don't clobber pins that we aren't actually using, and use the common LED framework rather than our own hob-job-but-not-really-working. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: unify common ADI board settingsMike Frysinger2009-03-24-937/+719
| | | | | | | | | | | | | | | | Rather than duplicate the same ADI settings in every ADI board, create a common ADI config header and have all ADI boards start using that. This will also make merging the ~10 boards I have to forward port a lot easier. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: put memory into self-refresh before/after programming clocksMike Frysinger2009-03-23-82/+190
| | | | | | | | | | | | | | | | | | | | | | When initializing the core clocks, stick external memory into self-refresh. This gains us a few cool things: - support suspend-to-RAM with Linux - reprogram clocks automatically when doing "go" on u-boot.bin in RAM - make sure settings are stable before flashing new version - finally fully unify initialize startup code path between LDR/non-LDR Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: do not program voltage regulator on parts that do not have oneMike Frysinger2009-03-23-3/+20
| | | | | | | | | | | | | | Some newer Blackfins (like the BF51x) do not have an on-chip voltage regulator, so do not attempt to program the memory as if it does. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: setup a sane default EBIU_SDBCTL for SDRAM controllersMike Frysinger2009-03-23-0/+33
| | | | | | | | | | | | | | If the board config does not specify an explicit EBIU_SDBCTL value, set it up with sane values based on other configuration options. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: handle reboot anomaly 432Mike Frysinger2009-03-23-0/+6
| | | | | | | | | | | | | | | | | | | | | | Workaround anomaly 432: The bfrom_SysControl() firmware function does not clear the SIC_IWR1 register before executing the PLL programming sequence. Therefore, any interrupt enabled in the SIC_IWR1 register prior to the call to bfrom_SysControl() can prematurely terminate the idle sequence required for the PLL to relock properly. SIC_IWR0 is properly handled. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: kill off LDR jump blockMike Frysinger2009-03-23-19/+14
| | | | | | | | | | | | | | The Boot ROM uses EVT1 as the entry point so set that rather than having to use a tiny jump block in the default EVT1 location. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: simplify symbol_lookup() a bitMike Frysinger2009-03-23-1/+1
| | | | | | | | | | | | No need to skip a byte as the symbol table handles this. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: fix SIC_RVECT definition: it is 16bits, not 32bitsMike Frysinger2009-03-23-6/+6
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: drop SPORT_TX read helper macrosMike Frysinger2009-03-23-26/+0
| | | | | | | | | | | | | | The SPORT_TX registers cannot be read (the hardware will trigger an error), so drop the read helper macros. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: unify duplicate CPU port definitionsMike Frysinger2009-03-23-320/+314
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: drop now-unused CONFIG_SYS_BFIN_CMD_XXXMike Frysinger2009-03-23-6/+0
| | | | | | | | | | | | | | With the new CONFIG_XXX system and CONFIG_CMD_XXX handling, these defines are no longer used/needed. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: print out Flash: before checking itMike Frysinger2009-03-23-1/+1
| | | | | | | | | | | | | | | | If there is some problem in the flash init/checking code, it's nicer to see the message "Flash:" before crashing. This way the source of the problem is a bit more straightforward. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: safely flush data caches when in writeback modeMike Frysinger2009-03-23-0/+42
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: update lockbox api according to latest documentationMike Frysinger2009-03-23-35/+35
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: mark bfin_reset staticMike Frysinger2009-03-23-1/+1
| | | | | | | | | | | | The function is only used locally, so mark it static. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: spi: there is no PORTJ_FER MMR on BF537Sonic Zhang2009-03-23-5/+3
| | | | | | | | | | | | | | | | Since the PORTJ on the BF537 is peripheral-only (no GPIO functionality), then there is no PORTJ_FER register for us to worry about. Signed-off-by: Sonic Zhang <Sonic.Zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: fix jtag console tstcMike Frysinger2009-03-23-4/+11
| | | | | | | | | | | | | | | | | | | | The jtag tstc operation was checking the hardware to see if data is available from it (which is fine for the jtag getc operation), but the higher layers need to know whether any data is available. Since we have to read up to 4 bytes at a time from the hardware, the higher layers need to know they can consume the cached bytes as well. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: bf537-stamp: move CONFIG_POST handling to COBJS-$(...)Mike Frysinger2009-03-23-4/+2
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: unify net-related init codeMike Frysinger2009-03-23-10/+20
| | | | | | | | | | | | | | Unify all of the net-related init code in the common Blackfin board init code to clean up the ifdef mess a bit. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: fix SWRST/SYSCR register sizesMike Frysinger2009-03-23-9/+9
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: update anomaly listsMike Frysinger2009-03-23-11/+39
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Reduce OneNAND IPL common codeKyungmin Park2009-03-23-40/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | OneNAND IPL has common codes for RAM init, load data, and jump to 2nd bootloader, but it's common code used about 300~400 bytes. So board specific codes, such as lowlevel_init, can't has enough code. It make a difficult to implement OneNAND IPL. his patch make this common code as small as possible. and give lowlevel_init can have more codes. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Add multi-chip NAND support for the TQM8548 modulesWolfgang Grandegger2009-03-23-26/+11
| | | | | | | | | | | | | | | | | | This patches configures the NAND UPM-FSL driver with multi-chip support for the Micron MT29F8G08FAB NAND flash memory on the TQM8548 modules. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Add wait flags to support board/chip specific delaysWolfgang Grandegger2009-03-23-11/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The NAND flash on the TQM8548_BE modules requires a short delay after running the UPM pattern like the MPC8360ERDK board does. The TQM8548_BE requires a further short delay after writing out a buffer. Normally the R/B pin should be checked, but it's not connected on the TQM8548_BE. The corresponding Linux FSL UPM driver uses similar delay points at the same locations. To manage these extra delays in a more general way, I introduced the "wait_flags" field allowing the board-specific driver to specify various types of extra delay. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Add support for TQM-specific chip select logic to FSL-UPMWolfgang Grandegger2009-03-23-1/+5
| | | | | | | | | | | | | | | | | | For the NAND chips on the TQM8548 modules, a special chip-select logic is used. It uses dedicated address lines to be set via UPM machine address register (mar). This patch adds such support to the FSL-UPM driver. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Add multi chip support to the FSL-UPM driverWolfgang Grandegger2009-03-23-10/+40
| | | | | | | | | | | | | | | | | | | | | | This patch adds support for multi-chip NAND devices to the FSL-UPM driver. The "dev_ready" callback of the "struct fsl_upm_nand" is now called with the argument "chip_nr" to allow testing the proper chip select line. The NAND support of the MPC8360ERDK is updated as well. No other boards are currently using the FSL UPM driver. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Enable multi chip support in the NAND layerWolfgang Grandegger2009-03-23-7/+22
|/ | | | | | | | | | This patch adds support for NAND_MAX_CHIPS to the MTD NAND layer. Multi-chips devices are displayed as shown: Device 0: 2x NAND 512MiB 3,3V 8-bit, sector size 128 KiB Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-avr32Wolfgang Denk2009-03-23-686/+1342
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| * Merge branch 'evk1100-prep'Haavard Skinnemoen2009-03-23-0/+0
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| | * avr32: fix cacheflush.h location introducted by d8f2aa3298610bJean-Christophe PLAGNIOL-VILLARD2009-03-23-0/+0
| | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
| * | Merge branch 'mimc200'Haavard Skinnemoen2009-03-23-686/+1342
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| | * | Setup extra MIMC200 chip selectsMark Jackson2009-02-23-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added code to setup the extra Flash and FRAM chip selects as used on the MIMC200 board. V2 moves the init code from the common "cpu.c" file into the board specific setup file. Signed-off-by: Mark Jackson <mpfj@mimc.co.uk> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
| | * | MIMC200: tidy GCLK init codeMark Jackson2009-02-23-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the MIMC200 startup code to use the built-in (rather than hard-coded) funtions for setting up gclk outputs. We'll also move the code to the new, more-appropriate board_postclk_init() routine. Signed-off-by: Mark Jackson <mpfj@mimc.co.uk> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
| | * | Merge branch 'evk1100-prep' into nextHaavard Skinnemoen2009-02-23-124/+141
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| | | * AVR32: Must add NOPs after disabling interrupts for AT32UC3A0512ESOlav Morken2009-02-23-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AT32UC3A0512ES chip has a bug when disabling interrupts. As a workaround, two NOPs can be inserted. Signed-off-by: Gunnar Rangoy <gunnar@rangoy.com> Signed-off-by: Paul Driveklepp <pauldriveklepp@gmail.com> Signed-off-by: Olav Morken <olavmrk@gmail.com> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
| | | * AVR32: Make GPIO implmentation cpu dependentGunnar Rangoy2009-02-23-81/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are some differences in the implementation of GPIO in the at32uc chip compared to the ap700x series. Signed-off-by: Gunnar Rangoy <gunnar@rangoy.com> Signed-off-by: Paul Driveklepp <pauldriveklepp@gmail.com> Signed-off-by: Olav Morken <olavmrk@gmail.com> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
| | | * AVR32: Move addrspace.h to arch-directory, and move some functions from io.h ↵Olav Morken2009-02-23-38/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to addrspace.h The AVR32A architecture (which AT32UC3A-series is based on) has a different memory layout than the AVR32B-architecture. This patch moves addrspace.h to an arch-dependent directory in preparation for AT32UC3A-support. It also moves some address-space manipulation functions from io.h to addrspace.h. Signed-off-by: Gunnar Rangoy <gunnar@rangoy.com> Signed-off-by: Paul Driveklepp <pauldriveklepp@gmail.com> Signed-off-by: Olav Morken <olavmrk@gmail.com> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
| | | * AVR32: Make cacheflush cpu-dependentOlav Morken2009-02-23-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AT32UC3A series of processors doesn't contain any cache, and issuing cache control instructions on those will cause an exception. This commit makes cacheflush.h arch-dependent in preparation for the AT32UC3A-support. Signed-off-by: Gunnar Rangoy <gunnar@rangoy.com> Signed-off-by: Paul Driveklepp <pauldriveklepp@gmail.com> Signed-off-by: Olav Morken <olavmrk@gmail.com> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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