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* mtd: nand: omap: make am33xx/elm.c as common driver for all OMAPx and AMxxxx ↵pekon gupta2013-11-21-5/+28
| | | | | | | | | | | | | | | | | | platforms ELM hardware engine which is used for ECC error detection, is present on all latest OMAP SoC (like OMAP4xxx, OMAP5xxx, DRA7xxx, AM33xx, AM43xx). Thus ELM driver should be moved to common drivers/mtd/nand/ folder so that all SoC having on-chip ELM hardware engine can re-use it. This patch has following changes: - mv arch/arm/include/asm/arch-am33xx/elm.h arch/arm/include/asm/omap_elm.h - mv arch/arm/cpu/armv7/am33xx/elm.c drivers/mtd/nand/omap_elm.c - update Makefiles - update #include <asm/elm.h> - add CONFIG_NAND_OMAP_ELM to compile driver/mtd/nand/omap_elm.c and include in all board configs using AM33xx SoC platform. Signed-off-by: Pekon Gupta <pekon@ti.com>
* mtd: atmel_nand: use dev_xxx instead of printkWu, Josh2013-11-21-11/+11
| | | | Signed-off-by: Josh Wu <josh.wu@atmel.com>
* mtd: atmel_nand: don't print bit correction message in driverWu, Josh2013-11-21-2/+2
| | | | | | | Since for some MLC nand, bit errors happened too often. Just disable it to avoid noise Signed-off-by: Josh Wu <josh.wu@atmel.com>
* sama5d3xek: support larger than 4G nand flashWu, Josh2013-11-21-2/+3
| | | | Signed-off-by: Josh Wu <josh.wu@atmel.com>
* mtd: atmel_nand: enable PMECC support for 8k bytes page NAND flashWu, Josh2013-11-21-1/+9
| | | | | | increase the delay to 75us to support the 8k bytes page nand flash Signed-off-by: Josh Wu <josh.wu@atmel.com>
* board/c29xpcie: Add support of 8K page size NAND flashPrabhakar Kushwaha2013-11-21-4/+6
| | | | | | Defines constants required to support 8K page size NAND flash. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* mtd/ifc: Add support of 8K page size NAND flashPrabhakar Kushwaha2013-11-21-2/+109
| | | | | | | | | | | | Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
* mtd: move & update nand_ecclayout structure (plus board changes)Prabhakar Kushwaha2013-11-21-17/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_ecclayout is present in mtd.h at Linux. Move this structure to mtd.h to comply with Linux. Also, increase the ecc placement locations to 640 to suport device having writesize/oobsize of 8KB/640B. This means that the maximum oobsize has gone up to 640 bytes and consequently the maximum ecc placement locations have also gone up to 640. Changes from Prabhabkar's version (squashed into one patch to preserve bisectability): - Added _LARGE to MTD_MAX_*_ENTRIES This makes the names match current Linux source, and resolves a conflict between http://patchwork.ozlabs.org/patch/280488/ and http://patchwork.ozlabs.org/patch/284513/ The former was posted first and is closer to matching Linux, but unlike Linux it does not add _LARGE to the names. The second adds _LARGE to one of the names, and depends on it in a subsequent patch (http://patchwork.ozlabs.org/patch/284512/). - Made max oobfree/eccpos configurable, and used this on tricorder, alpr, ASH405, T4160QDS, and T4240QDS (these boards failed to build for me without doing so, due to a size increase). On tricorder SPL, this saves 2576 bytes (and makes the SPL build again) versus the new default of 640 eccpos and 32 oobfree, and saves 336 bytes versus the old default of 128 eccpos and 8 oobfree. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Vipin Kumar <vipin.kumar@st.com> [scottwood@freescale.com: changes as described above] Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Thomas Weber <weber@corscience.de> Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Cc: Stefan Roese <sr@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Tom Rini <trini@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
* driver/mtd/ifc: Read Status while programming NAND flashPrabhakar Kushwaha2013-11-13-5/+16
| | | | | | | | | | | | | | | | | as per controller description, "While programming a NAND flash, status read should never skipped. Because it may happen that a new command is issued to the NAND Flash, even when the device has not yet finished processing the previous request. This may result in unpredictable behaviour." IFC controller never polls for R/B signal after command send. It just return control to software. This behaviour may not occur with NAND flash access. because new commands are sent after polling R/B signal. But it may happen in scenario where GPCM-ASIC and NAND flash device are working simultaneously. Update the controller driver to take care of this requirement Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* MTD: atmel_nand: support for software BCH ECCBo Shen2013-11-13-0/+4
| | | | | | Add possible to use software BCH ECC for atmel nand driver Signed-off-by: Bo Shen <voice.shen@gmail.com>
* cm_t35: use scf0403 driverNikita Kiryanov2013-11-12-2/+59
| | | | | | | | Use scf0403 driver to add scf0403x LCD support for cm-t35 and cm-t3730 boards. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* omap3_dss: define DSS_ONOFFNikita Kiryanov2013-11-12-4/+5
| | | | | | | | | | | Add DSS_ONOFF to polarity defines Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Anatolij Gustschin <agust@denx.de>
* lcd: add DataImage SCF0403x LCD panel supportNikita Kiryanov2013-11-12-0/+308
| | | | | | | | | | | | Add SPI-based driver for DataImage SCF0403852GGU04 and SCF0403526GGU20 LCD panels. Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* spi: define SPI_XFER_ONCENikita Kiryanov2013-11-12-0/+1
| | | | | | | | | | | | | The flag combination "SPI_XFER_BEGIN | SPI_XFER_END" is a common use case of spi_xfer, and it can easily cause an already long line (spi_xfer takes 5 parameters) to go over the 80 character limit. define SPI_XFER_ONCE to be a shorter version of the above flag combination. Cc: Tom Rini <trini@ti.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* spi: omap3: add support for more word lengthsNikita Kiryanov2013-11-12-24/+82
| | | | | | | | | | | | | | | | | | Current implementation only supports 8 bit word lengths, even though omap3 can handle anything between 4 and 32. Update the spi interface to support changing the SPI word length, and implement it in omap3_spi driver to support the full range of possible word lengths. This implementation is backwards compatible by defaulting to the old behavior of 8 bit word lengths. Also, it required a change to the omap3_spi non static I/O functions, but since they are not used anywhere else, no collateral changes are required. Cc: Tom Rini <trini@ti.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* spi: omap3: remove semicolon from #defineNikita Kiryanov2013-11-12-1/+1
| | | | | | | | | | Remove unnecessary semicolon from #define SPI_WAIT_TIMEOUT Cc: Tom Rini <trini@ti.com> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Gerhard Sittig <gsi@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* video: bcm2835: respect the pitch valueAndre Heider2013-11-12-0/+11
| | | | | | | | | | | | | | | | Depending on the firmware's video options [1] the active SDTV or HDTV mode can yield a framebuffer with noncontiguous horizontal lines, giving a messed up display, for both, u-boot and the loaded kernel. Fix this by setting lcd_line_length to the pitch value of the configured framebuffer. [1] http://elinux.org/RPiconfig#Video_mode_options Signed-off-by: Andre Heider <a.heider@gmail.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
* lcd: allow overriding lcd_get_size()Anatolij Gustschin2013-11-12-3/+7
| | | | | | | | | | | | | | Remove the redundant lcd_line_length initialisation which sneaked in when an earlier version of the patch of commit 6d330719 has been rebased. Some lcd drivers need to setup lcd_line_length not from the panel_info parameters but by different means. Make the lcd_get_size() weak to allow setting lcd_line_length in a driver specific way. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Stephen Warren <swarren@wwwdotorg.org>
* ARM: bcm2835: add missing mbox overscan response fieldAndre Heider2013-11-12-0/+1
| | | | | | | | Add the missing "right" field to struct bcm2835_mbox_tag_overscan. Signed-off-by: Andre Heider <a.heider@gmail.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* MPC824x: remove obsolete "PN62" boardWolfgang Denk2013-11-11-990/+4
| | | | | | | | | | | The MPC824x processors have long reached EOL, and the PN62 board has not seen any board-specific updates for more than a decade. It is now causing build issues. Instead of wasting time on things nobody is interested in any more, we rather drop this board. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Wolfgang Grandegger <wg@grandegger.com> cc: Tom Rini <trini@ti.com>
* time: fix gcc warnings on MIPS64Daniel Schwierzeck2013-11-11-2/+2
| | | | | | | | | | | | | | | | | | Commit 8dfafdde88eb3e71d5569846396ae67a91017232 introduced new gcc warnings on MIPS64: time.c: In function 'tick_to_time': time.c:59:2: warning: comparison of distinct pointer types lacks a cast [enabled by default] time.c:59:2: warning: passing argument 1 of '__div64_32' from incompatible pointer type [enabled by default] In file included from time.c:10:0: ./u-boot-mips/include/div64.h:22:17: note: expected 'uint64_t *' but argument is of type 'long long unsigned int *' time.c: In function 'usec_to_tick': time.c:76:2: warning: comparison of distinct pointer types lacks a cast [enabled by default] time.c:76:2: warning: passing argument 1 of '__div64_32' from incompatible pointer type [enabled by default] In file included from time.c:10:0: ./u-boot-mips/include/div64.h:22:17: note: expected 'uint64_t *' but argument is of type 'long long unsigned int *' Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2013-11-11-298/+1256
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| * malta: arch/mips/include/asm/malta.h SPDX license tagPaul Burton2013-11-11-3/+2
| | | | | | | | | | | | | | | | This patch replaces the GPL-2.0 text with a GPL-2.0 SPDX-License-Identifier tag, and adds Imagination Technologies copyright following my recent changes. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: define CONFIG_MEMSIZE_IN_BYTESGabor Juhos2013-11-09-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The memsize environment variable must contain the memory size in bytes on the Malta board. Otherwise Linux will use wrong memory size which causes a kernel panic. Define CONFIG_MEMSIZE_IN_BYTES in malta.h to avoid that. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Paul Burton <paul.burton@imgtec.com>
| * malta: add myself to maintainersPaul Burton2013-11-09-2/+2
| | | | | | | | | | | | | | | | This patch adds me as a maintainer of the malta(el) board(s). I have access to physical Malta boards and the desire for U-boot to run well on them. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: add script & instructions to flash U-bootPaul Burton2013-11-09-0/+56
| | | | | | | | | | | | | | | | | | | | This patch adds a script which may be used with MIPS Navigator Console and a MIPS Nagivator Probe in order to flash U-boot to a MIPS Malta development board. Please see the newly added doc/README.malta for usage instructions. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: setup PIIX4 interrupt routePaul Burton2013-11-09-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | Without setting up the PIRQ[A:D] interrupt routes, PCI interrupts will be left disabled. Linux does not set up this routing but relies upon it having been set up by the bootloader, reading back the IRQ lines which the PIRQ[A:D] signals have been routed to. This patch routes PIRQA & PIRQB to IRQ 10, and PIRQC & PIRQD to IRQ 11. This matches the setup used by YAMON. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: store environment in flashPaul Burton2013-11-09-6/+9
| | | | | | | | | | | | | | | | | | Allow the environment to be stored in the monitor flash of a Malta board. The environment is stored in the final 128KB of the flash, which both leaves the majority of the flash available for U-boot code and also matches the location which YAMON uses. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: enable RTC supportPaul Burton2013-11-09-1/+14
| | | | | | | | | | | | | | | | | | This is actually required in order for a Linux kernel to boot successfully on a physical Malta board. Without enabling the RTC, a Malta Linux kernel will get stuck in its estimate_frequencies function on boot. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: disable L2 cachesPaul Burton2013-11-09-0/+7
| | | | | | | | | | | | | | | | | | | | Malta boards may be used with cores which support L2 caches, however U-boot does not yet support L2 cache for MIPS. Thus for the moment we'll disable L2 caches by setting the L2B bit in Config2. This is specific to MTI/Imagination MIPS cores which is why this is done for the Malta board rather than generically. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: remove cache size definitionsPaul Burton2013-11-09-4/+0
| | | | | | | | | | | | | | | | | | | | These will now be detected at runtime, allowing a single U-boot configuration to function correctly with different bitstreams. Without this you may need to re-configure, re-build and re-flash U-boot to your Malta if you flash a new bitstream with a different cache configuration to your old bitstream. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: enable CONFIG_PCNET_79C973, PCNET_HAS_PROM, CONFIG_CMD_DHCPPaul Burton2013-11-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This model of the pcnet is used in current Malta boards, at least in the Malta-R rev 3. Enable support for it. The Malta also has the ethernet controller PROM containing its MAC address, so enable support for that in order to read that MAC address. DHCP is a very useful feature to have available for many networks, enable support for it also. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: display "U-boot" on the LCD screenPaul Burton2013-11-09-0/+29
| | | | | | | | | | | | | | Displaying a message on the LCD screen is a simple yet effective way to show the user that the board has booted successfully. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: support for coreFPGA6 boardsPaul Burton2013-11-09-16/+594
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for running on Malta boards using coreFPGA6 core cards, including support for the msc01 system controller used with them. The system controller is detected at runtime allowing one U-boot binary to run on a Malta with either. Due to the PCI I/O base differing between Maltas using gt64120 & msc01 system controllers, the UART setup is modified slightly. A second UART is added so that there is one pointing at the correct address for each system controller. The Malta board then defines its own default_serial_console function to select the correct one at runtime. The incorrect UART will simply not function. Tested on: - A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both with and without an L2 cache. - QEMU. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * malta: setup super I/O UARTsPaul Burton2013-11-09-0/+89
| | | | | | | | | | | | | | | | On a real Malta the Super I/O needs to be configured before we are able to access the UARTs. This patch performs that configuration, setting up the UARTs in the same way that YAMON would. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * qemu-malta: rename to just "malta"Paul Burton2013-11-09-16/+16
| | | | | | | | | | | | | | | | | | This is in preparation for adapting this board to function correctly on a physical MIPS Malta board. The board is moved into an "imgtec" vendor directory at the same time in order to ready us for any other boards supported by Imagination in the future. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * pci.h: allow inclusion in assembly sourcePaul Burton2013-11-09-1/+5
| | | | | | | | | | | | | | | | | | This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * pcnet: enable the NOUFLO featurePaul Burton2013-11-09-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On relatively slow boards (such as the MIPS Malta with an FPGA core card) it can be extremely common for transmits to underflow - to the point where it appears they simply do not work at all. Setting the NOUFLO bit causes the ethernet controller to not begin transmission on the wire until a transmit start point is reached. Setting that transmit start point to the full packet will cause the controller to only transmit the packet once it has buffered it entirely thus preventing any transmit underflows from occuring and allowing the controller to function on slower boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * pcnet: add cache flushing & invalidationPaul Burton2013-11-09-0/+16
| | | | | | | | | | | | | | | | | | | | | | Ensure that the view of memory from the CPU & the ethernet controller is coherent at the various points where they exchange data. This prevents stale data from being transmitted or received, and prevents the driver from getting stuck waiting for the ethernet controller to update descriptors when in reality it has but the old values are being read from cache. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * pcnet: s/le16_to_cpu/cpu_to_le16/ in pcnet_sendPaul Burton2013-11-09-2/+2
| | | | | | | | | | | | | | This should cause no change to the generated code, but is semantically correct. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * pcnet: code style cleanupPaul Burton2013-11-09-125/+123
| | | | | | | | | | | | | | | | | | Fix up the code to match Documentation/CodingStyle. This is mostly removing extraneous spaces. No functional change is intended. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * mips32: detect L1 cache sizes if they're not definedPaul Burton2013-11-09-19/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For boards such as the MIPS Malta with an FPGA core card it is desirable to be able to detect the L1 cache sizes at runtime, since they are not dependant upon the board but on the FPGA bitstream in use. This patch performs that detection when the CONFIG_SYS_[DI]CACHE_SIZE macros are not defined by the board configuration. In cases where the sizes are detected this patch also removes the restriction that the I-cache & D-cache line sizes must be the same, as this is not necessarily true. If the cache sizes are defined by a configuration then they will be hardcoded as before, so this patch will not add overhead to such boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* | Merge branch 'iu-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-11-09-1172/+1730
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/arm926ejs/mxs/Makefile board/compulab/cm_t35/Makefile board/corscience/tricorder/Makefile board/ppcag/bg0900/Makefile drivers/bootcount/Makefile include/configs/omap4_common.h include/configs/pdnb3.h Makefile conflicts are due to additions/removals of object files on the ARM branch vs KBuild introduction on the main branch. Resolution consists in adjusting the list of object files in the main branch version. This also applies to two files which are not listed as conflicting but had to be modified: board/compulab/common/Makefile board/udoo/Makefile include/configs/omap4_common.h conflicts are due to the OMAP4 conversion to ti_armv7_common.h on the ARM side, and CONFIG_SYS_HZ removal on the main side. Resolution is to convert as this icludes removal of CONFIG_SYS_HZ. include/configs/pdnb3.h is due to a removal on ARM side. Trivial resolution is to remove the file. Note: 'git show' will also list two files just because they are new: include/configs/am335x_igep0033.h include/configs/omap3_igep00x0.h
| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-11-07-53/+819
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| | * wandboard: README: Include the quad versionFabio Estevam2013-11-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Wandboard quad was not ported into U-boot at the time of writing the README. Add it to the list of Wandboard variants. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * Revert "configs: imx: Make CONFIG_SYS_PROMPT uniform across FSL boards"Stefano Babic2013-11-04-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 178b8e15ade96c7bd59b9704b91ca51d27c391cd. Patch was merged too fast, without checking that another patch is fixing the reported issue globally - reverted. Signed-off--by: Stefano Babic <sbabic@denx.de>
| | * configs: imx: Make CONFIG_SYS_PROMPT uniform across FSL boardsFabio Estevam2013-10-31-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is no real benefit in adding the board name into U-boot's prompt. Use the simple "=> " prompt across FSL boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| | * i.MX6: nitrogen6x: fix erase size in 6x_upgrade.txtEric Nelson2013-10-31-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 6x_upgrade script is used to upgrade U-Boot in SPI-NOR on Nitrogen6x/SABRE Lite boards using U-Boot's 'sf' command. U-Boot is placed at offset 0x400 in flash, and the script currently only erases 0x50000 bytes. Since the current head is 319k, any additional features enabled in the configuration will exceed the space erased and cause errors re-programming the device. This patch increases the erase size to the full size of the region allocated for the U-Boot binary. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| | * ARM: mxs: Configure 2 Gbit DDR2 RAM for BG0900Christoph G. Baumann2013-10-31-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BG0900 module has 2Gbit DRAM module on it, adjust the DataBahn DRAM controller registers so the DRAM module will be correctly recognised. Signed-off-by: Christoph G. Baumann <c.baumann@ppc-ag.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| | * ARM: mxs: Enable DCDC converter for battery bootMarek Vasut2013-10-31-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case the board detected sufficient voltage for battery boot, make sure the DCDC converter is ON and the board is not running only from linregs, otherwise an instability will be observed. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
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