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* arm: socfpga: Enable DM and DM_SPIMarek Vasut2015-03-05-0/+6
| | | | | | | | | | | | | | Enable DM and DM_SPI support for both Cyclone 5 and Arria 5 boards, since they use drivers which require those. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* dt: socfpga: Import and enable Arria V DK DTSMarek Vasut2015-03-04-0/+111
| | | | | | | | | | | | | Import DTS for Arria V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* dt: socfpga: Import and enable Cyclone V DK DTSMarek Vasut2015-03-04-1/+84
| | | | | | | | | | | | | Import DTS for Cyclone V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* arm: socfpga: Add Altera Arria V DK supportMarek Vasut2015-03-04-0/+1043
| | | | | | | | | | | Add support for the Altera Arria V development kit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* arm: socfpga: Zap board_early_init_f()Marek Vasut2015-03-04-9/+0
| | | | | | | | | | | Zap this unused empty function, no point in having it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* arm: socfpga: Zap checkboard()Marek Vasut2015-03-04-10/+1
| | | | | | | | | | | | | Since all boards now have a DT, instead of hard-coding the board name into the U-Boot binary, read the board name from DT "model" property. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* arm: socfpga: Drop cyclone5 suffix from board file nameMarek Vasut2015-03-04-1/+1
| | | | | | | | | | | | Drop the _cyclone5 suffix from socfpga_cyclone5.c since this file will contain Arria 5 support as well. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* arm: socfpga: Add USB and UDC support for Cyclone V DKMarek Vasut2015-03-04-0/+9
| | | | | | | | | | | | | | | | Add support for USB host mode and USB device mode for the Cyclone V development kit and enable support for UMS (to export SD card as USB mass storage). The UMS is activated via 'ums 0 mmc 0' command, the system must be connected to a host PC via HPS USB port and SD card must be installed for this to work. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* arm: socfpga: Sync Cyclone V DK PLL configurationMarek Vasut2015-03-04-23/+11
| | | | | | | | | | | | | | | Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR). NOTE: This change is useless until we get proper SPL support, at which point this will likely need further rework. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* arm: socfpga: Sync Cyclone V DK pinmux configurationMarek Vasut2015-03-04-101/+101
| | | | | | | | | | | | Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* arm: socfpga: Minor coding style fixMarek Vasut2015-03-04-4/+4
| | | | | | | | | | | Replace multiple spaces with a single tab. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* Prepare v2015.04-rc3Tom Rini2015-03-03-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* mpc837xerdb: "fix Calling __hwconfig without a buffer" warningSinan Akman2015-03-02-1/+6
| | | | Signed-off-by: Sinan Akman <sinan@writeme.com>
* Merge branch 'xnext/zynqmp' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-03-02-0/+442
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| * arm64: Add Xilinx ZynqMP supportMichal Simek2015-03-02-0/+442
| | | | | | | | | | | | | | | | | | Add basic Xilinx ZynqMP arm64 support. Serial and SD is supported. It supports emulation platfrom ep108 and QEMU. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | atngwmkii: convert to generic boardAndreas Bießmann2015-03-02-0/+4
| | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | kconfig: remove unneeded U-Boot extension codeMasahiro Yamada2015-03-02-8/+0
| | | | | | | | | | | | | | This code was introduced to support the multiple .config configuration in U-Boot. We do not need it any more. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | serial: ns16550: Fix build error due to a typoAxel Lin2015-03-02-1/+1
| | | | | | | | | | | | | | Fix trivial typo. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Axel Lin <axel.lin@ingics.com>
* | MAINTAINERS, git-mailrc: Update my email addressTom Rini2015-03-02-17/+8
| | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* | armv7.h: Add <asm/io.h>Tom Rini2015-03-02-0/+1
| | | | | | | | | | | | | | With a389531 we now call readl() from this file so add <asm/io.h> so that we have a prototype for the function. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge git://git.denx.de/u-boot-usbTom Rini2015-03-02-34/+190
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| * | MAINTAINERS: Add F: drivers/usb/gadget to DFU custodian responsibilityLukasz Majewski2015-03-02-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After discussion during the last u-boot mini summit with USB maintainer - Marek Vasut - it has been decided, that gadget development should be coordinated by DFU custodian. Such patch formalizes current development status. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
| * | usb: gadget: fastboot: Set the Serial Number for Fastboot GadgetDileep Katta2015-02-25-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Configure the serial number using the serial# environment variable during the fastboot bind. This enables "fastboot devices" to return the serial number for the attached devices. Signed-off-by: Dileep Katta <dileep.katta@linaro.org> Acked-by: Steve Rae <srae@broadcom.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
| * | fastboot: Correct fastboot_fail and fastboot_okay stringsDileep Katta2015-02-25-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the string is copied without NULL termination using strncpy(), then strncat() on the next line, may concatenate the string after some stale (or random) data, if the response string was not zero-initialized. Signed-off-by: Dileep Katta <dileep.katta@linaro.org> Reviewed-by: Steve Rae <srae@broadcom.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
| * | fastboot: OUT transaction length must be aligned to wMaxPacketSizeDileep Katta2015-02-25-5/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OUT transactions must be aligned to wMaxPacketSize for each transfer, or else transfer will not complete successfully. This patch modifies rx_bytes_expected to return a transfer length that is aligned to wMaxPacketSize. Note that the value of wMaxPacketSize and ep->maxpacket may not be the same value, and it is the value of wMaxPacketSize that should be used for alignment. wMaxPacketSize is passed depending on the speed of connection. Signed-off-by: Dileep Katta <dileep.katta@linaro.org> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
| * | fastboot: Add USB cable detect checkRob Herring2015-02-25-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a check for USB cable attached and only enter fastboot when a cable is attached. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Steve Rae <srae@broadcom.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
| * | usb: gadget: fastboot: Add fastboot eraseDileep Katta2015-02-25-3/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the fastboot erase functionality, to erase a partition specified by name. The erase is performed based on erase group size, to avoid erasing other partitions. The start address and the size is aligned to the erase group size for this. Currently only supports erasing from eMMC. Signed-off-by: Dileep Katta <dileep.katta@linaro.org> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
| * | odroid: adjust get_dfu_alt_*() functions to new declarationsInha Song2015-02-25-14/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change is required after updated dfu_alt_system/boot declarations. Signed-off-by: Inha Song <ideal.song@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [Test HW: Odroid U3 (Exynos 4412)] Acked-by: Minkyu Kang <mk7.kang@samsung.com>
| * | dfu: samsung: move call to set_dfu_alt_info() to dfu common codePrzemyslaw Marczak2015-02-25-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This common call can be used for setting proper entities based on dfu command arguments. The config: CONFIG_SET_DFU_ALT_INFO, was used only for few configs, and now it is common. The board file should implement: - set_dfu_alt_info() function Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [Test HW: Odroid U3 (Exynos 4412)]
| * | fastboot: add support for "oem format" commandRob Herring2015-02-25-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add "oem format" command to write partition table. This relies on the env variable partitions to contain the list of partitions as required by the gpt command. Note that this does not erase any data other than the partition table. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Steve Rae <srae@broadcom.com>
| * | fastboot: add "fastboot oem" command supportMichael Scott2015-02-25-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add code stub to handle "fastboot oem __" command. As unlock is a common fastboot command, distinguish that it is not implemented. Signed-off-by: Michael Scott <michael.scott@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Tested-by: Steve Rae <srae@broadcom.com>
| * | usb: musb-new: omap2430: Reset the MUSB controller earlyPaul Kocialkowski2015-02-24-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting from USB peripheral boot, the bootrom will not properly deinit the MUSB controller, which doesn't clearly indicate an USB disconnection to the host and leaves U-Boot to deal with the state of the previous USB session. On some host controller drivers (e.g. xhci_hcd), this ends up in a failure during set address, caused by the lack of proper disconnection notification. Resetting the controller early in U-Boot notifies the host of the disconnection and doesn't hurt other use cases. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@ti.com>
| * | exynos: usb: make dwc3_set_mode to staticJoonyoung Shim2015-02-24-1/+1
| | | | | | | | | | | | | | | | | | | | | The dwc3_set_mode function is used only in drivers/usb/host/xhci-exynos5.c so make it to static. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
* | | Merge git://git.denx.de/u-boot-pxaTom Rini2015-03-02-61/+47
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| * | | pxa: colibri_pxa270: integrate latest validated register settingsMarcel Ziswiler2015-03-02-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Integrate latest validated register settings from Toradex WinCE BSP 4.2 working accross all module versions from early V1.x, V1.2D, V2.2B to V2.4A. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * | | pxa: colibri_pxa270: remove CONFIG_ENV_ADDR_REDUNDMarcel Ziswiler2015-03-02-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Usually not required for NOR flash. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * | | pxa: colibri_pxa270: fix wrong comment about voipac ethernet chipMarcel Ziswiler2015-03-02-1/+0
| | | | | | | | | | | | | | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * | | pxa: colibri_pax270: fix CONFIG_BOOTCOMMANDMarcel Ziswiler2015-03-02-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | While 'mmc init' is no longer required the address to bootm the kernel from NOR flash was wrong. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * | | pxa: colibri_pxa270: avoid overwriting factory configuration blockMarcel Ziswiler2015-03-02-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specify a CONFIG_BOARD_SIZE_LIMIT of 256 KB in order to avoid overwriting the factory configuration block located at offset 0x40000 in NOR flash. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * | | pxa: colibri_pxa270: disable loadb/s commands and long helpMarcel Ziswiler2015-03-02-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To save more than 20 KB of precious space in NOR flash get rid of the following configuration options: CONFIG_CMD_LOADB CONFIG_CMD_LOADS CONFIG_SYS_LONGHELP Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * | | pxa: colibri_pxa270: migrate to generic boardMarcel Ziswiler2015-03-02-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Migrate Toradex Colibri PXA270 to use CONFIG_SYS_GENERIC_BOARD. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | pxa: balloon3/colibri_pxa270: fix environment optionally being nowhereMarcel Ziswiler2015-03-02-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | I couldn't quite figure out whether or not CONFIG_SYS_ENV_IS_NOWHERE actually ever worked but nowadays this is called CONFIG_ENV_IS_NOWHERE. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * | | pxa: balloon3: fix comment about sdram banksMarcel Ziswiler2015-03-02-3/+3
| | | | | | | | | | | | | | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * | | pxa: balloon3: remove nowhere used symbol CONFIG_SYS_MEM_BUF_IMPMarcel Ziswiler2015-03-02-2/+0
| | | | | | | | | | | | | | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * | | remove nowhere used symbol CONFIG_SYS_CLKS_IN_HZMarcel Ziswiler2015-03-02-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Basically finish what the following commit started a long time ago: 488f5d8790c451fc527fe5d2ef218f2a5e40ea17 Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> For mx35pdk/woodburn: Acked-by: Stefano Babic <sbabic@denx.de>
| * | | pxa: fix wrong comment about vpac270 being the arch numberMarcel Ziswiler2015-03-02-2/+2
| | |/ | |/| | | | | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2015-03-01-35/+495
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| * | | Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800Doug Anderson2015-02-28-95/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It was found that the L2 cache timings that we had before could cause freezes and hangs. We should make things more robust with better timings. Currently the production ChromeOS kernel applies these timings, but it's nice to fixup firmware too (and upstream probably won't take our kernel hacks). This also provides a big cleanup of the L2 cache init code avoiding some duplication. The way things used to work: * low_power_start() was installed by the SPL (both at boot and resume time) and left resident in iRAM for the kernel to use when bringing up additional CPUs. It used configure_l2_ctlr() and configure_l2_actlr() when it detected it was on an A15. This was needed (despite the L2 cache registers being shared among all A15s) because we might have been the first man in after the whole A15 cluster was shutdown. * secondary_cores_configure() was called on at boot time and at resume time. Strangely this called configure_l2_ctlr() but not configure_l2_actlr() which was almost certainly wrong. Given that we'll call both (see next bullet) later in the boot process it didn't matter for normal boot, but I guess this is how L2 cache settings got set on 5420/5800 (but not 5250?) at resume time. * exynos5_set_l2cache_params() was called as part of cache enablement. This should happen at boot time (normally in the SPL except for USB boot where it happens in main U-Boot). Note that the old code wasn't setting ECC/parity in the cache enablement code but we happened to get it anyway because we'd call secondary_cores_configure() at boot time. For resume time we'd get it anyway when the 2nd A15 core came up. Let's make this a whole lot simpler. Now we always set these parameters in the same place for all boots and use the same code for setting up secondary CPUs. Intended net effects of this change (other than cleanup): * Timings go from before: data: 0 cycle setup, 3 cycles (0x2) latency tag: 0 cycle setup, 3 cycles (0x2) latency after: data: 1 cycle setup, 4 cycles (0x3) latency tag: 1 cycle setup, 4 cycles (0x3) latency * L2ACTLR is properly initted on 5420/5800 in all cases. One note is that we're still relying on luck to keep low_power_start() working. The compiler is being nice and not storing anything on the stack. Another note is that on its own this patch won't help to fix cache settings in an RW U-Boot update where we still have the RO SPL. The plan for that is: * Have RW U-Boot re-init the cache right before calling the kernel (after it has turned the L2 cache off). This is why the functions are in a header file instead of lowlevel_init.c. * Have the kernel save the L2 cache settings of the boot CPU and apply them to all other CPUs. We get a little lucky here because the old code was using "|=" to modify the registers and all of the bits that it's setting are also present in the new settings (!). That means that when the 2nd CPU in the A15 cluster comes up it doesn't actually mess up the settings of the 1st CPU in the A15 cluster. An alternative option is to have the kernel write its own low_power_start() code. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Exynos542x: Make A7s boot with thumb-mode U-Boot on warm resetAkshay Saraswat2015-02-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On warm reset, all cores jump to the low_power_start function because iRAM data is retained and because while executing iROM code all cores find the jump flag 0x02020028 set. In low_power_start, cores check the reset status and if true they clear the jump flag and jump back to 0x0. The A7 cores do jump to 0x0 but consider following instructions as a Thumb instructions which in turn makes them loop inside the iROM code instead of jumping to power_down_core. This issue is fixed by replacing the "mov pc" instruction with a "bx" instruction which switches state along with the jump to make the execution unit consider the branch target as an ARM instruction. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Exynos542x: Fix secondary core booting for thumbAkshay Saraswat2015-02-28-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When compiled SPL for Thumb secondary cores failed to boot at the kernel boot up. Only one core came up out of 4. This was happening because the code relocated to the address 0x02073000 by the primary core was an ARM asm code which was executed by the secondary cores as if it was a thumb code. This patch fixes the issue of secondary cores considering relocated code as Thumb instructions and not ARM instructions by jumping to the relocated with the help of "bx" ARM instruction. "bx" instruction changes the 5th bit of CPSR which allows execution unit to consider the following instructions as ARM instructions. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
generated by cgit v1.1 at 2024-12-22 16:06:32 +0000