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* ColdFire: Add DSPI support for MCF5227x and MCF5445xTsiChung Liew2009-07-14-673/+263
| | | | | | | | Remove individual CPU specific DSPI driver. Add required feature for the common DSPI driver in cpu_init and in platform configuration file. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
* Coldfire: Consolidate DSPI driverTsiChung Liew2009-07-14-0/+358
| | | | | | | Unify both MCF5227x and MCF5445x DSPI driver in CPU to driver/spi folder for common use. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
* ColdFire: Remove compiler warning messagesTsiChung Liew2009-07-14-1/+1
| | | | | | | Remove unused variables and printf type mismatch in lib_m68k/board.c Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
* ColdFire: Fix M53017EVB flash sizeTsiChung Liew2009-07-14-1/+1
| | | | | | Increase the flash size from 8MB to 16MB Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
* ColdFire: Add M5208EVB and MCF520x CPU supportTsiChung Liew2009-07-14-14/+1330
| | | | Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
* ColdFire: Update for M54451EVBTsiChung Liew2009-07-14-66/+82
| | | | | | | | Update serial boot DRAM's Internal RAM, vector table and DRAM in start.S, serial flash's read status command over SPI and NOR flash. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
* ColdFire: Update configuration file to use flash buffer writeTsiChung Liew2009-07-14-0/+5
| | | | | | | Update M52277EVB, M53017EVB and M54455EVB platform configuration file to use flash buffer write Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
* mpc5121ads: add JFFS2 and MTDPARTS support; adjust flash mapWolfgang Denk2009-07-14-8/+38
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* aria: add JFFS2 and MTDPARTS support; adjust flash mapWolfgang Denk2009-07-14-5/+34
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* aria: enable NAND flash supportWolfgang Denk2009-07-14-1/+24
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* MPC512x: fix typo in comment listing the NAND driver nameWolfgang Denk2009-07-14-2/+2
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* mecp5123: cleanup - remove dead codeWolfgang Denk2009-07-14-7/+0
| | | | | | | | Remove dead code that was obviously a left-over from copy & paste. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* aria: adjust memory controller initializationWolfgang Denk2009-07-14-13/+72
| | | | | | Needed for Rev. 2 silicon at 400 MHz Signed-off-by: Wolfgang Denk <wd@denx.de>
* MPC512x: factor out common codeWolfgang Denk2009-07-14-335/+191
| | | | | | | | | | | | | | Now that we have 3 boards for the MPC512x it turns out that they all use the very same fixed_sdram() code. This patch factors out this common code into cpu/mpc512x/fixed_sdram.c and adds a new header file, include/asm-ppc/mpc512x.h, with some macros, inline functions and prototype definitions specific to MPC512x systems. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* mecp5123: fix build errorWolfgang Denk2009-07-14-8/+5
| | | | | | | | | | The mecp5123 board did not compile because the MSCAN Clock Control Registers were missing; these got added, but as an array instead of 4 individual registers. Adapt the code so it builds. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* MPC512x: Add MSCAN1...4 Clock Control RegistersWolfgang Denk2009-07-14-4/+5
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* MPC512x: enabling NAND support requires CONFIG_SYS_64BIT_VSPRINTFWolfgang Denk2009-07-14-0/+4
| | | | | | | | | | When enabling NAND support for a board, one must also define CONFIG_SYS_64BIT_VSPRINTF because this is needed in nand_util.c for correct output. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* Merge branch 'master' of /home/wd/git/u-boot/masterWolfgang Denk2009-07-14-1915/+2617
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| * Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-07-13-618/+1474
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| | * Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-07-13-618/+1474
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| | | * versatile: update config and merge to cfi flash driverJean-Christophe PLAGNIOL-VILLARD2009-07-12-530/+51
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Peter Pearse <peter.pearse@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com>
| | | * versatile: specify the board type on the promptJean-Christophe PLAGNIOL-VILLARD2009-07-12-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Peter Pearse <peter.pearse@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com>
| | | * at91: Introduction of at91sam9g10 SOC.Sedji Gaouaou2009-07-12-7/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | AT91sam9g10 is an ARM 926ej-s SOC. It is an evolution of the at91sam9261 with a faster clock speed: 266/133MHz. Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
| | | * at91: Introduction of at91sam9g45 SOC.Sedji Gaouaou2009-07-12-22/+1221
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AT91sam9g45 series is an ARM 926ej-s SOC family clocked at 400/133MHz. It embeds USB high speed host and device, LCD, DDR2 RAM, and a full set of peripherals. The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES. On the board you can find 2 USART, USB high speed, a 480*272 LG lcd, ethernet, gpio/joystick/buttons. Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
| | | * pxa: fix CKEN_B register bitsDaniel Mack2009-07-12-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current defition for CKEN_B register bits is nonsense. Adding 32 to the shifted value is equal to '| (1 << 5)', and this bit is marked 'reserved' in the PXA docs. Signed-off-by: Daniel Mack <daniel@caiaq.de>
| | | * pxa: add clock for system bus 2 arbiterDaniel Mack2009-07-12-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This clock is needed for systems using the USB2 device unit or the 2d graphics accelerator. Signed-off-by: Daniel Mack <daniel@caiaq.de>
| | | * OMAP3 pandora: Fix CKE1 MUX setting to allow self-refreshGrazvydas Ignotas2009-07-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pandora is using both SDRC CSes. The MUX setting is needed for the second CS clock signal to allow the 2 RAM parts to be put in self-refresh correctly. Based on similar patch for beagle and overo by Jean Pihet and Steve Sakoman.
| | | * OMAP3 pandora: setup pulls for various GPIOsGrazvydas Ignotas2009-07-12-25/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Set pullups or pulldowns for GPIOs which need them. Disable them for others, which have external pulls. Also make disabled pull setting consistent (some pins had type set to "up" even if pull type selection was disabled).
| | | * OMAP3 pandora: setup pin mux for pins used on rev3 boardsGrazvydas Ignotas2009-07-12-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Setup pin mux for GPIO pins connected on rev3 or later boards. Also change NUB2 IRQ pin. This should not affect older boards because they don't have any nubs (analog controllers) attached to them.
| | | * OMAP3 pandora: pin mux cleanupGrazvydas Ignotas2009-07-12-25/+0
| | | | | | | | | | | | | | | | | | | | Remove configuration of not unused pins, effectively leaving them in safe mode.
| | | * arm: Kirkwood: bugfix: UART1 bar correctionPrafulla Wadaskar2009-07-12-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
| | | * nand: Add Marvell Kirkwood NAND driverPrafulla Wadaskar2009-07-08-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a NAND driver for the Marvell Kirkwood SoC's Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Scott Wood <scottwood@freescale.com>
| * | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-07-13-3/+8
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| | * | Merge branch 'master' of git://git.denx.de/u-boot-cfi-flashWolfgang Denk2009-07-13-3/+8
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| | | * | issue write command to base for JEDEC flashPo-Yu Chuang2009-07-13-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For JEDEC flash, we should issue word programming command relative to base address rather than sector base address. Original source makes SST Flash fails to program sectors which are not on the 0x10000 boundaries. e.g. SST39LF040 uses addr1=0x5555 and addr2=0x2AAA, however, each sector is 0x1000 bytes. Thus, if we issue command to "sector base (0x41000) + offset(0x5555)", it sends to 0x46555 and the chip fails to recognize that address. This patch is tested with SST39LF040. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-07-13-1136/+720
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| | * | | Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2009-07-13-1136/+720
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| | | * | | sh: Update pci config for Renesas r7780mp boardNobuhiro Iwamatsu2009-07-11-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | | * | | sh: Add support ESPT-GIGA boradNobuhiro Iwamatsu2009-07-11-0/+575
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ESPT-Giga is SH7763-based reference board. Board support is relatively sparse, presently supporting serial, gigabit ethernet, USB host, and MTD. More information (in Japanese) available at: http://www.cente.jp/product/cente_hard/ESPT-Giga.html Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | | * | | sh: Revised the build with newest compilerNobuhiro Iwamatsu2009-07-08-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The check of data became severe from newest gcc. This patch checked in gcc-4.2 and 4.3 . Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | | * | | sh3/sh4: rename config option TMU_CLK_DIVIDER to CONFIG_SYS_TMU_CLK_DIVJean-Christophe PLAGNIOL-VILLARD2009-07-08-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | | * | | sh3/sh4: fix CONFIG_SYS_HZ to 1000Jean-Christophe PLAGNIOL-VILLARD2009-07-08-27/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | | * | | sh: introduce clock frameworkJean-Christophe PLAGNIOL-VILLARD2009-07-08-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | | * | | sh: unify linker scriptJean-Christophe PLAGNIOL-VILLARD2009-07-08-775/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | all sh boards use the same cpu linker script so move it to cpu/$(CPU) that could be overwrite in following order SOC BOARD via the corresponding config.mk tested on r2dplus Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | | * | | sh: make the linker scripts more genericJean-Christophe PLAGNIOL-VILLARD2009-07-08-314/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | currently we need to sync the linker script enty and TEXT_BASE manualy and the reloc_dst is based on it instead provide it now from the ldflags tested on r2dplus Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| | | * | | sh7785lcr: fix out of tree buildJean-Christophe PLAGNIOL-VILLARD2009-07-08-3/+4
| | | | |/ | | | |/| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-07-13-9/+25
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| | * | | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-07-13-9/+25
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| | | * | | ppc4xx: Set default PCI device ID for 405EP boardsMatthias Fuchs2009-07-10-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code only sets the PCI vendor id to 0x1014 and leaved device id to 0x0000. Ths patch .... a) uses the correct PCI_VENDOR_ID_IBM macro for this b) sets the default device ID as stated in the UM to 0x0156 by using PCI_DEVICE_ID_IBM_405GP for this. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
| | | * | | ppc4xx: Move 405EP pci code from cpu_init_f() to __pci_pre_init()Matthias Fuchs2009-07-10-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves some basic PCI initialisation from the 4xx cpu_init_f() to cpu/ppc4xx/4xx_pci.c. The original cpu_init_f() function enabled the 405EP's internal arbiter in all situations. Also the HCE bit in cpc0_pci is always set. The first is not really wanted for PCI adapter designs and the latter is a general bug for PCI adapter U-Boots. Because it enables PCI configuration by the system CPU even when the PCI configuration has not been setup by the 405EP. The one and only correct place is in pci_405gp_init() (see "Set HCE bit" comment). So for compatibility reasons the arbiter is still enabled in any case, but from weak pci_pre_init() so that it can be replaced by board specific code. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
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