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* m28evk: Remove 'all' target from MakefileFabio Estevam2012-01-16-2/+0
| | | | | | | Remove 'all' target from Makefile, as this is unused code. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
* m28evk: Use GENERATED_GBL_DATA_SIZEFabio Estevam2012-01-16-1/+8
| | | | | | Use GENERATED_GBL_DATA_SIZE for calculating CONFIG_SYS_INIT_SP_OFFSET. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx28evk: Remove 'all' target from MakefileFabio Estevam2012-01-16-2/+0
| | | | | | | Remove 'all' target from Makefile, as this is unused code. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
* MX28: Fix MXSBOOT segfault if no params specifiedMarek Vasut2012-01-16-0/+3
| | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* i.mx6:imx6q: allign MAC address with burned-in orderingJason Liu2012-01-16-7/+9
| | | | | | | | | | | | | | | | For the i.mx6q, the burned-in MAC address will be the following odering, fuse: 0x620[7:0] MAC_ADDR[7:0] ---> mac[5] fuse: 0x620[15:8] MAC_ADDR[15:8] ---> mac[4] fuse: 0x620[23:16] MAC_ADDR[23:16] ---> mac[3] fuse: 0x620[31:24] MAC_ADDR[31:24] ---> mac[2] fuse: 0x630[7:0] MAC_ADDR[39:32] ---> mac[1] fuse: 0x630[15:8] MAC_ADDR[47:40] ---> mac[0] This patch also fix the error caculation for the fuse bank[0] address Signed-off-by: Jason Liu <jason.hui@linaro.org> Cc: Stefano Babic <sbabic@denx.de>
* mx28evk: Add initial support for MX28EVK boardFabio Estevam2012-01-16-0/+548
| | | | | | | | | | | Add initial support for Freescale MX28EVK board. Tested boot via SD card and by loading a kernel via TFTP through the FEC interface. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx28: Let dram_init be common for mx28Fabio Estevam2012-01-16-17/+24
| | | | | | | | Let dram_init function be a common function, so that other mx28 boards can reuse it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
* mx28: Let imx_get_mac_from_fuse be common for mx28Fabio Estevam2012-01-16-35/+46
| | | | | | | | | Let imx_get_mac_from_fuse function be a common function, so that other mx28 boards can reuse it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* net: imx: Add multi-FEC support for imx_get_mac_from_fuseFabio Estevam2012-01-16-12/+13
| | | | | | | | | | Add multi-FEC support for imx_get_mac_from_fuse by passing dev_id as a parameter. This feature is important on mx28 SoC for example that has two FEC ports. Cc: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* i.mx6q: mx6qarm2: Enable the usboh3 clockEric Nelson2012-01-16-1/+1
| | | | | | | | | Bits 0 and 1 of CCM_CCGR7 are the usboh3 clock enable bits. Enabling this clock is necessary for the USB download. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> CC: Jason Hui <jason.hui@linaro.org> Acked-by: Jason Hui <jason.hui@linaro.org>
* mx28: remove omap specific config optionsVeli-Pekka Peltola2012-01-16-6/+0
| | | | | | | | | | | Config options for OMAP are not used with i.MX28 so remove dead code. Signed-off-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* i.mx6q: arm2: Add the enet function supportJason Liu2012-01-16-2/+100
| | | | | | | | | This enable the network function on the i.mx6q armadillo2 board(arm2), thus we can use tftp to load image from network. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Jason Liu <jason.hui@linaro.org> Tested-by: Dirk Behme <dirk.behme@de.bosch.com>
* fec: add the i.mx6q enet driver supportJason Liu2012-01-16-1/+16
| | | | | | Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Jason Liu <jason.hui@linaro.org> Acked-by: Stefano Babic <sbabic@denx.de>
* i.mx: i.mx6q: Add the enet clock functionJason Liu2012-01-16-0/+5
| | | | | | Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Jason Liu <jason.hui@linaro.org> Acked-by: Stefano Babic <sbabic@denx.de>
* openrisc: Add MAINTAINERS entryStefan Kristiansson2012-01-13-0/+11
| | | | Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* openrisc: Add architecture to MAKEALLStefan Kristiansson2012-01-13-0/+5
| | | | Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* openrisc: Add openrisc-generic example boardStefan Kristiansson2012-01-13-0/+1238
| | | | Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* openrisc: Add support for standalone programsStefan Kristiansson2012-01-13-0/+14
| | | | Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* openrisc: Add board info printout to cmd_bdinfoStefan Kristiansson2012-01-13-0/+22
| | | | Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* openrisc: Add library functionsStefan Kristiansson2012-01-13-0/+403
| | | | Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* openrisc: Add cpu filesStefan Kristiansson2012-01-13-0/+923
| | | | Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* openrisc: Add architecture image supportStefan Kristiansson2012-01-13-0/+2
| | | | Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* openrisc: Add architecture header filesStefan Kristiansson2012-01-13-0/+1397
| | | | Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* Strip mkenvimageDavid Wagner2012-01-13-0/+1
| | | | Signed-off-by: David Wagner <david.wagner@free-electrons.com>
* post/Makefile: Only build FP post tests if enabled via CONFIG_SYS_POST_FPUKumar Gala2012-01-13-1/+1
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2012-01-13-109/+393
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of /home/wd/git/u-boot/custodians: fsl_lbc: add printout of LCRR and LBCR to local bus regs sbc8548: Fix up local bus init to be frequency aware sbc8548: enable support for hardware SPD errata workaround sbc8548: relocate fixed ddr init code to ddr.c file sbc8548: Make enabling SPD RAM configuration work sbc8548: Fix LBC SDRAM initialization settings sbc8548: enable ability to boot from alternate flash sbc8548: relocate 64MB user flash to sane boundary Revert "SBC8548: fix address mask to allow 64M flash" MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM eXMeritus HWW-1U-1A: Minor environment variable tweaks
| * Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2012-01-13-109/+393
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: fsl_lbc: add printout of LCRR and LBCR to local bus regs sbc8548: Fix up local bus init to be frequency aware sbc8548: enable support for hardware SPD errata workaround sbc8548: relocate fixed ddr init code to ddr.c file sbc8548: Make enabling SPD RAM configuration work sbc8548: Fix LBC SDRAM initialization settings sbc8548: enable ability to boot from alternate flash sbc8548: relocate 64MB user flash to sane boundary Revert "SBC8548: fix address mask to allow 64M flash" MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM eXMeritus HWW-1U-1A: Minor environment variable tweaks
| | * fsl_lbc: add printout of LCRR and LBCR to local bus regsPaul Gortmaker2012-01-13-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | It can be handy to have these in the output when trying to debug odd behaviour. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * sbc8548: Fix up local bus init to be frequency awarePaul Gortmaker2012-01-11-3/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code here was copied from the mpc8548cds support, and it wasn't using the CONFIG_SYS_LBC_LCRR define, and was just unconditionally setting the LCRR_EADC bit. Snooping with a hardware debugger also showed we had LCRR_DBYP set, since we were setting it based on a read of an uninitialized lcrr read via clkdiv. Borrow from the code in the tqm85xx.c support to add LBC frequency aware masking of these bits. This change will correct reliability issues associated with trying to use the 128MB of LBC 100MHz SDRAM on this board. Thanks to Keith Savage for assistance in diagnosing the root cause of this. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * sbc8548: enable support for hardware SPD errata workaroundPaul Gortmaker2012-01-11-7/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Existing boards by default have an issue where the LBC SDRAM SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51. After the hardware modification listed in the README is made, then the DDR2 SPD EEPROM appears at 0x53. So this implements a board specific get_spd() by taking advantage of the existing weak linkage, that 1st tries reading at 0x53 and then if that fails, it falls back to the old 0x51. Since the old dependency issue of "SPD implies no LBC SDRAM" gets removed with the hardware errata fix, remove that restriction in the code, so both LBC SDRAM and SPD can be selected. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * sbc8548: relocate fixed ddr init code to ddr.c filePaul Gortmaker2012-01-11-44/+49
| | | | | | | | | | | | | | | | | | | | | | | | Nothing to see here, just a relocation of the fixed ddr init sequence to live in the actual ddr.c file itself. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * sbc8548: Make enabling SPD RAM configuration workPaul Gortmaker2012-01-11-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, SPD configuration of RAM was non functional on this board. Now that the root cause is known (an i2c address conflict), there is a simple end-user workaround - remove the old slower local bus 128MB module and then SPD detection on the main DDR2 memory module works fine. We make the enablement of the LBC SDRAM support conditional on being not SPD enabled. We can revisit this dependency as the hardware workaround becomes available. Turning off LBC SDRAM support revealed a couple implict dependencies in the tlb/law code that always expected an LBC SDRAM address. This has been tested with the default 256MB module, a 512MB a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration worked fine in all cases. The default configuration remains to go with the hard coded DDR config, so the default build will continue to work on boards where people don't bother to read the docs. But the advantage of going to the SPD config is that even the small default module gets configured for CL3 instead of CL4. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * sbc8548: Fix LBC SDRAM initialization settingsPaul Gortmaker2012-01-11-20/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These were cloned from the mpc8548cds platform which has a different memory layout (1/2 the size). Set the values by comparing to the register file for the board used during JTAG init sequence: LSDMR1 0x2863B727 /* PCHALL */ LSDMR2 0x0863B727 /* NORMAL */ LSDMR3 0x1863B727 /* MRW */ LSDMR4 0x4063B727 /* RFEN */ This differs from what was there already in that the RFEN is not bundled in all four steps implicitly, but issued once as the final step. The other difference seen when comparing vs. the register file init, is that since the memory is split across /CS3 and /CS4, the dummy writes need to go to 0xf000_0000 _and_ to 0xf400_0000. We also rewrite the final LBC SDRAM inits as macros, as there is no real need for them to be a local variable that is modified on the fly at runtime. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * sbc8548: enable ability to boot from alternate flashPaul Gortmaker2012-01-11-27/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board has an 8MB soldered on flash, and a 64MB SODIMM flash module. Normally the board boots from the 8MB flash, but the hardware can be configured for booting from the 64MB flash as well by swapping CS0 and CS6. This can be handy for recovery purposes, or for supporting u-boot and VxBoot at the same time. To support this in u-boot, we need to have different BR0/OR0 and BR6/OR6 settings in place for when the board is configured in this way, and a different TEXT_BASE needs to be used due to the larger sector size of the 64MB flash module. We introduce the suffix _8M and _64M for the BR0/BR6 and the OR0/OR6 values so it is clear which is being used to map what specific device. The larger sector size (512k) of the alternate flash needs a larger malloc pool, otherwise you'll get failures when running saveenv, so bump it up accordingly. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * sbc8548: relocate 64MB user flash to sane boundaryPaul Gortmaker2012-01-11-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current situation has the 64MB user flash at an awkward alignment; shifted back from 0xfc00_0000 by 8M, to leave an 8MB hole for the soldered on boot flash @ EOM. But to switch to optionally supporting booting off the 64MB flash, the 64MB will then be mapped at the sane address of 0xfc00_0000. This leads to awkward things when programming the 64MB flash prior to transitioning to it -- i.e. even though the chip spans from 0xfb80_0000 to 0xff7f_ffff, you would have to program a u-boot image into the two sectors from 0xfbf0_0000 --> 0xfbff_ffff so that it was in the right place when JP12/SW2.8 were switched to make the 64MB on /CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_ffff) We also have to have three TLB entries responsible for dealing with mapping the 64MB flash due to this 8MB of misalignment. In the end, there is address space from 0xec00_0000 to 0xefff_ffff where we can map it, and then the transition from booting from one config to the other will be a simple 0xec --> 0xfc mapping. Plus we can toss out a TLB entry. Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot flash; this means we won't have to change it when the alternate config uses the full 64MB for booting, in TLB0. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * Revert "SBC8548: fix address mask to allow 64M flash"Paul Gortmaker2012-01-11-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit ccf1ad535ae1c0dc2d466235c668adbdfe3a55b7. The commit "SBC8548: fix address mask to allow 64M flash" essentially made this change: * OR6: - * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 + * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0 But this makes no sense, as section 13.3.1.2.1 in the MPC8548ERM v2 clearly indicates the masks: 1111_1111_1000_0000_0 8 Mbytes 1111_1100_0000_0000_0 64 Mbytes 1111_1000_0000_0000_0 128 Mbytes So the original value was correct, and the commit was invalid, causing a 128MB mapping for a 64MB flash device. The problem rears its head when trying to configure u-boot to have access to both flash, since the default memory map is: FB80_0000 – FF7F_FFFF 32-bits 64MB FLASH SODIMM FF80_0000 – FFFF_FFFF 8-bits 8MB FLASH By extending the mapping of the 64MB flash to 128MB, it now conflicts with the normal 8MB boot flash, causing issues. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBCPaul Gortmaker2012-01-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These boards were meaning to deploy this value: #define LCRR_DBYP 0x80000000 but were missing a zero, and hence toggling a bit that lands in an area marked as reserved in the 8548 reference manual. According to the documentation, LCRR_DBYP should be used as: PLL bypass. This bit should be set when using low bus clock frequencies if the PLL is unable to lock. When in PLL bypass mode, incoming data is captured in the middle of the bus clock cycle. It is recommended that PLL bypass mode be used at frequencies of 83 MHz or less. So the impact would most likely be undefined behaviour for LBC peripherals on boards that were running below 83MHz LBC. Looking at the actual u-boot code, the missing DBYP bit was meant to be deployed as follows: Between 66 and 133, the DLL is enabled with an override workaround. In the future, we'll convert all boards to use the symbolic DBYP constant to avoid these "count the zeros" problems, but for now, just fix the impacted boards. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROMKyle Moffett2012-01-11-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This EEPROM is hardware-write-protected and used to persist key information such as the serial number and MAC addresses even if the primary environment sector in NOR FLASH is overwritten. During manufacturing, the environment is initialized from Linux and then the key parameters copied to the EEPROM via U-Boot: env export -c -s 0x2000 $loadaddr serial# macaddr mac1addr mac2addr eeprom write $loadaddr 0x0000 0x2000 The chip is then locked via hardware for delivery. When doing a field U-Boot upgrade, the environment is erased and reset to the defaults to avoid problems with "hwconfig" changes, etc. After loading the new U-Boot image, the hardware data is reloaded: i2c dev 0 eeprom read $loadaddr 0x0000 0x2000 env import -c $loadaddr 0x2000 saveenv The first three commands are saved in the "restore_eeprom" variable for user convenience. (EG: "run restore_eeprom && saveenv") Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * eXMeritus HWW-1U-1A: Minor environment variable tweaksKyle Moffett2012-01-11-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the ethernet connections are internal links with specialized hardware and are not useful for "dhcp" or general-purpose networking; U-Boot should not be cycling through them. Force the primary external network interface in "ethprime" and disable the interface cycling with "ethrotate=no". Additionally, the environment variable "preboot" has its own config option and means something entirely different from what the HWW-1U-1A variable was intended for. Rename the board variable to "setbootargs" to avoid potential confusion. Finally, fix an incorrect address for the kernel in FLASH memory. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2012-01-13-1/+1
|\ \ \ | |/ / | | | | | | | | | * 'master' of /home/wd/git/u-boot/custodians: fix: error ATMEL_FIO_BASE undeclared, if use I2C_Soft on AT91
| * | Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2012-01-13-1/+1
| |\ \ | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-i2c: fix: error ATMEL_FIO_BASE undeclared, if use I2C_Soft on AT91
| | * | fix: error ATMEL_FIO_BASE undeclared, if use I2C_Soft on AT91esw@bus-elektronik.de2012-01-11-1/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | * Since AT91 name schema was changed to ATMEL_BASE_xxx, I2C_SOFT on AT91 devices fails with 'error: ATMEL_FIO_BASE undeclared' * change ATMEL_PIO_BASE to ATMEL_BASE_PIOA will fix this Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
* | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2012-01-13-922/+287
|\ \ \ | |/ / | | | | | | | | | | | | | | | | | | | | | * 'master' of /home/wd/git/u-boot/custodians: board/mpl/pati: use the CFI driver for the PATI board board/mpl/mip405: use the CFI driver for the MIP405/MIP405T board board/mpl/pip405: use the CFI driver for the PIP405 board board/mpl/common: remove the old legacy flash ppc4xx: Setup HICB on Io64
| * | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2012-01-13-922/+287
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-ppc4xx: board/mpl/pati: use the CFI driver for the PATI board board/mpl/mip405: use the CFI driver for the MIP405/MIP405T board board/mpl/pip405: use the CFI driver for the PIP405 board board/mpl/common: remove the old legacy flash ppc4xx: Setup HICB on Io64
| | * | board/mpl/pati: use the CFI driver for the PATI boardDavid Müller2012-01-09-6/+11
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Mueller <d.mueller@elsoft.ch> Signed-off-by: Stefan Roese <sr@denx.de>
| | * | board/mpl/mip405: use the CFI driver for the MIP405/MIP405T boardDavid Müller2012-01-09-7/+36
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Mueller <d.mueller@elsoft.ch> Signed-off-by: Stefan Roese <sr@denx.de>
| | * | board/mpl/pip405: use the CFI driver for the PIP405 boardDavid Müller2012-01-09-12/+38
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Mueller <d.mueller@elsoft.ch> Signed-off-by: Stefan Roese <sr@denx.de>
| | * | board/mpl/common: remove the old legacy flashDavid Müller2012-01-09-896/+182
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Mueller <d.mueller@elsoft.ch> Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Setup HICB on Io64Dirk Eibach2012-01-09-1/+20
| | |/ | | | | | | | | | | | | | | | | | | The FPGA High-Speed Interconnect Bus (HICB) is now setup by u-boot. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2012-01-13-437/+590
|\ \ \ | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of /home/wd/git/u-boot/custodians: mpc8313erdb: fix mtdparts address powerpc/83xx/km: add support for 8321 based tuge1 board powerpc/83xx/km: merge tuxa and tuda1 boards to tuxx1 powerpc/83xx/km: remove obsolete defines for tuda1 powerpc/83xx/km: update SDRAM parameters for km8321 boards mpc8313erdb: Enable GPIO support on the MPC8313E RDB mpc83xx: Add a GPIO driver for the MPC83XX family gpio: Replace ARM gpio.h with the common API in include/asm-generic gpio: Modify common gpio.h to more closely match Linux
generated by cgit v1.1 at 2024-12-03 15:40:46 +0000