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* ehci-mxc: Define host offsetsBenoît Thébaudeau2012-11-16-1/+3
| | | | | | | | | | Some MXC SoCs like the i.MX35 have hosts located at unusual offsets, so prepare to the introduction of i.MX35 support by defining the ehci-mxc hosts offsets at SoC level. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* ehci-mxc: Make i.MX25 EHCI configurableBenoît Thébaudeau2012-11-16-11/+67
| | | | | | | | | Use EHCI MXC configuration options for i.MX25. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Matthias Weisser <weisserm@arcor.de>
* ehci-mxc: Make EHCI power/oc polarities configurableBenoît Thébaudeau2012-11-16-4/+62
| | | | | | | | | | Make EHCI power and overcurrent polarities configurable. If not set, these new configurartions keep the default register values so that existing board files do not have to be changed. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* ehci-mx5: Add missing OC_DIS for i.MX53Benoît Thébaudeau2012-11-16-0/+24
| | | | | | | | The i.MX53 has MXC_H*_UCTRL_H*_OC_DIS_BIT bits to disable the oc pin. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* ehci-mx5: Fix *PM usage for i.MX53Benoît Thébaudeau2012-11-16-1/+6
| | | | | | | | The MXC_*_UCTRL_*PM_BIT bits are available only on i.MX51. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* ehci-mx5: Fix OPM usageBenoît Thébaudeau2012-11-16-2/+2
| | | | | | | | | MXC_OTG_UCTRL_OPM_BIT disables (masks) the power/oc pins if set, like MXC_H1_UCTRL_H1PM_BIT and MXC_H2_UCTRL_H2PM_BIT, not the opposite. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* ehci-mx5: Fix OC_DIS usageBenoît Thébaudeau2012-11-16-3/+3
| | | | | | | | | MXC_OTG_PHYCTRL_OC_DIS_BIT disables the oc pin if set, like MXC_H1_OC_DIS_BIT, not the opposite. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* ehci-mx5: Clean upBenoît Thébaudeau2012-11-16-19/+26
| | | | | | | | | | Clean up ehci-mx5: - Fix column alignments. - Fix comments. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* ehci-mxc: Clean upBenoît Thébaudeau2012-11-16-46/+40
| | | | | | | | | | | Clean up ehci-mxc: - Remove useless #if's. - Fix identation. - Issue a #error if used with an unsupported platform. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* mx31: Move EHCI definitions to ehci-fsl.hBenoît Thébaudeau2012-11-16-26/+22
| | | | | | | | | The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to ehci-fsl.h so that all MXC SoCs can use them. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* arch-mx6: add mx6dl_pins.hTroy Kisky2012-11-10-0/+149
| | | | | | | Only the values used in the sabrelite board are added currently. Add more as other boards use them. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* imx-common: cpu: add imx_ddr_sizeTroy Kisky2012-11-10-0/+52
| | | | | | | | | | Read memory setup registers to determine size of available ram. This routine works for mx53/mx6x I need this because when mx6solo called get_ram_size with a too large maximum size, the system hanged. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mx6: use CONFIG_MX6 instead of CONFIG_MX6QTroy Kisky2012-11-10-4/+7
| | | | | | | | | | Use CONFIG_MX6 when the particular processor variant isn't important. Reserve the use of CONFIG_MX6Q to specifically test for quad cores variant. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololiteTroy Kisky2012-11-10-17/+51
| | | | | | | | | | Previously, the same value was returned for both mx6dl and mx6solo. Check number of processors to differeniate. Also, a freescale patch says that sololite has its cpu/rev stored at 0x280 instead of 0x260. I don't have a sololite to verify. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* Merge git://git.denx.de/u-bootStefano Babic2012-11-10-29058/+23633
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| * Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2012-11-09-37/+14
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| | * microblaze: Fix compilation failure because of missing libdtsMichal Simek2012-11-08-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Microblaze platform can use CONFIG_OF_EMBED option but also it is necessary to support boards which don't want to use this option. U-Boot doesn't compile dts/libdts.o for #undef CONFIG_OF_EMBED case that's why it should be guarded by ifdef. Signed-off-by: Michal Simek <monstr@monstr.eu>
| | * microblaze: Remove asm/bitops.h from asm/posix_types.hMichal Simek2012-11-07-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch "include/linux/byteorder: import latest endian definitions from linux" (sha1: eef1cf2d5cf1cae5fb76713e912263dedf110aeb) Introduced a lot of compilation failures with unknow types. include/linux/byteorder/big_endian.h:45:1: error: unknown type name '__le64' include/linux/byteorder/big_endian.h: In function '__cpu_to_le64p': include/linux/byteorder/big_endian.h:47:18: error: '__le64' undeclared (first use in this function) include/linux/byteorder/big_endian.h:47:18: note: each undeclared identifier is reported only once for each function it appears in include/linux/byteorder/big_endian.h:47:25: error: expected ';' before '__swab64p' include/linux/byteorder/big_endian.h: At top level: include/linux/byteorder/big_endian.h:49:1: error: unknown type name '__le64' include/linux/byteorder/big_endian.h:53:1: error: unknown type name '__le32' include/linux/byteorder/big_endian.h: In function '__cpu_to_le32p': include/linux/byteorder/big_endian.h:55:18: error: '__le32' undeclared (first use in this function) include/linux/byteorder/big_endian.h:55:25: error: expected ';' before '__swab32p' include/linux/byteorder/big_endian.h: At top level: include/linux/byteorder/big_endian.h:57:1: error: unknown type name '__le32' include/linux/byteorder/big_endian.h:61:1: error: unknown type name '__le16' ... Removing asm/bitops.h solved this problem. Signed-off-by: Michal Simek <monstr@monstr.eu>
| | * microblaze: Flush caches before enabling themMichal Simek2012-11-07-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | Flushing caches is necessary because of soft reset which doesn't clear caches. Signed-off-by: Michal Simek <monstr@monstr.eu> Reviewed-by: Marek Vasut <marex@denx.de>
| | * microblaze: Fix byteorder for microblazeMichal Simek2012-11-07-23/+0
| | | | | | | | | | | | | | | | | | | | | | | | Just remove ancient code. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Stephan Linz <linz@li-pro.net> Reviewed-by: Marek Vasut <marex@denx.de>
| | * microblaze: Fix compilation warning in ext2_find_next_zero_bitMichal Simek2012-11-07-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ext2_find_next_zero_bit must be also static if __swab32 is also static. Warning: include/asm/bitops.h:369:22: warning: '__fswab32' is static but used in inline function 'ext2_find_next_zero_bit' which is not static [enabled by default] Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Stephan Linz <linz@li-pro.net>
| * | common/command.c: revert changes from commit 199adb60Anatolij Gustschin2012-11-08-8/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 199adb601ff34bdbbd0667fac80dfe0a87bffc2b "common/misc: sparse fixes" broke the help command trying to fix the sparse error "command.c:44:38: error: bad constant expression". As Henrik points out, the fix was bad because the commit used CONFIG_SYS_MAXARGS whereas the code intended to use the maximum number of commands (not arguments to a command). Revert command.c changes to the original code as asked by Wolfgang. Reported-by: Henrik Nordström <henrik@henriknordstrom.net> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * Merge branch 'master' of git://git.denx.de/u-boot-avr32Tom Rini2012-11-05-9/+0
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| | * avr32: allow multi block mmc access for all boardsAndreas Bießmann2012-11-02-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 1db7377a70a8d931c32648e717695133120d5456 fixes the gen_atmel_mci driver to be able to use multi block access for avr32. Therefore remove the setting which forces single block access. This also adds a huge performace gain for mmc access: ---8<--- Loading file "/boot/uImage" from mmc device 0:1 1830666 bytes read in 1293 ms (1.3 MiB/s) --->8--- vs. ---8<--- Loading file "/boot/uImage" from mmc device 0:1 1830666 bytes read in 237 ms (7.4 MiB/s) --->8--- Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: haavard.skinnemoen@atmel.com Cc: hans-christian.egtvedt@atmel.com Cc: mpfj@mimc.co.uk Cc: alex.raimondi@miromico.ch Cc: julien.may@miromico.ch Cc: egtvedt@samfundet.no Cc: havard@skinnemoen.net
| * | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-11-05-639/+5732
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| | * | socfpga/spl: Remove malloc.hVikram Narayanan2012-11-04-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove unused header Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
| | * | socfpga/spl: Remove timer_init from spl_board_initVikram Narayanan2012-11-04-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Timer is initialized already in board_init_r function in (common/spl/spl.c) No need to initialize it again Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Cc: Dinh Nguyen <dinguyen@altera.com>
| | * | arm: atmel: cpux9k2: add missing cache configsJens Scharsig (BuS Elektronik)2012-11-04-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * add CONFIG_SYS_CACHELINE_SIZE to eb_cpux9k2 board config header * dissable dcache (CONFIG_SYS_DCACHE_OFF) for eb_cpux9k2 Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
| | * | Merge remote-tracking branch 'u-boot-ti/master'Albert ARIBAUD2012-11-03-32/+3421
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| | | * | am335x: add initial AM335x IDK board supportMatthias Fuchs2012-11-02-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends the am335x_evm board for the AM335x IDK. The IDK board uses MII for the ethernet phy (same as Beaglebone board) and MMC0 for storage (but without card detect line). The IDK uses UART3 for console. So u-boot must be build with CONFIG_SERIAL4 and CONFIG_CONS_INDEX=4 or for the am335x_evm_uart3 board configuration as introduced by Andrew Bradfords recent patch series "am33xx: Enable UART {1,2,3,4,5}...". When using the IDK with console on UART0, those patches are not required. In this case the board slightly needs to be modified. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
| | | * | omap3: Rework board.c for !CONFIG_SYS_L2CACHE_OFFTom Rini2012-10-30-13/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_SYS_L2CACHE_OFF is defined we end up with a few warnings currently. Re-order functions so that we don't have that anymore. Signed-off-by: Tom Rini <trini@ti.com>
| | | * | am335x: add mux config for DDR3 version of beagleboneKoen Kooi2012-10-30-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the following boothang in SPL: Unknown board, cannot configure pinmux.### ERROR ### Please RESET the board ### Future commits will add pinmuxes for more on-board peripherals. Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
| | | * | eco5pk: Add new board and default configRaphael Assenat2012-10-30-0/+594
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Raphael Assenat <raph@8d.com> [trini: Squash boards.cfg / MAINTAINERS change into main patch] Signed-off-by: Tom Rini <trini@ti.com>
| | | * | New board support: Nokia RX-51 aka N900Pali Rohár2012-10-30-0/+2193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on previous work by: Alistair Buxton <a.j.buxton@gmail.com> Signed-off-by: Pali Rohár <pali.rohar@gmail.com> Cc: Ивайло Димитров <freemangordon@abv.bg>
| | | * | cfb_console: Add support for some ANSI terminal escape codesPali Rohár2012-10-30-9/+323
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add optional support for some ANSI escape sequences to the cfb_console driver. Define CONFIG_CFB_CONSOLE_ANSI to enable cursor moving, color reverting and clearing the cfb console via ANSI escape codes. Signed-off-by: Pali Rohár <pali.rohar@gmail.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| | | * | Add power bus message definitions in twl4030.hPali Rohár2012-10-30-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Code copied from linux kernel 3.0.0 from file include/linux/i2c/twl.h * commit 6523b148b44be38d89c2ee9865d34da30d9f5f1c Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
| | | * | arm bootm: Allow to pass board specified atagsPali Rohár2012-10-30-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Board can implement function setup_board_tags which is used for adding atags Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
| | | * | am335x_evm: Enable use of UART{1,2,3,4,5}Andrew Bradford2012-10-25-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add targets of am335x_evm_uart{1,2,3,4,5} to have serial input/output on UART{1,2,3,4,5} for use with the Beaglebone RS232 cape, am335x_evm daughterboard, and other custom configurations. Modify target for am335x_evm to include SERIAL1 and CONS_INDEX=1 options in order to clarify UART selection requirements. Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
| | | * | serial: ns16550: Enable COM5 and COM6Andrew Bradford2012-10-25-3/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Increase the possible number of ns16550 serial devices from 4 to 6. Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
| | | * | am33xx: Enable UART{1,2,3,4,5} pin-muxAndrew Bradford2012-10-25-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If configured to use UART{1,2,3,4,5} such as on the Beaglebone RS232 cape or on the am335x_evm daughterboard, enable the proper pin-muxing. Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
| | | * | am33xx: Enable UART{1,2,3,4,5} clocksAndrew Bradford2012-10-25-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If configured to use UART{1,2,3,4,5} such as on the Beaglebone RS232 cape or the am335x_evm daughterboard, enable the required clocks for the UART in use. Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
| | * | | arm720t: add back common.h includeAllen Martin2012-10-29-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add back common.h header that was removed in previous patch so that CONFIG_TEGRA can be evaluated correctly. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | serial: remove calls to serial_assign()Allen Martin2012-10-29-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove calls to serial_assign() that are failing now that it returns a proper error code. This calls were not actually doing anything because they passed the name of a stdio_dev when a serial_device name is exptectd. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | ARM: tegra: combine duplicate Makefile rulesStephen Warren2012-10-29-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rules to generate u-boot-{no,}dtb-tegra.bin were almost identical. Combine them into a single paremeterized rule. This will allow the next patch to edit a single rule, rather than being cut/paste twice. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | tegra20: initialize variable to avoid compiler warningAllen Martin2012-10-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize this variable to avoid a compiler warning about possible use of uninitialized variable with gcc 4.4.6. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | tegra: move to common SPL frameworkAllen Martin2012-10-29-77/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change tegra SPL to use common SPL framework. Any tegra specific initialization is now done in spl_board_init() instead of board_init_f()/board_init_r(). Only one SPL boot target is supported on tegra, which is boot to RAM image. jump_to_image_no_args() must be overridden on tegra so the host CPU can be initialized. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Tested-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | SPL: make jump_to_image_no_args a weak symbolAllen Martin2012-10-29-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change jump_to_image_no_args() to a weak symbol to allow override by SoC specific code. This is required by tegra because the SPL runs on a different CPU from the image it is loading, so tegra specific initialization is required to start the host CPU. Pass in spl_image as a parameter for the same reason. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Tom Rini <trini@ti.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | ARM: tegra: don't request GPIO from Seaboard's SPLStephen Warren2012-10-29-10/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Seaboard has a GPIO that switches an external mux between Tegra's debug UART and SPI flash. This is initialized from the SPL so that SPL debug output can be seen. Simplify the code that does this, and don't actually request the GPIO in the SPL; just program it. This saves ~4.5K from the size of the SPL, mostly BSS due to the large gpio_names[] table that is no longer required. This makes Seaboard's SPL fit within the current max size. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Allen Martin <amartin@nvidia.com> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | ARM: tegra: select between Seaboard/Ventana at compile timeStephen Warren2012-10-29-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Seaboard and Ventana are very similar boards, and so share the seaboard.c board file. The one difference needed so far is detected at run-time by calling machine_is_ventana(). This bloats the Ventana build with code that is never used. Switch to detecting Ventana at compile time to remove bloat. This shaves ~5K off the SPL size on Ventana, and makes the SPL fit within the max size. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | | ARM: tegra: derive CONFIG_SPL_MAX_SIZE instead of hard-coding itStephen Warren2012-10-29-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Tegra, the SPL and main U-Boot are concatenated together to form a single memory image. Hence, the maximum SPL size is the different in TEXT_BASE for SPL and main U-Boot. Instead of manually calculating SPL_MAX_SIZE based on those two TEXT_BASE, which can lead to errors if one TEXT_BASE is changed without updating SPL_MAX_SIZE, simply perform the calculation automatically. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Allen Martin <amartin@nvidia.com> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-12-12 23:39:58 +0000