| Commit message (Collapse) | Author | Age | Lines |
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The new command dumps the TLBCAM, the LAWs, and the BR/OR regs.
Add CONFIG_CMD_REGINFO to the config for all MPC85xx parts.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Add printing of LAWBARH/LAWBARL for FSL_CORENET platforms.
Signed-off-by: Becky Bruce <Beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The current code redefines functions based on FSL_CORENET_ vs not -
create macros/inlines instead that hide the differences.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This dumps out the contents of TLB1 on 85xx-based systems.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Extract the operation to read a tlb into a function - we will need
this later to print out the tlbs, and there's no point in duplicating
the code. Create a TSIZE_TO_BYTES macro to deal with the conversion
from the MAS field to an actual size instead of duplicating this in code.
There are a few misc other minor cleanups.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers. Merge
this into a single spot.
To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.
In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.
I have done a successful ppc build all and tested a board or two from
each processor family.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Some parts that have an Enhanced Local Bus Controller weren't
setting CONFIG_FSL_ELBC. Fix this so we can use this define
properly going forward (currently it's only used if PHYS_64BIT is
set, which meant not all platforms needed to have it set correctly).
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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We have several boards that use the same ICS307 CLK chip to drive the
System clock and DDR clock. Move the code into a common location so we
share it.
Convert the P2020DS board as the first to use the new common ICS307
code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Timur Tabi <timur@freescale.com>
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The various boards that have PIXIS FPGAs have slightly different
register definitions, however there is some common functionality (like
reset, ICS307 clk control, etc) that can be shared.
The struct definition exists for MPC8536DS, MPC8544DS, MPC8572DS,
MPC8610HPCD, and MPC8641HPCN boards.
Also fixed ngpixis to be __packed__ instead of aligned.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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If we explicitly disabled a core remove it from the dtb we pass on to
the kernel.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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We may have cpu-handles pointing to the cpu nodes we delete. If so we
should delete the handles as well.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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CONFIG_SYS_FSL_SEC_COMPAT is set to 2 for the SEC 2.x and SEC 3.x.
Parts with newer SEC h/w versions will increment the number to
accomodate incompatible code changes.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The example configuration files of nios2-generic board can generated
binary to run on the EP1C20, EP1S10, and EP1S40 boards. So the three
boards can be removed.
With nios2-generic approach, the fpga parameter header file can
be generated from hardware designs using tools. Porting u-boot for
nios2 boards is simplified. Vendors can supply their fpga parameter
file or patches to add a new nios2-generic board instance. There is
no need to include other boards support for nios2 in the u-boot
mainline.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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This patch enables the altera_spi and spi_flash drivers for the
nios2-generic board. It allows access to the EPCS/SPI flash on
the Altera EP1C20 board.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Tested-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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This patch adds the gpio usage request. The polarity is changed to
positive as suggested by Mike Frysinger.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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This will be used by nand_plat.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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This patch adds fdt support to boot linux, followed Michal's
work on microblaze.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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Follow the discussion of Charles Manning and Mike Frysinger.
Using gc_sections helps reduce image size.
Configuring for nios2-generic board...
Before,
text data bss dec hex filename
123979 3724 22892 150595 24c43 /tmp/u-boot/u-boot
After,
text data bss dec hex filename
115983 3800 22732 142515 22cb3 /tmp/u-boot/u-boot
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
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This patch add support for the ve8313 board based on
Freescale MPC8313 CPU.
- serial console on UART 1
- 128 MB DDR RAM
- 32 MB NOR Flash
- 16 MB NAND Flash
- Ethernet MII Mode over on TSEC0
- micrel ksz804 phy
- Hardware WDT MAX824
changes since v1
- Environment size = sector size
- use red. environment
- add comments from Kim Phillips
- add MAKEALL, MAINTAINERS entry
- Codingstyle issues fixed
- inserted original Copyrights
- PCI subsys vendor ID changed from 0x1057 (Motorola)
to 0x1957 (Freescale)
changes since v2
- add comments from Wolfgang Denk
- fix Codingstyle and some comments
- reworked WDT reset (just toggling the WD_TRIG pin)
- Environment size now 16KiB
- fixed RAMBOOT version
- fixed CONFIG_SYS_LOAD_ADDR
- renamed CONFIG_TSEC1_NAME to TSEC1
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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This patch provides support for MPC8308RDB development board from
Freescale with a minimal set of features:
Dual UART is supported
NOR flash is supported
Both TSEC Ethernet controllers are supported
PCI Express initialization is supported
The following features are enabled in configuration but not fully tested:
I2C (used to get the board revision)
I2C-connected RTC
VSC7385 switch
There is one (hopefully) minor issue: on soft reset the board sometimes
resets twice. I've not managed to find the fix for this problem yet.
As a workaround instruction cache can be disabled.
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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This patch adds basic support for Freescale MPC8308 CPU. Serial ports,
NOR flash and integrated Ethernet controllers are supported.
PCI Express is also supported. eSDHC, NAND and USB may work but aren't
tested (using ULPI PHY requires additional patch).
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Add edminiv2 board support for mv_egiga.
Add edminiv2 config to enable mv_egiga.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Add definitions and initialization in orion5x for mvgbe.
Add orion5x in mvgbe SoC includes.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Rename all references to kirkwood in mvgbe symbols
throughout the whole codebase.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Rename kirkwood_egiga.* to mvgbe.* and adjust makefile
and #include accordingly.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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This configuration option allows SoCs without random
generation capability to fill in local MACs with a fixed
rather than random value
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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* the following problems are met :
config was set to use the new driver as a default but
- RMII was not enabled for the new driver
- the new driver didn't compile with RMII enabled
- the new driver initialize a PHY at address O when the PHY of
this board is at 1 thus we get "AT91 EMAC RMII: No PHY present"
* to fix these problems, this patch :
- enable RMII for the new driver
- fix the wrong define used in the at91_emac.c
- allow the config file to set a default phy address (and use
0 as a default as in the actual at91_emac.c driver)
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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tested on cpuat91.
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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The current dm9000x driver accesses its memory mapped registers directly
instead of using the standard I/O accessors. This can cause problems on
Blackfin systems as the accesses can get out of order. So convert the
direct volatile dereferences to use the normal in/out macros.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Tested-by: Hoan Hoang <hnhoan@i-syst.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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The current OUTW function is always defined as a 16bit function, but this
doesn't work correctly when using the 32bit access mode. So define it as
a 32bit function when in 32bit mode so things work correctly on Blackfin
32bit LE systems.
Signed-off-by: Hoan Hoang <hnhoan@i-syst.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Some places in the current code equate the Marvell 88E1111 PHY as the family
when in reality it's a subpart of the Alaska family. So once we generalize
that, add support for the 88E1118 PHY.
Signed-off-by: Hoan Hoang <hnhoan@i-syst.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Also, remove all calls to eth_init() in boards that use MACB
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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The smc911x_detect function in /net/driver/net/smc911x.c
returns a 0 if everything was ok (a chip was found) and -1 else.
In the standalone example 'smc911x_eeprom' the return value
of smc911x_detect is interpreted in a different way
(0 for error, !0 as OK).
This leads to the error that the chip will not be detected.
Signed-off-by: Juergen Kilb <j.kilb@phytec.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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The Ethernet initialization functions are supposed to return the number of
devices initialized, so fix tsec_eth_init() so that they returns the number of
TSECs initialized, instead of just zero. This is safe because the return value
is currently ignored by all callers, but now they don't have to ignore it.
In general, if an function initializes only one device, then it should return
a negative number if there's an error. If it initializes more than one device,
then it should never return a negative number.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Device names should not contain non-printable characters like newlines.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Some commands operate on eth device names (like 'mii'), but those cannot
be passed on the command line as one argument. So detect devices like
these and warn about them so someone will fix it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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No compiled code change here, just drop the local PHY defines in favor of
the common standard ones.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Rather than hardcode specific phy addresses, search the possible phy
address space to find the first available phy. Also respect the normal
CONFIG_PHY_ADDR option for board porters to pick a specific address.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Signed-off-by: Hoan Hoang <hnhoan@i-syst.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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DRAM window mapping uses kirkwood-provided functions instead
of global gd as do other drivers--fix this.
Also, fix a typo in a comment
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Designware network driver support added.
This is a Synopsys ethernet controller
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Insert isb() sequence points to ensure DMA descriptors
are filled in and set up before actual DMA occurs.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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By defining CONFIG_M88E1111_DISABLE_FIBER boards can configure the
M88E1111 PYH to disable fiber. This is needed for an upcoming PPC460GT
based board, which has fiber/copper auto-selection enabled by default.
This doesn't seem to work. So we disable fiber in the PHY register.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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