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* ENGR00319241: imx6: pfuze: set pmic mode to decrease power number in DSM modeRobin Gong2014-06-20-0/+213
| | | | | | | Currently, kernel common regulator framework can't support setting pmic mode by common DTS, so move the related code to u-boot firstly. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00319151-2 HAB: Add the HAB image authentication to bootzYe.Li2014-06-20-0/+9
| | | | | | | Since the zImage is used at default, add the HAB image authentication support in bootz to authenticate zImage. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00319151-1 iMX6SX: Change default boot to use bootz and zImageYe.Li2014-06-20-57/+57
| | | | | | | Modified the default boot commands of all iMX6SX boards to use bootz and zImage. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00319003 iMX6SX:HAB: Fixed build break when enabling secure bootYe.Li2014-06-18-6/+6
| | | | | | | | | | | | | | | When enabling "CONFIG_SECURE_BOOT", the build broken on iMX6SX platform due to two problems. 1. The imximage tool in v2014 changes the command name of "SECURE_BOOT" to "CSF". Must update it in imximage.cfg scripts. 2. The iMX6SX uses "CONFIG_ROM_UNIFIED_SECTIONS", but some HAB API definitions are not defined and cause compile errors. (HAB_RVT_REPORT_EVENT_NEW, HAB_RVT_REPORT_STATUS_NEW, HAB_RVT_AUTHENTICATE_IMAGE_NEW, HAB_RVT_ENTRY_NEW, HAB_RVT_EXIT_NEW) Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-82 mx6sx arm2: Enable gis functionYe.Li2014-06-17-1/+7
| | | | | | | | Enable gis function for mx6sx 19x19 arm2 board Expand malloc buf pool to 16M. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-81 gis: Add gis moduleYe.Li2014-06-17-0/+641
| | | | | | | | Add gis module, current gis is support vadc input. Add power down function to lcdif driver. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-80 pxp: Add pxp moduleYe.Li2014-06-17-0/+324
| | | | | | | | Add pxp module. Support csc between YUV444 and RGB888 and scaling. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-79 csi: Add csi moduleYe.Li2014-06-17-0/+425
| | | | | | | Add csi module. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-78 vadc: Add vadc moduleYe.Li2014-06-17-0/+602
| | | | | | | | Add vadc module. Both PAL and NTSC mode can work. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-77 mx6 soc: Add vadc power up/down functionYe.Li2014-06-17-0/+58
| | | | | | | Add vadc power up/down function. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-76 mx6 clock: Add vadc clock enable functionYe.Li2014-06-17-0/+10
| | | | | | | Add vadc clock enable function. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-75 iMX6SX:SABRESD Support the reworked eMMC on SD4Ye.Li2014-06-17-0/+29
| | | | | | | | | | | | | | The eMMC chip on iMX6SX SABRESD board is DNP at default. HW rework is needed to weld it on the eMMC socket and disconnect SD card slot. The pins IOMUX of eMMC are different with SD card slot: 1. The eMMC uses 8 data pins, while SD card slot only uses 4 bits. 2. The CD pin used by SD card slot works as a data pin for eMMC. So adding a new u-boot target "mx6sxsabresd_emmc" for the eMMC support, rather than using the SD boot configuration. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-74 pfuze200: add clear print for pfuze200Ye.Li2014-06-17-3/+6
| | | | | | | | add clear print log to show pfuze200 or pfuze100 found on mx6qsabresd/ mx6slevk/mx6sx_19x19_arm2 boards. Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-73 iMX6SX:SABRESD/ARM2 Add "bmode" command supportYe.Li2014-06-17-0/+51
| | | | | | | | | | | | | Enable the "CONFIG_CMD_BMODE" and add BSP support. "bmode" supports to reboot: SD4, QSPI2 (SABRESD) SD2, SD3, eMMC, QSPI2, NAND, SPINOR (17x17 ARM2) SD1, QSPI2, SPINOR, EIMNOR (19x19 ARM2) BTW: Board rework is needed on ARM2 for NAND, SPINOR or EIMNOR boot. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-72 iMX6SX:SABRESD/19x19ARM2 Add splash screen support in BSPYe.Li2014-06-17-4/+374
| | | | | | | | | | | | Enable the video drivers and MXS LCDIF driver to support the splash screen on MX6SX SDB and 19x19 ARM2. Add BSP codes for video parameters and LCDIF/LVDS initialization. "panel" env is used for selecting the display panel. Set "panel" env to "Hannstar-XGA" for LVDS display. Set "panel" env to "MCIMX28LCD" for parallel LCD display. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-71 iMX6SX Update registers and clock for displayYe.Li2014-06-17-1/+445
| | | | | | Add registers and clock functions to enable/set LCDIF clock and LVDS. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-70 iMX6SX:Video Update MXS LCDIF driverYe.Li2014-06-17-13/+67
| | | | | | | | | | | | Add a new interface "mxs_lcd_panel_setup" to setup fb parameters and specifies the LCDIF controller for multiple controllers of iMX6SX. Pass fb parameters via "videomode" env remains work if the new interface is not called before video initialization. Modify LCDIF clock interface "mxs_set_lcdclk" to support multiple LCDIF controllers on iMX6SX. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-69 iMX6:SABREAUTO Change android NAND partition layoutYe.Li2014-06-17-1/+1
| | | | | | | Update NAND memory layout for match with new mfg tool. Signed-off-by: Ke Qinghua <qinghua.ke@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-68 iMX6SX:SABRESD: Add Android features supportYe.Li2014-06-17-2/+178
| | | | | | | Add BSP codes to mx6sxsabresd to support android uboot features: fastboot, booti and recovery Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-67 iMX6SX:SABRESD Disable the RDC temporarilyYe.Li2014-06-17-1/+1
| | | | | | | Disable RDC in u-boot till kernel implements it. Otherwise, crash may happen in kernel. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-66 iMX6SX:SABRESD Support M4 fast boot at early stageYe.Li2014-06-17-2/+12
| | | | | | | | | | | | | | | | T support M4 boot in 50 ms, kick start M4 at "board_early_init_f" stage where u-boot passes ARM and architecture initialization. Add a configuration "CONFIG_SYS_AUXCORE_FASTUP" for this feature enablement. And a build config "mx6sxsabresd_m4fastup". Adjust the default M4 image address to 0x78000000 represented by "CONFIG_SYS_AUXCORE_BOOTDATA". When M4 fast boot is enabled, RDC should be enabled together and the QSPI driver must turn off, because M4 is running on QSPI flash in XIP. Setup this relationship by configurations. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-65 iMX6SX:SABRESD Add RDC settings to BSPYe.Li2014-06-17-0/+14
| | | | | | | | | | | According to the SRS, in the M4 CAN demo, the GPIO group1 will be shared between A9 and M4. At A9 side, the pins 0, 1, 2, 3 are used. M4 also uses one pin in its application. To synchronize the registers setttings of GPIO1, must enable RDC and RDC semaphore on the GPIO1. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-64 iMX6SX: Add MX6SX SABRE SD board supportYe.Li2014-06-17-0/+1244
| | | | | | | | | | | | Add BSP codes for iMX6SX SABRE SD board to support SD/MMC, USB, QSPI2 NOR Flash, Ethernet, I2C, PMIC and M4 command boot(bootaux). Add board build targets of SABER SD for boot device: mx6sxsabresd --- SD/MMC mx6sxsabresd_qspi2 --- QuadSPI2 NOR flash Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-63 iMX6SX: Add MX6SX 19x19 LPDDR2 ARM2 board supportYe.Li2014-06-17-0/+283
| | | | | | | | Add script "imximage_lpddr2.cfg" for DDR controller settings of LPDDR2. Modify "plugin.S" for LPDDR2. Add build target for 19x19 LPDDR2 ARM2 board. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-62 iMX6SX: Add MX6SX 19x19 DDR3 ARM2 board supportYe.Li2014-06-17-0/+950
| | | | | | | | | | | | | | | | | | | Add BSP codes for iMX6SX 19x19 DDR3 ARM2 board to support SD/MMC, USB, QSPI2 NOR Flash, SPI NOR flash, WEIM NOR Flash, Ethernet, I2C, PMIC and M4 command boot(bootaux). Some features has conflicts, so can't be enabled at same time: WEIM-NOR <---> QSPI pin conflict QSPI <---> SPI-NOR u-boot driver conflict SPI-NOR <---> SD2 pin conflict Add board build targets of 19x19 DDR3 ARM2 for boot device: mx6sx_19x19_ddr3_arm2 --- SD/MMC/eMMC mx6sx_19x19_ddr3_arm2_spinor --- SPINOR on ECSPI4 CS0 mx6sx_19x19_ddr3_arm2_eimnor --- WEIM NOR flash mx6sx_19x19_ddr3_arm2_qspi2 --- QuadSPI2 NOR flash Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-61 iMX6SX: Add MX6SX 17x17 ARM2 board supportYe.Li2014-06-17-0/+1412
| | | | | | | | | | | | | | | | | | | Add BSP codes for iMX6SX 17x17 ARM2 board to support SD/MMC, USB, QSPI2 NOR Flash, SPI NOR flash, NAND Flash, Ethernet, I2C ,PMIC and M4 command boot (bootaux). Some features has conflicts, so can't be enabled at same time: QSPI <---> NAND pin conflict QSPI <---> SPI-NOR u-boot driver conflict SPI-NOR <---> SD2 pin conflict Add board build targets of 17x17 ARM2 for boot device: mx6sx_17x17_arm2 --- SD/MMC/eMMC mx6sx_17x17_arm2_spinor --- SPINOR on ECSPI4 CS0 mx6sx_17x17_arm2_nand --- NAND flash mx6sx_17x17_arm2_qspi2 --- QuadSPI2 NOR flash Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-60 GPIO: Modify driver mxc_gpio to support RDC SemaphoresYe.Li2014-06-17-0/+50
| | | | | | | | | | | | For GPIO group which shared by multiple masters, it may set in RDC to shared and semaphore required. Before access the GPIO register, the GPIO driver must get the RDC semaphore, and release the semaphore after the GPIO register access. When CONFIG_MXC_RDC is set, the features related to RDC semaphores is enabled in mxc_gpio driver. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-59 iMX6SX: Add RDC mappings of masters and peripheralsYe.Li2014-06-17-0/+159
| | | | | | | Add the definitions for the RDC mappings on iMX6SX and include this file to "imx-rdc.h" Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-58 RDC: Add an iMX platform driver for RDC-SEMAYe.Li2014-06-17-0/+319
| | | | | | | | | | | | | | The RDC driver provides interfaces for setting peripherals and masters at BSP initialization, before using the peripherals driver. Another interfaces for lock/unlock RDC semaphore and permission check. The driver assumes boot CPU which runs u-boot is in Domain 0 (default setting on boot). Users should not set it to other domains. The peripherals ID and masters ID may change on different chip, each should provide definitions of the IDs and be included in "imx-rdc.h". Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-57 iMX6SX: Add M4 boot support at soc levelYe.Li2014-06-17-0/+30
| | | | | | | | | Implement the override function "arch_auxiliary_core_up" to boot Cortex-M4 by executing command "bootaux". The parameter "boot_private_data" points to fields where stores the stack address and PC address for M4 to run. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-56 CMD: Add new command "bootaux" to boot auxiliary coreYe.Li2014-06-17-0/+43
| | | | | | | | | | | To boot a auxiliary core in asymmetric multicore system, introduce the new command "bootaux" to do it. Example of boot auxliary core from 0x70000000 where stores the boot head information that should be parsed by each core. "bootaux 0x70000000" Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-55 iMX6SX: add debug monitor supportYe.Li2014-06-17-0/+29
| | | | | | | | | | | Debug monitor will print out last failed AXI access info when system reboot is caused by AXI access failure, only works when debug monitor is enabled. Enable this module on i.MX6SX. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-54 iMX6SX/SL: Modify SOC to support two ENETYe.Li2014-06-17-6/+97
| | | | | | | | | | | | | | | | | | | | | iMX6SX has different enet system clocks with iMX6SL, and has two ENET controllers. So update clocks and soc APIs accordingly to support this features. 1. Modify the clock API "enable_enet_clock" to enable enet system clock for enet controllers. 2. Enet RGMII TX clock source may come from external or internal PLL. By default, use the external phy CLK_25M output as TX clock source. When using internal PLL as source, the function enable_fec_anatop_clock must be called to enable clock for each enet controller. 3. Modify the MAC address function "imx_get_mac_from_fuse" to get either ENET MAC address. 4. Add configuration "CONFIG_FEC_MXC_25M_REF_CLK" to enable ENET 25Mhz reference clock. 5. Modify imx6slevk BSP to fit the new APIs. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-53 ENET:FEC Update fec_mxc driver for iMX6SXYe.Li2014-06-17-5/+14
| | | | | | | | | | | | | | 1. iMX6SX enet rx have 64 bytes alignment limitation for DMA transfer. For i.MX6SX platform, need to add below define in config file: #define CONFIG_FEC_DMA_MINALIGN 64 2. Change to check READY bit in BD, not check the TDAR. On iMX6SX, FEC will clear the TDAR prior than the READY bit of last BD. Since fec driver only prepare two BD for transmit, this cause the BD send failed at the third packet. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-52 imximage: Add QuadSPI bootYe.Li2014-06-17-0/+8
| | | | | | | | Adding QuadSPI boot support to imximage tool. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-51 iMX6SX: Add QuadSPI clock enable functionYe.Li2014-06-17-0/+45
| | | | | | | Enable the clock for QuadSPI controllers. Must be called at initialization. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-50 QuadSPI: Add Freescale QuadSPI driverYe.Li2014-06-17-0/+783
| | | | | | | | | | | | | | | | | | | | | | | | | | Enable the Quadspi read/write/erase functions. Add two configurations "CONFIG_QSPI_BASE" and "CONFIG_QSPI_MEMMAP_BASE" for QSPI registers base and AHB memory base. Use "bus" and "cs" parameters to denote 4 flash chip connected on one QuadSPI: SFA1: bus 0, cs 0 SFA2: bus 0, cs 1 SFB1: bus 1, cs 0 SFB2: bus 1, cs 1 Currently in uboot, the SPI flash framework does not have way to notify the flash size to the driver. It brings a problem for QSPI driver to set the memory map space of each chip. In this patch, we fix the mem map space of each chip to 64MB(total is 256MB). So for each flash device, driver support 64MB at most. In addition, because u-boot SPI flash framework only supports 24bits address mode, and uses EAR register to switch bank for flash larger than 16MB. The QuadSPI does not support this way when reading data from AHB address. Thus, only lower 16MB is supported. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Allen Xu <b45815@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-49 SD/MMC: Update fsl_esdhc driver for iMX6SXYe.Li2014-06-17-0/+13
| | | | | | | | The reset value of "uSDHCx_INT_STATUS_EN" register is changed to 0 on iMX6SX. So the fsl_esdhc driver must update to set the register, otherwise no state can be detected. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-48 iMX6SX: Add iMX6SX SoC supportYe.Li2014-06-17-17/+2149
| | | | | | | | | | | Adding clks, pinmux, memory map, etc for iMX6SoloX. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-47 i.mx6:arm2/slevk Enable the CONFIG_SYS_GENERIC_BOARDYe.Li2014-06-17-0/+2
| | | | | | | Using the CONFIG_SYS_GENERIC_BOARD for imx6 arm2 board and imx6slevk to sync the deprecation process for generic board on upstream. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-46 i.mx6slevk: Enable SPI NOR flash at defaultYe.Li2014-06-17-2/+2
| | | | | | | | | Default imx6slevk BSP supports SPI NOR flash read, write and erase by using "sf" command. The "mx6slevk_spinor" builds the uboot that can be booted from SPI NOR flash and stored the environments variables in it. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-45 ARM:imx6:sabreauto Add USB HOST BSP supportYe.Li2014-06-17-26/+117
| | | | | | | | | | | | Sabreauto board has pin conflict (pin EIM_D18) between NOR flash and i2c3. To enable the USB host, the i2c3 must be used to operate the max7310 IO expander to output the VBUS power. As SPINOR is enabled at default, it is impossible to use USB host at same time. Thus, remove the SYS_USE_SPINOR from sabreauto configurations to disable SPINOR. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-44 imx6:USB: Update EHCI driver for OTG lines compatibilityYe.Li2014-06-17-25/+6
| | | | | | | | | | | To be compatible with more USB otg lines which has micro port B to connect imx6 OTG port when imx6 working at host mode, remove the checking for the OTG ID with the init type. Only use the init type for the power and controller initialization. Use same EHCI register base address for various imx6 platform. Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-43 ARM:imx6 Enable OCOTP driver and fuse commandYe.Li2014-06-17-0/+12
| | | | | | | | | | | | | Enable the fuse command config "CONFIG_CMD_FUSE" and OCOTP driver "CONFIG_MXC_OCOTP" for imx6. Users can use "sense" and "prog" to access the fuse directly, or use "read" and "override" to access shadow registers. Supported boards: mx6qdlsabresd, mx6qdlsabreauto, mx6qdlarm2, mx6slevk Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-42 i.mx6:sabreauto/sabresd/slevk Add Android build targetsYe.Li2014-06-17-0/+10
| | | | | | | Add build targets for enabling android support on i.mx6sabreauto/sabresd and i.mx6slevk boards Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-41 i.mx6:sabresd/sabreauto/slevk Fix build break for android ↵Ye.Li2014-06-17-1/+98
| | | | | | | | | | support Add the android header file "mx6slevkandroid.h" for imx6slevk android support. Fix header file and pin name problems in BSP codes. Remove build warning in cmd_fastboot.c Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-40 i.mx6dl: arm2: add the i.MX6DL arm2 board supportYe.Li2014-06-17-2/+386
| | | | | | | | | | | | | | | | This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2 shared the same board with i.MX6Q ARM2 board since the i.MX6DL is pin-pin compatible with i.MX6Q. The patch also support the DDR 32-BIT mode option. Please define CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT mode.But due to the board design, it's 64bit DDR buswidth physically, so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it. The patch has been tested on the i.MX6Q and i.MX6DL arm2 board. Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-39 Splash screen: correct i.MX6dl ipu hsp clock rateYe.Li2014-06-17-0/+4
| | | | | | | | | | | i.MX6dl ipu hsp clock rate is 270MHz in kernel. In uboot, i.MX6dq ipu hsp clock rate is 264MHz, and i.MX6dl ipu hsp clock rate is 198MHz. Correct i.MX6dl ipu hsp clock rate, display will get correct pixel clock now. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-38 MX6 Sabreauto:Add IPUv3 splash screen supportYe.Li2014-06-17-16/+217
| | | | | | | | | | | | | | | | This patch adds IPUv3 splash screen support for the MX6Q/SDL Sabreauto platforms. The default display is the Hannstar-XGA LVDS panel. Users may set the uboot variable 'panel' to be 'HDMI' to switch to use HDMI splash screen. To avoid duplicate configures on different sabre platforms, this patch moves the IPUv3 splash screen relevant configures to the head file 'mx6qsabre_common.h'. Also, this patch modifies the condition to build in EPDC splash screen feature in order to avoid the build break due to the migration of the IPUv3 splash screen relevant configures. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* ENGR00315894-37 MX6 SabreSD: Correct IPU DI pix fmt for LDBYe.Li2014-06-17-12/+3
| | | | | | | | | | | | | The DC mapping for LVDS666 is different from that for RGB666. Currently, we set IPU DI pixel format to be LVDS666 and set LDB data width to be 24bit. This happens to make the display work normally somehow. But, the two configurations are wrong and don't match with each other. This patch corrects the IPU DI output pixel format from LVDS666 to RGB666 and LDB data width from 24bit to 18bit. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
generated by cgit v1.1 at 2024-12-28 10:43:33 +0000