summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* wandboard: Add support for Carrier Board MicroSD cardOtavio Salvador2013-04-25-7/+60
| | | | | | | | Allow use of the carrier board MicroSD card available in the Wandboard; this allow for loading alternative system from the other card for testing or upgrade proposes. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* wandboard: Add card detection for SOM MicroSD cardOtavio Salvador2013-04-25-0/+19
| | | | | | | | This add support to identify if the card is connected or not; so it does not try to communicate with the controller if no card is available. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* wandboard: Add update_sd_firmware supportOtavio Salvador2013-04-25-0/+16
| | | | | | | This allow for easy update of firmware in the SD card from a running U-Boot. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* wandboard: Use env storage info for mmcdev/mmcpartOtavio Salvador2013-04-25-2/+3
| | | | | | | This makes environment and mmcdev/mmcpart in sync with SYS_MMC_ENV_DEV and SYS_MMC_ENV_PART settings. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mx6qsabresd: Return status when initializing MMCOtavio Salvador2013-04-25-6/+7
| | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mx6qsabre{sd, auto}: Add update_sd_firmware supportOtavio Salvador2013-04-25-0/+14
| | | | | | | This allow for easy update of firmware in the SD card from a running U-Boot. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* nitrogen6x: Setup CCM_CCOSR registerFabio Estevam2013-04-25-0/+12
| | | | | | | | | | | | CKO1 drives sgtl5000 codec clock on nitrogen boards and wandboard. Doing this setup in the bootloader will allow us to remove a lot of code in arch/arm/mach-imx/mach-imx6q.c from the mainline kernel. Also, according to Eric Nelson: "enabling the clock <in the bootloader> will remove squeal after an ungraceful reboot (watchdog) if hooked up to speakers." Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* imx: mx6q_4x_mt41j128.cfg: Setup CCM_CCOSR registerFabio Estevam2013-04-25-0/+11
| | | | | | | | | | | | | Setup CCM_CCOSR register to provide a CKO1 clock frequency of 16.5 MHz. CKO1 drives sgtl5000 codec clock on mx6qsabrelite and doing this setup in the bootloader will allow us to remove a lot of code in arch/arm/mach-imx/mach-imx6q.c from the mainline kernel. mx6q_4x_mt41j128.cfg is also used by mx6qsabresd, and it is safe to use it for this board as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx35 iomux: correct input select register indexPhilip Paeps2013-04-25-0/+1
| | | | | | | | Prior to this fix, calls to mxc_iomux_set_input() for registers after MUX_IN_GPIO2_IN_19 would write to the wrong registers, possibly resulting in unexpected behaviour. Signed-off-by: Philip Paeps <philip@paeps.cx>
* arm: imx: Codingstyle enhancement of include/asm/arch-mx6/crm_regs.hStefan Roese2013-04-25-86/+86
| | | | | | | | | Add spaces before and after "<<". Please note that I intentionally didn't wrap the > 80 lines for the sake of better readability. Signed-off-by: Stefan Roese <sr@denx.de>
* imx: Add titanium board support (i.MX6 based)Stefan Roese2013-04-22-2/+845
| | | | | | | | | | Titanium is a i.MX6 based board from ProjectionDesign / Barco. This patch adds support for this board with the newly introduced NAND support for i.MX6. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* mtd: mxs_nand: Add support for i.MX6Stefan Roese2013-04-22-2/+26
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* dma: Add i.MX6 support to drivers/dma/apbh_dma.cStefan Roese2013-04-22-2/+34
| | | | | | | | | This will be used by the i.MX6 NAND support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* imx: Move some i.MX common functions into the imx-common directoryStefan Roese2013-04-22-64/+102
| | | | | | | | | | | | | | | | | | This patch moves the following functions into the imx-common directory: - mxs_wait_mask_set() - mxs_wait_mask_clr() - mxs_reset_block() These are currently used by i.MX28. But the upcoming GPMI NAND port for i.MX6 will also use these functions. So lets move them to a common location to re-use them. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* imx: Move some header files from arch-mxs to imx-commonStefan Roese2013-04-22-24/+27
| | | | | | | | | | | | | | | | | | | The following headers are moved to a i.MX common location: - regs-common.h - regs-apbh.h - regs-bch.h - regs-gpmi.h - dma.h This way this header can be re-used also by other i.MX platforms. For example the i.MX6 which will need it for the upcoming NAND support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* mx6sl: Add initial support for mx6slevk boardFabio Estevam2013-04-22-0/+439
| | | | | | | | | | mx6slevk board is a development board from Freescale based on the mx6 solo-lite processor. For details about mx6slevk, please refer to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX6SLEVK&parentCode=i.MX6SL&fpsp=1 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: Add solo-lite variant supportFabio Estevam2013-04-22-3/+132
| | | | | | | | | mx6 solo-lite is another member of the mx6 series. For more information about mx6 solo-lite, please visit: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6SL&nodeId=018rH3ZrDRB24A Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* iomux-v3: Place pad control definitions into common fileFabio Estevam2013-04-22-55/+26
| | | | | | | Instead of having the same PAD control definition in each MX6 variant pin file, place it into a common location. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* Merge branch 'next'Stefano Babic2013-04-21-17/+11
|\
| * ARM: mx6: define CONFIG_ARM_ERRATA_742230Shawn Guo2013-04-17-0/+1
| | | | | | | | | | | | | | | | | | | | The ARM errata 742230 - "ARM errata: DMB operation may be faulty" is claimed for Cortex-A9 (r1p0..r2p2). Though i.MX6 uses a newer revision than r2p2, we are seeing a reboot failure on i.MX6 SMP build that can be fixed by applying the workaround for this errata. So for safety, let's define CONFIG_ARM_ERRATA_742230 to enable the workaround on i.MX6. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * arm: imx: Change iomux functions to void typeStefan Roese2013-04-16-15/+7
| | | | | | | | | | | | | | | | They never return anything also than 0, so lets change the function to void instead. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
| * mx28evk: add trimffs to nand commandEric Benard2013-04-16-0/+1
| | | | | | | | | | | | | | | | this is usefull when writing an UBI image which contains and UBIFS volume (check README.nand and UBI FAQ for more details) Signed-off-by: Eric Bénard <eric@eukrea.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| * mx35 iomux: correct offsets of IOMUX registersPhilip Paeps2013-04-16-2/+2
| | | | | | | | | | | | | | | | | | | | This makes mxc_iomux_set_input() work correctly. Previously, the incorrect offset of IOMUXSW_INPUT_CTL caused mxc_iomux_set_input() to write to the wrong register, possibly resulting in unexpected behaviour. Signed-off-by: Philip Paeps <philip@paeps.cx> Acked-by: Stefano Babic <sbabic@denx.de>
* | exynos: fdt: Add TMU node for snowSimon Glass2013-04-17-0/+14
| | | | | | | | | | | | | | | | Snow is missing a TMU node, and with TMU support this is not allowed, so it fails to boot. Add it. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | exynos: Correct use of 64-bit divisionSimon Glass2013-04-17-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | The current code is causing errors like this on my toolchains: /usr/x86_64-pc-linux-gnu/armv7a-cros-linux-gnueabi/binutils-bin/2.22/ ld.bfd.real: failed to merge target specific data of file /usr/lib/gcc/ armv7a-cros-linux-gnueabi/4.7.x-google/libgcc.a(_divdi3.o) Use do_div() to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Exynos5: Add support for USB download boot modeVivek Gautam2013-04-17-2/+43
| | | | | | | | | | | | | | | | | | | | | | | | Exynos5250 supports secondary USB device boot mode. If the iROM fails to download u-boot from the primary boot device (such as SD or eMMC), it will try to retrieve from the secondary boot device (such as USB). Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Tegra: T30: Beaver board support.Tom Warren2013-04-15-0/+149
| | | | | | | | | | | | | | | | Beaver is a Tegra30 board that is nearly 100% compatible w/Cardhu. Add a Beaver build so it can begin to be differentiated, if need be. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | Tegra: Split tegra_get_chip_type() into soc & sku funcsTom Warren2013-04-15-37/+84
| | | | | | | | | | | | | | | | | | | | | | As suggested by Stephen Warren, use tegra_get_chip() to return the pure CHIPID for a Tegra SoC (i.e. 0x20 for Tegra20, 0x30 for Tegra30, etc.) and rename tegra_get_chip_type() to reflect its true function, i.e. tegra_get_chip_sku(), which returns an ID like TEGRA_SOC_T25, TEGRA_SOC_T33, etc. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | Tegra: Fix MSELECT clock divisors for T30/T114.Tom Warren2013-04-15-8/+6
| | | | | | | | | | | | | | | | | | A comparison of registers between our internal NV U-Boot and u-boot-tegra/next showed some discrepancies in the MSELECT clock divisor programming. T20 doesn't have a MSELECT clk src reg. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | Tegra114: Initialize System Counter (TSC) with osc frequencyTom Warren2013-04-15-0/+72
| | | | | | | | | | | | | | | | | | T114 needs the SYSCTR0 counter initialized so the TSC can be read by the kernel. Do it in the bootloader since it's a write-once deal (secure/non-secure mode dependent). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | Tegra: Configure L2 cache control reg properly.Tom Warren2013-04-15-8/+52
| | | | | | | | | | | | | | | | | | | | Without this change, kernel fails at calling function cache_clean_flush during kernel early boot. Aprocryphally, intended for T114 only, so I check for a T114 SoC. Works (i.e. dalmore 3.8 kernel now starts printing to console). Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra: TEC: Enable boot script supportThierry Reding2013-04-15-7/+3
| | | | | | | | | | | | | | | | | | | | Boot script support brings TEC in line with other Tegra boards. To enable booting a Linux kernel with initial ramdisk, also include support for the new FIT image type. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | Tegra: Plutux: Enable NAND and boot script supportThierry Reding2013-04-15-7/+11
| | | | | | | | | | | | | | | | | | | | Boot script support brings Plutux in line with other Tegra boards. In order to enable booting a Linux kernel with initial ramdisk, also add support for the new FIT image type. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | Tegra: Medcom-Wide: Enable NAND and boot script supportThierry Reding2013-04-15-9/+12
| | | | | | | | | | | | | | | | | | | | Boot script support brings Medcom-Wide in line with other Tegra boards. In order to enable booting a Linux kernel with initial ramdisk, also add support for the new FIT image type. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | Tegra: All Tamonten-derived boards use onboard NANDThierry Reding2013-04-15-11/+11
| | | | | | | | | | | | | | | | | | Move the nand-controller node to the tegra20-tamonten.dtsi so that it can be shared between all derived boards. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | Tegra: Restore cp15 VBAR _start vector write for ARMv7Tom Warren2013-04-15-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | A start vector fix was added by AneeshV for OMAP4 (commit 0d479b53), and caused the old monilithic Tegra builds to hang due to an undefined instruction trap. Previously, the code needed to run on both the AVP (ARM7TDI) and A9, and the AVP doesn't have a CP15 register. I corrected this in commit 6d6c0bae w/#ifndef CONFIG_TEGRA, but now that we use SPL, and boot the AVP w/o any ARMv7 code, I can revert my change, and make Aneesh's change apply to Tegra. Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra: enable verify support for the crc32 commandTom Warren2013-04-15-0/+2
| | | | | | | | | | | | | | Some 3rd-party flash tools use the -v (verify) option of crc32 command. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | ARM: tegra: support T33 SKU of Tegra30Stephen Warren2013-04-15-0/+2
|/ | | | | | | | | | | | | | | | | | | Make U-Boot aware of the T33 SKU of Tegra30, and treat it identically to any other Tegra30. An alternative would be to simply remove the SKU checking from tegra_get_chip_type(); most use of the value most likely simply wants to know the current chip, not the specific SKU. Or, the function could be split into separate tegra_get_chip() and tegra_get_sku() for the cases where differentiation really is required. I wonder whether tegra_get_chip_type() should printf() whenever any unkown chip/SKU is found, although perhaps the function is called so early that the printf() wouldn't actually make it to the UART anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* ARMv7: start.S: stay in HYP mode if u-boot is entered in itAndre Przywara2013-04-15-3/+7
| | | | | | | | | | The KVM and Xen hypervisors for the Cortex-A15 virtualization implementation need to be entered in HYP mode. Should the primary board firmware already enter HYP mode (Calxeda firmware does that), we should not deliberately drop back to SVC mode. Since U-boot does not use the MMU, running in HYP mode is just fine. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* cosmetic: fix CONFIG_SPL_BSS_MAX_SIZE typo in READMEAlbert ARIBAUD2013-04-14-2/+2
| | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* smdk5250, snow: convert to CONFIG_SPL_MAX_FOOTPRINTAlbert ARIBAUD2013-04-14-2/+2
| | | | | | | | This target wants to check full SPL size, BSS included. Remove CONFIG_SPL_MAX_SIZE definition and instead define CONFIG_SPL_MAX_FOOTPRINT. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* da850evm, da850_am18xxevm: convert to CONFIG_SPL_MAX_FOOTPRINTAlbert ARIBAUD2013-04-14-2/+2
| | | | | | | | This target wants to check full SPL size, BSS included. Remove CONFIG_SPL_MAX_SIZE definition and instead define CONFIG_SPL_MAX_FOOTPRINT. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* cam_enc_4xx: convert to CONFIG_SPL_MAX_FOOTPRINTAlbert ARIBAUD2013-04-14-2/+2
| | | | | | | | This target wants to check full SPL size, BSS included. Remove CONFIG_SPL_MAX_SIZE definition and instead define CONFIG_SPL_MAX_FOOTPRINT. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* ARM: fix CONFIG_SPL_MAX_SIZE semanticsAlbert ARIBAUD2013-04-14-18/+30
| | | | | | | | | | | | | | | | | | | | Remove SPL-related ASSERT() in arch/arm/cpu/u-boot.lds as this file is never used for SPL builds. Rewrite the ASSERT() in arch/arm/cpu/u-boot-spl.lds to separately test image (text,data,rodata...) size, BSS size, and full footprint each against its own max, and make Tegra boards check full footprint. Also, output section mmutable is not used in SPL builds. Remove it. Finally, update README regarding the (now homogeneous) semantics of CONFIG_SPL_[BSS_]MAX_SIZE and add the new CONFIG_SPL_MAX_FOOTPRINT macro. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reported-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-14-6/+6
|\
| * fsl_esdhc: Fix DMA transfer completion waiting loopAndrew Gabbasov2013-04-14-3/+4
| | | | | | | | | | | | | | | | | | | | | | Rework the waiting for transfer completion loop condition to continue waiting until both Transfer Complete and DMA End interrupts occur. Checking of DLA bit in Present State register looks not needed in addition to interrupts status checking, so it can be removed from the condition. Also, DMA Error condition is added to the list of data errors, checked in the loop. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
| * fsl_esdhc: flush cache after IO completionEric Nelson2013-04-14-3/+2
| | | | | | | | | | | | | | | | | | The cache should invalidate the read buffer for the SD card interface after the transfer complete, not command-complete. Tested-by: Andrew Gabbasov <Andrew_Gabbasov@mentor.com> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-14-9/+12
|\ \ | |/
| * spi: mxc_spi: Set master mode for all channelsFabio Estevam2013-04-13-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6qsabre{sd, auto}: Fix environment as 'mmc rescan' takes no argumentsOtavio Salvador2013-04-13-1/+1
| | | | | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
generated by cgit v1.1 at 2024-12-22 13:45:51 +0000