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* powerpc/mpc85xx: support application without resetvec segment in the linker ↵Ying Zhang2013-06-20-0/+27
| | | | | | | | | | | | | | | | script For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM, then jump to it to begin execution. After that, the SPL loads the final uboot image into DDR, then jump to it to begin execution. The segment .resetvec in the SPL and in final U-boot is useless. So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application. If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded and the segment .bootpg is placed in the previous 4K of the segment .text. Signed-off-by: Ying Zhang <b40530@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* board/p1010rdb: Fix PCIe TLB creation on CONFIG_PCI definePrabhakar Kushwaha2013-06-20-1/+1
| | | | | | | PCIe TLB should be created with CONFIG_PCI defined Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* board/b4860qds: Relax NOR flash teadc timing parameterPrabhakar Kushwaha2013-06-20-1/+1
| | | | | | | Relax parameters to give address latching more time to setup. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: work around erratum A-006593Scott Wood2013-06-20-0/+8
| | | | | | | | | | | | Erratum A-006593 is "Atomic store may report failure but still allow the store data to be visible". The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit 21 to 1'b1. This may have a small impact on synthetic write bandwidth benchmarks but should have a negligible impact on real code." Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* fsl_ifc: add support for different IFC bank countMingkai Hu2013-06-20-32/+125
| | | | | | | | | | | | Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/t4qds: Slave module for boot from SRIO and PCIELiu Gang2013-06-20-7/+48
| | | | | | | | | | | | | | | | | | | | | When a T4 board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/t4qds: Enable master module for Boot from SRIO and PCIELiu Gang2013-06-20-0/+1
| | | | | | | | | | | | | T4 can support the feature of Boot from SRIO/PCIE, and the macro "CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature when building the u-boot image. You can get some description about this macro in README file, and for more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/b4860qds: Slave module for boot from SRIO and PCIELiu Gang2013-06-20-5/+48
| | | | | | | | | | | | | | | | | | | | | | When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/b4860qds: Enable master module for boot from SRIO and PCIELiu Gang2013-06-20-0/+1
| | | | | | | | | | | | | B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro "CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature when building the u-boot image. You can get some description about this macro in README file, and for more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/boot: Change the macro of Boot from SRIO and PCIE master moduleLiu Gang2013-06-20-13/+13
| | | | | | | | | | | | | | | | | Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable the master module of Boot from SRIO and PCIE on a platform. But this is not a silicon feature, it's just a specific booting mode based on the SRIO and PCIE interfaces. So it's inappropriate to put the macro into the file arch/powerpc/include/asm/config_mpc85xx.h. Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/doc: Update the README.srio-pcie-boot-corenetLiu Gang2013-06-20-14/+20
| | | | | | | | | | | 1. Misalignment will be found in the doc/README.srio-pcie-boot-corenet file when the tabs are set to 8 characters. And the standard for u-boot should be 8 character tabs! So this issue should be amended. 2. Add a NOTE for the ENV parameters of the Slave. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPLPrabhakar Kushwaha2013-06-20-7/+22
| | | | | | | | | e500v2 processor does not support 8K page size TLB entries. So create new TLB entry only during NAND SPL boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFTAndy Fleming2013-06-20-3/+3
| | | | | | | All the other constants use lowercase 'x' in "MPC85xx", so we duplicate that here. Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc: Use lower case for the core namesFabio Estevam2013-06-20-5/+5
| | | | | | | | | | | | | | | | | | Freescale documentation presents the PowerPC core names in lower case, such as "e300", "e500", "e600", etc. Change the upper case occurrences into lower case so that the core names reported in U-boot can match the ones from the documentation. While at it also fix a checkpatch error: ERROR: space prohibited before that close parenthesis ')' #53: FILE: arch/powerpc/cpu/mpc86xx/cpu.c:81: + printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); Reported-by: Heinz Wrobel <heinz.wrobel@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/BSC9132: Add IFC bank countYork Sun2013-06-20-0/+1
| | | | | | | BSC9132 has 3 IFC banks. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* board/bsc9131rdb: Update default boot environment settingsPriyanka Jain2013-06-20-1/+13
| | | | | | | | | | | | | | | | BSC9131RDB has 1GB DDR. Out of this, only 880MB is passed on to Linux via bootm_size. Remaining -16MB is reserved for PowerPC-DSP shared control area -128MB is reserved for DSP private area. Also 256MB, out of this 880MB is required for data communication between PowerPC and DSP core. For this bootargs are modified to pass parameter to create 1 hugetlb page of 256MB via default_hugepagesz, hugepagesz and hugepages Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* board/bsc9131rdb: Add DSP side tlb and lawsPriyanka Jain2013-06-20-0/+29
| | | | | | | | | | | | | | | BSC9131RDB is a Freescale Reference Design Board for BSC9131 SoC which is a integrated device that contains one powerpc e500v2 core and one DSP starcore. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 memory Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* board/bsc9131rdb: Add targets for Sysclk 100MHzPriyanka Jain2013-06-20-2/+12
| | | | | | | | | | | | | | BSC9131RDB supports Sysclk -66MHz if jumper J16 is close (default state) -100MHz if jumper J16 is open Add targets -BSC9131RDB_NAND_SYSCLK100 : for NAND boot at Sysclk 100MHz -BSC9131RDB_SPIFLASH_SYSCLK100: for SPI boot at Sysclk 100MHz Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* board/bsc9132qds:Add NAND boot support using new SPL formatPrabhakar Kushwaha2013-06-20-17/+225
| | | | | | | | | | - Add NAND boot target - defines constants - Add spl_minimal.c to initialise DDR - update TLB, LAW entries as per NAND boot Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* board/bsc9131rdb:Add NAND boot support using new SPL formatPrabhakar Kushwaha2013-06-20-15/+177
| | | | | | | | | | - Add NAND boot target - defines constants - Add spl_minimal.c to initialise DDR - update TLB entries as per NAND boot Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* board/p1010rdb:Add NAND boot support using new SPL formatPrabhakar Kushwaha2013-06-20-458/+69
| | | | | | | | | | - defines constants - Add spl_minimal.c to initialise DDR - update TLB entries as per NAND boot - remove nand_spl support for P1010RDB Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: new SPL support for IFC NANDPrabhakar Kushwaha2013-06-20-1/+270
| | | | | | | | | | | | | | Linker script is not able find start.o binary. So add its absolute path in u-boot-spl.lds. This change is similar to u-boot-nand.lds common/Makefile: Avoid compiling unnecssary files fsl_ifc_spl.c : It is is responsible for reading u-boot binary from NAND flash and copying into DDR. It also transfer control from NAND SPL to u-boot image present in DDR. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx:No NOR boot, do not compile IFC errata A003399Prabhakar Kushwaha2013-06-20-6/+17
| | | | | | | | IFC errata A003399 is valid for IFC NOR boot i.e.if no on-board NOR flash or no NOR boot, do not compile its workaround. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: explicit cast the SDRAM size to type phys_size_tMingkai Hu2013-06-20-1/+1
| | | | | | | | | | To avoid sign extension problem, use explicit casting to cast the SDRAM size to type phys_size_t, or else, if the SDRAM size is 2G(0x80000000), it will be extended to 0xffffffff80000000 when phys_size_t is type 'unsigned long long'. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Change clock-frequency compatible to 2.0Andy Fleming2013-06-20-1/+1
| | | | | | | | | Accidentally applied an earlier version of the patch, which set the compatible to "fsl,qoriq-clockgen-2", lacking the final ".0". Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
* NET: Fix system hanging if NET device is not installedJim Lin2013-06-19-1/+2
| | | | | | | | | | | | | If we try to boot from NET device, NetInitLoop in net.c will be invoked. If NET device is not installed, eth_get_dev() function will return eth_current value, which is NULL. When NetInitLoop is called, "eth_get_dev->enetaddr" will access restricted memory area and therefore cause hanging. This issue is found on Tegra30 Cardhu platform after adding CONFIG_CMD_NET and CONFIG_CMD_DHCP in config header file. Signed-off-by: Jim Lin <jilin@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* image: Use ENOENT instead of ENOMEDIUM for better compatibilitySimon Glass2013-06-17-1/+1
| | | | | | | | | This error may not be defined on some platforms such as MacOS so host compilation will fail. Use one of the more common errors instead. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Lubomir Popov <lpopov@mm-sol.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mmcTom Rini2013-06-14-27/+156
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| * ARM: tegra: make use of negative ENV_OFFSET on NVIDIA boardsStephen Warren2013-06-13-8/+8
| | | | | | | | | | | | | | | | | | | | | | Use a negative value of CONFIG_ENV_OFFSET for all NVIDIA reference boards that store the U-Boot environment in the 2nd eMMC boot partition. This makes U-Boot agnostic to the size of the eMMC boot partition, which can vary depending on which eMMC device was actually stuffed into the board. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * env_mmc: allow negative CONFIG_ENV_OFFSETStephen Warren2013-06-13-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A negative value of CONFIG_ENV_OFFSET is treated as a backwards offset from the end of the eMMC device/partition, rather than a forwards offset from the start. This is useful when a single board may be stuffed with different eMMC devices, each of which has a different capacity, and you always want the environment to be stored at the very end of the device (or eMMC boot partition for example). One example of this case is NVIDIA's Ventana reference board. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * mmc: report capacity for the selected partitionStephen Warren2013-06-13-7/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | Enhance the MMC core to calculate the size of each MMC partition, and update mmc->capacity whenever a partition is selected. This causes: mmc dev 0 1 ; mmcinfo ... to report the size of the currently selected partition, rather than always reporting the size of the user partition. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * README: document CONFIG_ENV_IS_IN_MMCStephen Warren2013-06-13-0/+40
| | | | | | | | | | | | | | | | | | | | Describe the meaning of CONFIG_ENV_IS_IN_MMC, and all related defines that must or can be set when using that option. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * fsl_esdhc: Do not clear interrupt status bits until data processedAndrew Gabbasov2013-06-13-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After waiting for the command completion event, the interrupt status bits, that occured to be set by that time, are cleared by writing them back. It is supposed, that it should be command related bits (command complete and may be command errors). However, in some cases the DMA already completes by that time before the full transaction completes. The corresponding DINT bit gets set and then cleared before even entering the loop, waiting for data part completion. That waiting loop never gets this bit set, causing the operation to hang. This is reported to happen, for example, for write operation of 1 sector to upper area (block #7400000) of SanDisk Ultra II 8GB card. The solution could be to explicitly clear only command related interrupt status bits. However, since subsequent processing does not rely on any command bits state, it could be easier just to remove clearing of any bits at that point, leaving them all until all data processing completes. After that the whole register will be cleared at once. Also, on occasion, interrupts masking moved to before writing the command, just for the case there should be no chance of interrupt between the first command and interrupts masking. Reported-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * mmc: fsl_esdhc: Fix hang after 'save' commandFabio Estevam2013-06-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Since commit 48e0b2bd (powerpc/esdhc: Correct judgement for DATA PIO mode) we see mx6 systems to hang after doing a 'save' command. Revert this commit since the original 'ifdef' logic from 7b43db92 (drivers/mmc/fsl_esdhc.c: fix compiler warnings) was the correct one. Reported-by: Tapani Utriainen <tapani@technexion.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * mmc write bug fixRuud Commandeur2013-06-13-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a bug related to mmc writes. When doing fatwrites on an SD-Card, MMC bus problems can occur. Depending on the size of the file, "MMC0: Bus busy timeout!" is reported, resulting in an SD-Card that is no longer responding. It appears to be, that set_cluster can be called with a size being zero. That can be with a file that has a size being an exact multiple (including 0) of the clustersize, but also for files that are smaller than the size of one cluster. The same problem occurs if the "mmc write" command is given with a block count being 0. By adding a check for the block count being zero in mmc_write_blocks (drivers/mmc.c), this problem is solved. Signed-off-by: Ruud Commandeur <rcommandeur@clb.nl> Cc: Tom Rini <trini@ti.com> Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Mats Karrman <Mats.Karrman@tritech.se> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * mmc: sdhci: Enable 8-bit bus width only for 3.0 spec onwardsJagannadha Sutradharudu Teki2013-06-13-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CAP register don't have any information for 8-bit buswidth support on 2.0 sdhci spec, only from 3.0 onwards bit[18] got this information. Due to this misassignment in sdhci, mmc is setting 8-bit buswidth using mmc_set_bus_width even if controller doesn't support. Below change has code information. "mmc: Properly determine maximum supported bus width" (sha1: 7798f6dbd5e1a3030ed81a81da5dfb57c3307cac) Bug log: <mmc plus and emmc cards) ------- zynq-uboot> mmcinfo Error detected in status(0x208100)! Device: zynq_sdhci Manufacturer ID: fe ..... So enable 8-bit support only for 3.0 spec using CAP and for below 3.0 assign mmc->host_caps = MMC_MODE_8BIT on respective platform driver if host have a support. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * mmc: fix env in mmc with redundant compile errorBo Shen2013-06-13-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit d196bd8 (env_mmc: add support for redundant environment) introduce the following compile error when enable redundant environment support with MMC ---8<--- env_mmc.c:149: error: 'env_t' has no member named 'flags' env_mmc.c:248: error: 'env_t' has no member named 'flags' env_mmc.c:248: error: 'env_t' has no member named 'flags' env_mmc.c:250: error: 'env_t' has no member named 'flags' env_mmc.c:250: error: 'env_t' has no member named 'flags' env_mmc.c:252: error: 'env_t' has no member named 'flags' env_mmc.c:252: error: 'env_t' has no member named 'flags' env_mmc.c:254: error: 'env_t' has no member named 'flags' env_mmc.c:254: error: 'env_t' has no member named 'flags' env_mmc.c:267: error: 'env_t' has no member named 'flags' make[1]: *** [env_mmc.o] Error 1 --->8--- Add this patch to fix it Signed-off-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Michael Heimpold <mhei@heimpold.de> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Prepare v2013.07-rc1Tom Rini2013-06-14-2/+2
| | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-06-13-54/+122
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| * | sf: winbond: Correct the nr_blocks used for W25Q32DWJagannadha Sutradharudu Teki2013-06-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch corrected the nr_blocks used for W25Q32DW SPI flash. nr_blcoks are incorrectly assigned on below patch "sf: winbond: add W25Q32DW" (sha1: 772ba15474f73adc942e817cc072b6e9750836cc) Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: winbond: Add support for W25Q80BWJagannadha Sutradharudu Teki2013-06-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Winbond W25Q80BW SPI flash. This patch corrected the flash name, nr_blocks and also commit message header from below patch. "sf: winbond: add W25Q32" (sha1: c969abc47033d6f810d3c9dbdb994ea9d691d038) Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: spansion: Update the name for S25FL256S flashJagannadha Sutradharudu Teki2013-06-13-1/+1
| | | | | | | | | | | | | | | | | | | | | As the per the ID tabl the flash is under Uniform 64-kB sector architecture, hence updated with proper name. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | spi: tegra20_sflash: Remove redundant code to set bus and cs of struct spi_slaveAxel Lin2013-06-13-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | It's done in spi_alloc_slave(), thus remove the redundant code. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: tegra114_spi: Convert to use spi_alloc_slave()Axel Lin2013-06-13-3/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: armada100_spi: Remove unnecessary NULL test for dout and dinAxel Lin2013-06-13-9/+2
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Ajay Bhargav <ajay.bhargav@einfochips.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | cmd_sf: Add print mesgs on sf read/write commandsJagannadha Sutradharudu Teki2013-06-03-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a print messages while using 'sf read' and 'sf write' commands to make sure that how many bytes read/written from/into flash device. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Tom Rini <trini@ti.com>
| * | cmd_sf: Add print mesg for 'sf erase' commandJagannadha Sutradharudu Teki2013-06-03-10/+5
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds a print messages while using 'sf erase' command to make sure that how many bytes erased in flash device. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Tom Rini <trini@ti.com>
| * | sf: Fix sf read for memory-mapped SPI flashesJagannadha Sutradharudu Teki2013-06-03-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Missing return after memcpy is done for memory-mapped SPI flashes, hence added retun 0 after memcpy done. The return is missing in below patch "sf: Enable FDT-based configuration and memory mapping" (sha1: bb8215f437a7c948eec82a6abe754c226978bd6d) Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | spi: exynos: Support SPI_PREAMBLE modeRajeshwari Shinde2013-06-03-10/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support interfaces with a preamble before each received message. We handle this when the client has requested a SPI_XFER_END, meaning that we must close of the transaction. In this case we read until we see the preamble (or a timeout occurs), skipping all data before and including the preamble. The client will receive only data bytes after the preamble. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | spi: Add support for preamble bytesRajeshwari Shinde2013-06-03-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A SPI slave may take time to react to a request. For SPI flash devices this time is defined as one bit time, or a whole byte for 'fast read' mode. If the SPI slave is another CPU, then the time it takes to react may vary. It is convenient to allow the slave device to tag the start of the actual reply so that the host can determine when this 'preamble' finishes and the actual message starts. Add a preamble flag to the available SPI flags. If supported by the driver then it will ignore any received bytes before the preamble on each transaction. This ensures that reliable communication with the slave is possible. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
generated by cgit v1.1 at 2024-12-23 05:55:55 +0000