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* MC13892: Add SWx buck switchers definitionsMarek Vasut2011-02-02-0/+39
| | | | | | | Define voltages configurable on SWx buck switchers. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mxc_nand: add support for i.MX35 processorStefano Babic2011-02-02-3/+3
| | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
* BLOCK: Add freescale IMX51 PATA driverMarek Vasut2011-02-02-0/+150
| | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
* MX5:MX53: add initial support for MX53EVK boardLiu Hui-R643432011-02-02-0/+784
| | | | | | | Add initial support for MX53EVK board support. FEC, SD/MMC, UART, I2C, have been supported. Signed-off-by: Jason Liu <r64343@freescale.com>
* fsl_pmic: add I2C interface supportLiu Hui-R643432011-02-02-5/+40
| | | | | | This patch add I2C interface for fsl_pmic driver support Signed-off-by: Jason Liu <r64343@freescale.com>
* mxc_i2c: add support for MX53 processorLiu Hui-R643432011-02-02-3/+18
| | | | | | This patch add I2C support for Freescale MX53 processor Signed-off-by: Jason Liu <r64343@freescale.com>
* mxc_gpio: add support for MX53 processorLiu Hui-R643432011-02-02-2/+7
| | | | | | This patch add mxc_gpio support for Freescale MX53 processor Signed-off-by: Jason Liu <r64343@freescale.com>
* serial_mxc: add support for MX53 processorLiu Hui-R643432011-02-02-0/+6
| | | | | | This patch add UART support for Freescale MX53 processor Signed-off-by: Jason Liu <r64343@freescale.com>
* fec_mxc: add support for MX53 processorLiu Hui-R643432011-02-02-3/+3
| | | | | | This patch add FEC support for Freescale MX53 processor Signed-off-by: Jason Liu <r64343@freescale.com>
* MX5: Add initial support for MX53 processorLiu Hui-R643432011-02-02-208/+599
| | | | | | | | | | Add initial support for Freescale MX53 processor, - Add the iomux support and the pin definition, - Add the regs definition, clean up some unused def from mx51, - Add the low level init support, make use the freq input of setup_pll macro Signed-off-by: Jason Liu <r64343@freescale.com>
* MX51EVK: UART does not print out the early informationLiu Hui-R643432011-02-02-3/+10
| | | | | | | | | | | | | | The early bootup information is not print out due to the UART pin iomux not set up correctly before board_init Add the board_early_init_f function and enable the CONFIG_BOARD_EARLY_INIT_F. Move the UART pin setting from board_init to board_early_init_f function. This patch also move the FEC pin iomux setup to the board_early_init_f. Signed-off-by: Jason Liu <r64343@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-01-31-1/+848
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| * mpq101: initial support for Mercury Computer Systems MPQ101 boardAlex Dubov2011-01-26-0/+847
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548 processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash memory, real time clock and additional serial EEPROM on i2c bus (enabled). USB controller is available, but not presently enabled. Additional board information is available at: http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx Environment is configured to precede the actual u-boot image so that it's located at the beginning of flash erase block (made necessary by the recent changes to the embedded environment handling). This is achieved by means of custom ld script. Signed-off-by: Alex Dubov <oakad@yahoo.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * p1022ds: fix pixis_reset altbankYork Sun2011-01-26-1/+1
| | | | | | | | | | | | | | | | | | Fix the bits for ngpixis to reset to alternative bank. Originally the mask was 0xE0, which left it possible to reset to bank 3 if DIP switch is set to boot from bank 1. Changing to 0xF0 gurantees to reset to bank 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2011-01-31-3/+1
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| * | Fix at91 includes in soft_i2c driverRyan Mallon2011-01-27-3/+1
| |/ | | | | | | | | | | | | | | Make at91 header includes in soft_i2c depend only on CONFIG_AT91FAMILY rather than individual SoCs. Signed-off-by: Ryan Mallon <ryan@bluewatersys.com> Acked-by: Reinhard Meyer<u-boot@emk-elektronik.de>
* | lcd: align fb writing address for horizontal display offsetLiu Ying2011-01-27-1/+1
|/ | | | | | | | | CONFIG_SPLASH_SCREEN_ALIGN makes uboot support display offset for splashimage. The framebuffer writing address should be calculated according to different kinds of framebuffer pixel format, i.e., bits per pixel value. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGSNobuhiro Iwamatsu2011-01-25-11/+17
| | | | | | | | | | Linker needs to use the proper endian/bfd flags even when doing partial linking. LDFLAGS_u-boot sets linker option which is called it when U-boot is built (u-boot final). LDFLAGS sets necessary option by partial linking (use in cmd_link_o_target). CC: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* ftpmu010: support faraday ftpmu010 driverMacpaul Lin2011-01-25-0/+66
| | | | | | | | | Faraday's ftpmu010 is a power managemnet unit which support cpu sleep and frequency scaling. It has been integrated into many SoC. This patch also move ftpmu010 to a proper place for later enhancement. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
* powerpc: Fix FPU post related link warningsKumar Gala2011-01-25-16/+16
| | | | | | | | | | | | | | | | | | | | | | If we built POST on PPC's that didn't enable CONFIG_SYS_POST_FPU we'd get the following warning with newer toolchains: powerpc-linux-gnu-ld: Warning: lib_powerpc/fpu/libpostpowerpcfpu.o uses hard float, libpost.o uses soft float We actually worked around this sometime ago with the following commit: commit ce82ff05388b5ddafdf6082ef0776cce72c40b1c Author: Yuri Tikhonov <yur@emcraft.com> Date: Sat Dec 20 14:54:21 2008 +0300 FPU POST: fix warnings when building with 2.18 binutils However, this only took into effect if CONFIG_SYS_POST_FPU was enabled. We can simply move the GNU_FPOST_ATTR out of the CONFIG_SYS_POST_FPU ifdef block to address the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* UEC: Fix compiler warnings introduced by linux/mii.h changeKumar Gala2011-01-25-19/+9
| | | | | | | | | | | | | | | | | | | | | | | Patch 8ef583a0 [miiphy: convert to linux/mii.h] introduced the following compiler warnings in the uec ethernet driver: In file included from /local/home/galak/git/u-boot-85xx/include/miiphy.h:37:0, from uec.c:32: /local/home/galak/git/u-boot-85xx/include/linux/mii.h:133:0: warning: "LPA_1000FULL" redefined uec_phy.h:34:0: note: this is the location of the previous definition /local/home/galak/git/u-boot-85xx/include/linux/mii.h:134:0: warning: "LPA_1000HALF" redefined uec_phy.h:35:0: note: this is the location of the previous definition In file included from /local/home/galak/git/u-boot-85xx/include/miiphy.h:37:0, from uec_phy.c:27: /local/home/galak/git/u-boot-85xx/include/linux/mii.h:133:0: warning: "LPA_1000FULL" redefined uec_phy.h:34:0: note: this is the location of the previous definition /local/home/galak/git/u-boot-85xx/include/linux/mii.h:134:0: warning: "LPA_1000HALF" redefined uec_phy.h:35:0: note: this is the location of the previous definition Fix them be removing the duplication in the uec code and utlizing the linux/mii.h version instead. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-01-25-438/+1940
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| * powerpc/8xxx: Fix compile warning when build for a DDR1 or DDR2 boardKumar Gala2011-01-24-1/+1
| | | | | | | | | | | | | | | | | | ctrl_regs.c: In function 'set_ddr_sdram_mode_2': ctrl_regs.c:690:6: warning: unused variable 'i' 'i' is only used by DDR3 code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Protect all LBC code with CONFIG_FSL_LBCDipen Dudhat2011-01-19-2/+13
| | | | | | | | | | | | | | | | | | Future SoC (like the P1010) replace the LBC controller with the new IFC (Integrated Flash Controller) so ensure we properly protect code that is related to the LBC. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: Fix compile err when PCI disabled on P1_P2_RDBPrabhakar Kushwaha2011-01-19-7/+14
| | | | | | | | | | | | | | | | | | u-boot cannot be compiled after disabling CONFIG_PCI. Place PCI related codes under #ifdef CONFIG_PCI Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/p4080: Fix warning in serdes code from early use of hwconfigYork Sun2011-01-19-3/+14
| | | | | | | | | | | | | | Hwconfig is called before relocating. Use the new hwconfig APIs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * corenet_ds: Extend board specific parametersYork Sun2011-01-19-78/+84
| | | | | | | | | | | | | | | | | | Extend board specific parameters to include cpo, write leveling override Extend write leveling sample to 0xf Adding rcw overrid for quad-rank RDIMMs Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc85xx: Implement workaround for erratum DDR-A003York Sun2011-01-19-1/+103
| | | | | | | | | | | | | | | | Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM. Also adding polling after enabling DDR controller to ensure completion. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc85xx: Enable unique mode registers and dynamic ODT for DDR3York Sun2011-01-19-55/+596
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version (major, minor, errata) to determine if unique mode registers are available. If true, always use unique mode registers. Dynamic ODT is enabled if needed. The table is documented in doc/README.fsl-ddr. This function may also need to be extend for future other platforms if such a feature exists. Enable address parity and RCW by default for RDIMMs. Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for quad-rank RDIMMs. Use a formula to calculate rodt_on for timing_cfg_5. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc85xx: Adding more registers and optionsYork Sun2011-01-19-26/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * corenet_ds: Enable ECC for corenet_dsYork Sun2011-01-19-1/+1
| | | | | | | | | | | | | | | | ECC can be turned on/off by hwconfig without recompiling. So enable it by default. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc8xxx: Enable ECC on/off control in hwconfigYork Sun2011-01-19-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file, ECC can be turned on/off by this switch. If this switch is omitted, it is ON by default. Updated hwconfig calls to use local buffer. Syntax is hwconfig=fsl_ddr:ecc=on Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc8xxx: Display RDIMM if detectedYork Sun2011-01-19-12/+8
| | | | | | | | | | | | | | Print a message when a RDIMM is detected. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/8xxx: Introduce 85xx, 86xx, QorIQ config headersKumar Gala2011-01-19-70/+236
| | | | | | | | | | | | | | | | | | | | | | Add new headers that capture common defines for a given SoC/processor rather than duplicating that information in board config.h and random other places. Eventually this should be handled by Kconfig & defconfigs Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
| * powerpc/8xxx: Add hwconfig APIs to address early parsing used by DDR initKumar Gala2011-01-19-78/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several users of the hwconfig APIs (8xxx DDR) before we have the environment properly setup. This causes issues because of the numerous ways the environment might be accessed because of the non-volatile memory it might be stored in. Additionally the access might be so early that memory isn't even properly setup for us. Towards resolving these issues we provide versions of all the hwconfig APIs that can be passed in a buffer to parse and leave it to the caller to determine how to allocate and populate the buffer. We use the _f naming convention for these new APIs even though they are perfectly useable after relocation and the environment being ready. We also now warn if the non-f APIs are called before the environment is ready to allow users to address the issues. Finally, we convert the 8xxx DDR code to utilize the new APIs to hopefully address the issue once and for all. We have the 8xxx DDR code create a buffer on the stack and populate it via getenv_f(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
| * powerpc/p2040: Add various p2040 specific informationKumar Gala2011-01-19-2/+74
| | | | | | | | | | | | | | | | | | | | Add P2040 SoC specific information: * SERDES Table * Added p2040 to cpu_type_list and SVR list * Added number of LAWs for p2040 * Set CONFIG_MAX_CPUS to 4 for p2040 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/p5020: Add various p5020 specific informationKumar Gala2011-01-19-0/+258
| | | | | | | | | | | | | | | | | | Add P5020 SoC specific information: * SERDES Table * LIODN setup * Portal configuration Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/p3041: Add various p3041 specific informationKumar Gala2011-01-19-0/+258
| | | | | | | | | | | | | | | | | | Add P3041 SoC specific information: * SERDES Table * LIODN setup * Portal configuration Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add Support for Freescale P1014 ProcessorPoonam Aggrwal2011-01-19-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | The P1014 is similar to the P1010 processor with the following differences: - 16bit DDR with ECC. (P1010 has 32bit DDR w/o ECC) - no eCAN interface. (P1010 has 2 eCAN interfaces) - Two SGMII interface (P1010 has 3 SGMII) - No secure boot Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add Support for Freescale P1010 ProcessorPoonam Aggrwal2011-01-19-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Key Features include of the P1010: * e500v2 core frequency operation of 500 to 800 MHz * Power consumption less than 5.0 W at 800 MHz core speed * Dual SATA 3 Gbps controllers with integrated PHY * Dual PCI Express controllers * Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSECs) * TCP/IP acceleration and classification capabilities * IEEE 1588 support * Lossless flow control * RGMII, SGMII * DDR3 with support for a 32-bit data interface (40 bits including ECC), up to 800 MHz data rate 32/16-bit DDR3 memory controller * Dedicated security engine featuring trusted boot * TDM interface * Dual controller area networks (FlexCAN) controller * SD/MMC card controller supporting booting from Flash cards * USB 2.0 host and device controller with an on-chip, high-speed PHY * Integrated Flash controller (IFC) * Power Management Controller (PMC) * Four-channel, general-purpose DMA controller * I2C controller * Serial peripheral interface (SPI) controller with master and slave support * System timers including a periodic interrupt timer, real-time clock, software watchdog timer, and four general-purpose timers * Dual DUARTs Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDRPrabhakar2011-01-19-1/+1
| | | | | | | | | | | | | | | | | | CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET. It should be as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * powerpc/85xx: Move RESET_VECTOR_ADDRESS into config.hKumar Gala2011-01-19-94/+37
| | | | | | | | | | | | | | | | | | | | | | Rather than defining it config.mk we can set it in config.h and remove config.mk from several boards that don't need it. We mimic what 4xx does and introduce CONFIG_RESET_VECTOR_ADDRESS for config.h to set. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
| * 8xxx/ddr: add support to only compute the ddr sdram sizeHaiying Wang2011-01-19-9/+40
| | | | | | | | | | | | | | | | | | This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in case that the DDR SDRAM is initialized in the 2nd stage uboot and should not be intialized again in the final stage uboot. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Cleanup .boards.depend when using an objtreeLoïc Minier2011-01-21-2/+2
| | | | | | | | | | | | | | | | | | .boards.depend was created in the source tree even when calling make with O=objtree, and distclean O=objtree wouldn't clean it. Create .boards.depend in objtree instead as to clean it up properly. Reported-by: Loïc Minier <loic.minier@linaro.org> Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Don't add symlink in srctree when using an objtreeLoïc Minier2011-01-21-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building with srctree != objtree, the build creates arch/soc/cpu specific symlinks in the source tree. This means that the same source tree can't be used for multiple builds at the same time. Also, these symlinks in the source tree are only cleaned up if one passes the same O= to distclean. When srctree != objtree, mkconfig creates an $objtree/include2 directory in the objtree to host the asm -> arch/$arch/include/asm symlink so that "#include <asm>" can be used. But it also creates another identical symlink in $objtree/include. Then, mkconfig creates two symlinks: $objtree/include/asm/arch -> arch/$arch/include/asm/arch-$cpu (or $soc) $objtree/include/asm/proc -> arch/$arch/include/asm/proc-armv (on arm) but because $objtree/include/asm points at $srctree already, the two symlinks are created under $srctree. To fix this, create a real $objtree/include/asm directory, instead of a symlink. Update cleanup code accordingly. Signed-off-by: Loïc Minier <loic.minier@linaro.org>
* | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2011-01-19-43/+36
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| * | USB-CDC: Move MAC addresses setting into usb_eth_initVitaly Kuzmichev2011-01-19-36/+26
| | | | | | | | | | | | | | | | | | | | | This allows to change device and host MAC addresses without performing reset. Signed-off-by: Vitaly Kuzmichev <vkuzmichev@mvista.com>
| * | USB-CDC: Do not rename netdev after its registrationVitaly Kuzmichev2011-01-19-3/+2
| | | | | | | | | | | | | | | | | | | | | Calling eth_bind at usb_eth_init time causes renaming of the network device from 'usb_ether' to 'usb0'. Fixing this to keep the first name. Signed-off-by: Vitaly Kuzmichev <vkuzmichev@mvista.com>
| * | usb_ether: register usb ethernet gadget at each eth initLei Wen2011-01-19-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the ether may not be the only one usb gadget would be used in the uboot, it is neccessary to do the register each time the eth begin to work to make usb gadget driver less confussed when we want to use two different usb gadget at the same time. Usb gadget driver could simple ignore the register operation, if it find the driver has been registered already. Signed-off-by: Lei Wen <leiwen@marvell.com>
* | | Fix defines needed to enable command sha1sumAlexander Holler2011-01-19-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Documented is CONFIG_CMD_SHA1, through confusion in the source CONFIG_CMD_SHA1 and CONFIG_CMD_SHA1SUM has to be used to enable sha1sum. Fix both, the documentation and the source, so that only CONFIG_CMD_SHA1SUM is needed to enable the command sha1sum. Signed-off-by: Alexander Holler <holler@ahsoftware.de>
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