summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* spi: tegra20_sflash: Remove redundant code to set bus and cs of struct spi_slaveAxel Lin2013-06-13-2/+0
| | | | | | | | It's done in spi_alloc_slave(), thus remove the redundant code. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: tegra114_spi: Convert to use spi_alloc_slave()Axel Lin2013-06-13-3/+1
| | | | | | Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: armada100_spi: Remove unnecessary NULL test for dout and dinAxel Lin2013-06-13-9/+2
| | | | | | | Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Ajay Bhargav <ajay.bhargav@einfochips.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* cmd_sf: Add print mesgs on sf read/write commandsJagannadha Sutradharudu Teki2013-06-03-14/+15
| | | | | | | | | This patch adds a print messages while using 'sf read' and 'sf write' commands to make sure that how many bytes read/written from/into flash device. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Tom Rini <trini@ti.com>
* cmd_sf: Add print mesg for 'sf erase' commandJagannadha Sutradharudu Teki2013-06-03-10/+5
| | | | | | | | This patch adds a print messages while using 'sf erase' command to make sure that how many bytes erased in flash device. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Tom Rini <trini@ti.com>
* sf: Fix sf read for memory-mapped SPI flashesJagannadha Sutradharudu Teki2013-06-03-1/+3
| | | | | | | | | | | | Missing return after memcpy is done for memory-mapped SPI flashes, hence added retun 0 after memcpy done. The return is missing in below patch "sf: Enable FDT-based configuration and memory mapping" (sha1: bb8215f437a7c948eec82a6abe754c226978bd6d) Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
* spi: exynos: Support SPI_PREAMBLE modeRajeshwari Shinde2013-06-03-10/+59
| | | | | | | | | | | | | | Support interfaces with a preamble before each received message. We handle this when the client has requested a SPI_XFER_END, meaning that we must close of the transaction. In this case we read until we see the preamble (or a timeout occurs), skipping all data before and including the preamble. The client will receive only data bytes after the preamble. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: Add support for preamble bytesRajeshwari Shinde2013-06-03-0/+5
| | | | | | | | | | | | | | | | | | | | A SPI slave may take time to react to a request. For SPI flash devices this time is defined as one bit time, or a whole byte for 'fast read' mode. If the SPI slave is another CPU, then the time it takes to react may vary. It is convenient to allow the slave device to tag the start of the actual reply so that the host can determine when this 'preamble' finishes and the actual message starts. Add a preamble flag to the available SPI flags. If supported by the driver then it will ignore any received bytes before the preamble on each transaction. This ensures that reliable communication with the slave is possible. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* sf: winbond: Add support for W25PXX SPI flashKuo-Jung Su2013-05-28-1/+16
| | | | | | | | | | Add support for Winbond's W25PXX SPI flash. These devices is used on Faraday A369 evaluation board. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> CC: Tom Rini <trini@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* sf: winbond: Add support for W25Q256Jagannadha Sutradharudu Teki2013-05-28-0/+5
| | | | | | | Add support for Winbond W25Q256 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* sf: spansion: Add Spansion S25FL064P IDsMarek Vasut2013-05-28-0/+7
| | | | | | | | | | | | This is a S25FL064A successor. It supports up to 104MHz bus speed. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Scott Wood <scottwood@freescale.com> Cc: Wolfgang Denk <wd@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* powerpc/esdhc: Correct judgement for DATA PIO modeHaijun.Zhang2013-05-15-1/+1
| | | | | | | | | | | | The logic for the whether to configure for polling or DMA was mistakenly reversed in this patch: Commit 7b43db92110ec2f15c5f7187a165f2928464966b drivers/mmc/fsl_esdhc.c: fix compiler warnings Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> CC: Sun Yusong-R58495 <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: update Faraday FTSDC010 for rw performanceKuo-Jung Su2013-05-15-697/+400
| | | | | | | | | | | | | | | | Faraday FTSDC010 is a MMC/SD host controller. Although there is already a driver in current u-boot release, which is modified from eSHDC and contributed by Andes Tech. Its performance is too terrible on Faraday A36x SoC platforms, so I turn to implement this new version of driver which is 10+ times faster than the old one. It's carefully designed to be compatible with Andes chips, so it should be safe to replace it. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2013-05-15-227/+1154
|\
| * T4240/eth: fix SGMII card PHY addressShaohui Xie2013-05-14-4/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | QSGMII card assumed to be used by default, but if SGMII card is used, it will use different PHY address, but we don't know which card is used until we access PHY on the card. So we check the card type slot by slot, if we can read a PHY ID by reading a SGMII PHY address on a slot, then the slot must have a SGMII card pluged, we mark all ports on that slot, and fix dts to use the SGMII card PHY address when doing dts fixup for the marked ports. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/t4qds: Fix disabling remote I2C connectionEd Swarthout2013-05-14-3/+3
| | | | | | | | | | | | | | | | | | Only clear IRE bit in qixis brdcfg5 register and keep other bits unchanged. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/b4860qds: Assign DDR address in board fileYork Sun2013-05-14-0/+72
| | | | | | | | | | | | | | | | B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address. This is the requirement for DSP cores to run in 32-bit address space. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Allow board file to override DDR address assignmentYork Sun2013-05-14-1/+6
| | | | | | | | | | | | | | | | | | This gives boards flexibility to assign other than default addresses to each DDR controller. For example, DDR controler 2 can have 0 as the base and DDR controller 1 has higher memory. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Update workaround for DDR erratum A-004934York Sun2013-05-14-1/+1
| | | | | | | | | | | | | | | | The workaround has been updated to use a slightly different magic number. Change from 0x00003000 to 0x30003000. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * T4/usb: move usb 2.0 utmi dual phy init code to cpu_init.cRoy Zang2013-05-14-21/+22
| | | | | | | | | | | | | | | | This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY initialization can be reused in kernel without “usb start” command. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * T4240/net: use QSGMII card PHY address by defaultShaohui Xie2013-05-14-57/+67
| | | | | | | | | | | | | | | | Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card PHY address is variable depends on different slot. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * net/phy: add VSC8574 supportShaohui Xie2013-05-14-0/+69
| | | | | | | | | | | | | | | | | | | | The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes interfaces for quad-port dual media capability. This driver supports SGMII and QSGMII MAC mode. For now SGMII mode is tested. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: fix build error introduced by serdes_get_prtclShengzhou Liu2013-05-14-1/+0
| | | | | | | | | | | | | | Removed unused declare serdes_get_prtcl() which was no longer needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * net/fm: fixup ethernet for mEMACShengzhou Liu2013-05-14-0/+27
| | | | | | | | | | | | | | | | | | - set proper compatible property name for mEMAC. - fixed ft_fixup_port for dual-role mEMAC, which will lead to MAC node disabled incorrectly. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * t4240qds/eth: fixup ethernet for t4240qdsShengzhou Liu2013-05-14-18/+91
| | | | | | | | | | | | | | | | | | | | | | 1, Implemented board_ft_fman_fixup_port() to fix port for kernel. 2, Implemented fdt_fixup_board_enet() to fix node status of different slots and interfaces. 3, Adding detection of slot present for XGMII interface. 4, There is no PHY for XFI, so removed related phy address settings. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: add missing QMAN frequency calculationShaohui Xie2013-05-14-0/+4
| | | | | | | | | | | | | | | | When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not be initialized, and QMAN will have a wrong frequency display. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc: Add T4160QDSYork Sun2013-05-14-1/+17
| | | | | | | | | | | | | | | | | | T4160QDS shares the same platform as T4240QDS. T4160 is a low power version of T4240, with eight e6500 cores, two DDR3 controllers, and slightly different SerDes protocols. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/t4240qds: Move SoC define into boards.cfgYork Sun2013-05-14-4/+3
| | | | | | | | | | | | | | | | Separate CONFIG_PPC_T4240 from board config file. Prepare to add more SoC variants supported on the same board. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Add T4160 SoCYork Sun2013-05-14-2/+173
| | | | | | | | | | | | | | | | | | | | T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/t4240: Fix SerDes protocol arrays with const prefixYork Sun2013-05-14-7/+7
| | | | | | | | | | | | | | Protocols are constants. Fix arrays with const prefix. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Fix PIR parsing for chassis2York Sun2013-05-14-3/+3
| | | | | | | | | | | | | | | | The PIR parsing algorithm we used is not only for E6500. It applies to all SoCs with chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/corenet2: Print SerDes protocol in decimalYork Sun2013-05-14-1/+1
| | | | | | | | | | | | | | | | Use decimal and hexadecimal for protocol numbers. It helps to match with SoC user manual. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * T4/USB: Add USB 2.0 UTMI dual phy supportRoy Zang2013-05-14-2/+63
| | | | | | | | | | | | | | | | | | | | | | | | T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/t4240qds: Add voltage ID supportYork Sun2013-05-14-2/+239
| | | | | | | | | | | | | | | | T4240 has voltage ID fuse. Read the fuse and configure the voltage correctly. Core voltage has higher tolerance on over side than below. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Fix portal setupYork Sun2013-05-14-14/+22
| | | | | | | | | | | | | | | | | | Missing nodes of crypto, pme, etc in device tree is not a fatal error. Setting up the qman portal should skip the missing node and continue to finish the rest. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Fix DDR 3-way interleavingYork Sun2013-05-14-8/+11
| | | | | | | | | | | | | | Should check if interleaving is enabled before using interleaving mode. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/t4240qds: Update DDR timing tableYork Sun2013-05-14-22/+34
| | | | | | | | | | | | | | | | | | | | Update the timing table to support more rank density, based on the theory that similar density DIMMs have similar clock adjust and write level start timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * T4/SerDes: correct the SATA indexRoy Zang2013-05-14-2/+2
| | | | | | | | | | | | | | | | Lane H on SerDes4 should be SATA2 instead of SATA1 Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Fman/t4240: some fix for 10G XAUIShaohui Xie2013-05-14-6/+20
| | | | | | | | | | | | | | | | | | | | 1. fix 10G mac offset by plus 8; 2. add second 10G port info for FM1 & FM2 when init ethernet info; 3. fix 10G lanes name to match lane protocol table; Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/t4240qds: fix XAUI card PHY addressShaohui Xie2013-05-14-4/+4
| | | | | | | | | | | | Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * T4/serdes: fix the serdes clock frequencyRoy Zang2013-05-14-2/+2
| | | | | | | | | | | | | | | | | | | | Reverse the bit sequence to set and display serdes clock frequency correctly. The correct bit maps in BRDCFG2 are 0 1 2 3 4 5 6 7 S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0] Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * e6500: Move L1 enablement after L2 enablementAndy Fleming2013-05-14-47/+47
| | | | | | | | | | | | | | | | | | | | The L1 D-cache on e6500 is write-through. This means that it's not considered a good idea to have the L1 up and running if the L2 is disabled. We don't actually *use* the L1 until after the L2 is brought up on e6500, so go ahead and move the L1 enablement after that code is done. Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/t4240qds: Fix SPI flash typeShaohui Xie2013-05-14-1/+1
| | | | | | | | | | | | | | T4240QDS uses a SST instead of SPANSION SPI flash. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Update corenet global utility block registersYork Sun2013-05-14-11/+10
| | | | | | | | | | | | | | | | Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse status register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Add definitions for HDBCR registersAndy Fleming2013-05-14-8/+18
| | | | | | | | | | | | | | | | Makes it a bit easier to see if we've properly set them. While we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually use those definitions. Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/B4860: Corrected FMAN1 operating frequency print at u-bootSandeep Singh2013-05-14-0/+8
| | | | | | | | | | | | | | | | | | The bit positions for FMAN1 freq in RCW is different for B4860. Also addded a case when FMAN1 frewuency is equal to systembus. Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Power: remove support for Freescale MPC8220Wolfgang Denk2013-05-15-9539/+5
| | | | | | | | | | | | | | | | | | | | The Freescale MPC8220 Power Architecture processors have long reached EOL; Freescale does not even list these any more on their web site. Remove the code to avoid wasting maitaining efforts on dead stuff. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andy Fleming <afleming@gmail.com>
* | doc/README.scrapyard: add missing commit IDsWolfgang Denk2013-05-15-2/+2
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | drivers/mmc: move spl_mmc.c to common/splYing Zhang2013-05-15-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mpc85xx repuires a special layout on the memory device that is connected to the eSDHC controller interface. But the file spl_mmc.c didn't handle this specfic case, there needs a special treatmen, in the powerpc drictory. So, there is no longer to keep spl_mmc.c on mpc85xx, CONFIG_SPL_FRAMEWORK is not set. When CONFIG_SPL_MMC_SUPPORT is set and CONFIG_SPL_FRAMEWORK is not set, there was an error in drivers/mmc/spl_mmc.c: drivers/mmc/libmmc.o:(.got2+0x8): undefined reference to `spl_image'. Now, the solution is to move the file "spl_mmc.c" to directory "common/spl". Signed-off-by: Ying Zhang <b40530@freescale.com>
* | smc911x: fix the timeout detectionMasahiro Yamada2013-05-15-2/+2
| | | | | | | | | | | | | | If timeout is occurred at the while loop above, the value of 'timeout' is -1, not 0. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
generated by cgit v1.1 at 2024-12-26 02:25:55 +0000