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* powerpc/pcie: add PCIe version 3.x supportZang Roy-R619112013-08-09-15/+48
| | | | | | | | | | | | | | | | | | | | | | | | | T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/rman: fix RMan support for t4240 and b4860Minghuan Lian2013-08-09-8/+12
| | | | | | | | | | | | 1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860. 2. Decrease RMan liodn offset number. SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3. For t4240 and b4860, RMan liodn base is assigned to 922, the original offset number is too large that the liodn (base+offset 922+678 = 1600) is greater than 0x500 the maximum liodn number. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* board/b4860qds: Add support for configuring SerDes1 RefclksShaveta Leekha2013-08-09-2/+119
| | | | | | | | | | | | | | | | | | 1) Add support in B4860 board files for using IDT driver where IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer that generate different refclks for SerDes modules, used this driver for reconfiguring SerDes1 Refclks(based on SerDes1 protocols) for CPRI to work. CPRI works on 122.88MHz and default refclks coming on board are not suitable for it 2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file to b4860qds board file, as SerDes1 Refclk1 would come from PHY MUX in case of certain protocols, that have been checked here. This change would make on board SGMIIs to work 3) Add I2C addresses for IDT8T49N222A devices in board/include file 4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/asm: Move function declaration of 'serdes_get_prtcl' to fsl_serdes.hShaveta Leekha2013-08-09-1/+1
| | | | | | | It allows files not in the same path to use this function as required by B4 board file Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
* powerpc/mpc85xx: Add defines for serdes RSTCTL registerShaveta Leekha2013-08-09-1/+3
| | | | | | | | Also change the define name SRDS_RSTCTL_SDPD to SRDS_RSTCTL_SDEN, which stands for SerDes enable as mentioned in SerDes module guide Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
* board/freescale/common: IDT8T49N222A configuration codeShaveta Leekha2013-08-09-0/+341
| | | | | | | | | | | | | Add code for configuring IDT8T49N222A device for various output refclks - The IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer with alarm and monitoring functions suitable for networking and communications applications. It is able to generate wide range of output frequencies. - In B4860QDS, it has been used to generate different refclks to SerDes modules - Programming of these devices are performed by I2C interface. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* board/bsc9132qds: Configure DSP DDR controllerPriyanka Jain2013-08-09-0/+28
| | | | | | | | | | | | | | BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* board/bsc9132qds: Add DSP side tlb and lawsPriyanka Jain2013-08-09-1/+34
| | | | | | | | | | | | | | | BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a integrated device that contains two powerpc e500v2 cores and two DSP starcores. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 and M3 memory -Creating LAW for 1GB DDR which is connected exclusively to DSP-cores Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIELiu Gang2013-08-09-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When a board (slave) boots from SRIO/PCIE, it would get the instructions from a remote board (master) by SRIO/PCIE interface, and the slave's u-boot image should be built with the SYS_TEXT_BASE=0xFFF80000; So the u-boot of the slave should avoid the NOR_BOOT branch at the booting stage. For example, when a P2041RDB boots from SRIO/PCIE, it will set TLB entry 15 from base address "CONFIG_SYS_MONITOR_BASE & 0xffc00000", and with the 4M size as the boot window in NOR_BOOT branch. Because the CONFIG_SYS_MONITOR_BASE = CONFIG_SYS_TEXT_BASE = 0xFFF80000, so the TLB entry will be from base address 0xffc00000 and with 4M size. Then the u-boot will set TLB entry 14 from base address "CONFIG_SYS_INIT_RAM_ADDR", and with the 16K size as the initial stack window. For the P2041RDB platform, the CONFIG_SYS_INIT_RAM_ADDR = 0xffd00000. So the TLB entry 14 and 15 will be in confliction. There will be right TLB entries configurations when avoid the NOR_BOOT branch and set the boot window from 0xfff00000 with 1M size space. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
* p1020rdb-pd: platform supportHaijun.Zhang2013-08-09-14/+63
| | | | | | | | | | | | | | Add new board p1020RDB-PD. P1020RDB-PD board was update from P1020RDB. DDR changed from DDR2 1G to DDR3 2G. NAND: 128 MiB Flash: 64 MiB Also change P1020RDB to P1020RDB-PC to distinguish from P1020RDB board. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> CC: Scott Wood <scottwood@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Workaround for A-005812York Sun2013-08-09-0/+29
| | | | | | | | Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can result in invalid atomic operations. For u-boot, this erratum only impacts SoCs running in write shadow mode. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: Add memory reset controlYork Sun2013-08-09-21/+131
| | | | | | | | | JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: Add x4 DDR device supportYork Sun2013-08-09-0/+13
| | | | | | | | | On selected platforms, x4 DDR devices can be supported. Using x4 devices may lower the performance, but generally they are available for higher density. Tested on MT36JSF2G72PZ-1G9E1 RDIMM. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/t4240qds: Adjust DDR timing for RDIMMYork Sun2013-08-09-10/+9
| | | | | | | RDIMM has different timing. Tested RDIMM is MT18JSF1G72PDZ-1G9E1 for dual rank. Single- and quad-rank are not tested due to availability. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffffYork Sun2013-08-09-3/+9
| | | | | | | | | | | | When chip select interleaving is enabled, cs0_bnds is used for address binding. Other csn_bnds are not used. When two controllers interleaving is enabled, cs0_bnds of both controllers are used, other csn_bnds are not. However, the unused csn_bnds may be used internally for calculating addresses for calibration. Setting those registers to 0 may confuse controllers in some cases. Instead, setting them to 0xffffffff together with normal LAWs will guarantee the address is not mapped to DDR. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/T4240EMU: Add T4240EMU targetYork Sun2013-08-09-609/+1006
| | | | | | | | | | | | Add emulator support for T4240. Emulator has limited peripherals and interfaces. Difference between emulator and T4240QDS includes: ECC for DDR is disabled due the procedure to load images No board FPGA (QIXIS) NOR flash has 32-bit port for higher loading speed IFC and I2C timing don't really matter, so set them fast No ethernet Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/corenet: Move RCW print to cpu.cYork Sun2013-08-09-62/+22
| | | | | | | The RCW print is common for all corenet platforms. Not necessary to ducplicate in each board file. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/t4qds: cleanup board header fileYork Sun2013-08-09-68/+0
| | | | | | CONFIG_PHYS_64BIT is always defined for t4qds. Removed unused #ifdef. Signed-off-by: York Sun <yorksun@freescale.com>
* mpc85xx: Base emulator supportYork Sun2013-08-09-1/+23
| | | | | | | | | Prepare for emulator support for mpc85xx parts. Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers. These two registers improve stability but not supported by emulator. Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base. Signed-off-by: York Sun <yorksun@freescale.com>
* drivers/fm: Fix compiling error if FW location is not definedYork Sun2013-08-09-0/+2
| | | | | | | FMAN firmware can be in NOR flash, NAND flash, SPI flash, MMC or even remote. In case none of them is defined, set it to null. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/corenet: Move CONFIG_FSL_CORENET out of board header fileYork Sun2013-08-09-4/+5
| | | | | | | Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board specific feature and belongs to SoC header. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/t4: Correct LIODN assignment for SRIOLiu Gang2013-08-09-2/+3
| | | | | | | For T4 platform, the SRIO LIODN registers are in SRIO address space and not in GUTs. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
* powerpc/b4860: Correct LIODN assignment for SRIOLiu Gang2013-08-09-2/+3
| | | | | | | For B4, the SRIO LIODN registers are in SRIO address space and not in GUTs. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
* powerpc/srio: Update the SRIO LIODN registers and ID table macroLiu Gang2013-08-09-0/+23
| | | | | | | | | | | | For some PowerPC platforms, LIODN registers for SRIO ports are in SRIO register address space. So the ccsr_rio structure should be updated for those LIODN registers. In addition, add a new macro "SET_SRIO_LIODN_BASE" to create the SRIO LIODN ID table based on the SRIO LIODN register address. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/85xx: Add TWR-P10xx board supportXie Xiaobo2013-08-09-0/+1180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TWR-P1025 Specification: ----------------------- Memory subsystem: 512MB DDR3 (on board DDR) 64Mbyte 16bit NOR flash One microSD Card slot Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC3: Connected to Atheros AR8035 GETH PHY UART: Two UARTs are routed to the FDTI dual USB to RS232 convertor USB: Two USB2.0 Type A ports I2C: AT24C01B 1K Board EEPROM (8 bit address) QUICC Engine: Connected to DP83849i PHY supply two 10/100M ethernet ports QE UART for RS485 or RS232 PCIE: One mini-PCIE slot Signed-off-by: Michael Johnston <michael.johnston@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> [yorksun: Fixup include/configs/p1_twr.h] Signed-off-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-08-06-6/+6
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| * i2c: soft: Fix typo in CONFIG_SYS_I2C_SOFT_SPEEDMarek Vasut2013-08-03-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case only the CONFIG_SYS_I2C_SPEED is set in configuration file, the CONFIG_SYS_I2C_SOFT_SPEED is defined as CONFIG_SYS_I2C_SPEED. The CONFIG_SYS_I2C_SOFT_SPEED is then used throughout the driver. Unfortunatelly, due to a typo in the driver, instead of defining CONFIG_SYS_I2C_SOFT_SPEED, an CONFIG_SYS_SOFT_I2C_SPEED was defined and therefore the driver failed to compile. The same applies for CONFIG_SYS_I2C_SOFT_SLAVE , where the swap happens as well. This patch fixes the issue. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de>
* | dts/Makefile: pass -undef -D__DTS__ to cppStephen Warren2013-08-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This brings U-Boot's cpp invocation into line with the way the Linux kernel invokes cpp on device trees. Consistency will be useful to ensure *.dts is portable between the two. -undef also has the added advantage of not defining "linux", so DT property names such as "linux,keymap" don't get mangled. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dts/Makefile: don't use cpp -PStephen Warren2013-08-02-1/+1
| | | | | | | | | | | | | | | | | | Recent dtc supports #line directives in the input source code, and even uses them to generate useful line numbers in any messages it emits. Stop passing -P to cpp, since there's no need any more. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | config: don't define CONFIG_ARCH_DEVICE_TREEStephen Warren2013-08-02-60/+1
| | | | | | | | | | | | | | Now that nothing uses CONFIG_ARCH_DEVICE_TREE, stop defining it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dts/Makefile: don't define ARCH_CPU_DTS, BOARD_DTSStephen Warren2013-08-02-7/+0
| | | | | | | | | | | | | | | | Now that nothing uses the defines ARCH_CPU_DTS, BOARD_DTS, stop defining them. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dt: don't use ARCH_CPU_DTSStephen Warren2013-08-02-3/+3
| | | | | | | | | | | | | | | | | | Now that we assume dtc supports the -i option, we don't need to use ARCH_CPU_DTS in *.dts{,i}; we simply specify the include filename directly, and dtc will find it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dts/Makefile: unify cpp/dtc include pathsStephen Warren2013-08-02-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | *.dts may use #include (via cpp) or /include/ (via dtc; assuming a newer dtc). The choice is up to the creator of the DT. Create a common variable DTC_INCDIRS that lists the paths searched by include statements, and update cpp and dtc invocation to use them. For cpp, also specify -nostdinc to ensure the same set of paths is available to both type of include statement. For dtc, create a new DTC_FLAGS variable to hold all the flags passed to dtc. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dts/Makefile: simplify dtc invocationStephen Warren2013-08-02-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The invocation of dtc is significantly more complex that it could be, in order to work around an issue on old versions of dtc, which print a message to stdout every time they run. Remove this workaround, on the assumption that people have or will upgrade to a newer version of dtc. This simplifies the build rule significantly. Related, split the invocation of cpp and dtc into separate commands rather than a pipeline, so that if either fail, it is detected. This has the nice benefit of saving off the result of the pre-processing step, allowing it to be easily inspected. Assuming a new enough dtc (which an earlier patch enforces), dtc will parse #line directives in its input file, and generate correct file and line numbers in error messages, even though cpp is unconditionally applied to its input file. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | xilinx: move microblaze-generic .dts to standard locationStephen Warren2013-08-02-2/+1
| | | | | | | | | | | | | | | | | | | | Aside from microblaze, all other SoCs/boards/vendors store their DT files in board/$vendor/dts/$soc-$board.dts. Move microblaze-generic.dts to this location for consistency. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Michal Simek <monstr@monstr.eu>
* | Validate dtc is new enoughStephen Warren2013-08-02-1/+28
|/ | | | | | | | | Subsequent patches assume that dtc supports various recent features. These are available in dtc 1.4.0. Validate that dtc is at least that version. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2013-08-01-158/+423
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| * ehci-hcd: fix memory leak in lowlevel initNikita Kiryanov2013-07-29-1/+3
| | | | | | | | | | | | | | | | | | | | usb_lowlevel_init() allocates a new periodic_list each time it is invoked, without freeing the original list. Since it is initialized later on in the code, just reuse the first-allocated list in future invocations of usb_lowlevel_init. Cc: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| * usb_hub: fix power cycling logicNikita Kiryanov2013-07-29-2/+2
| | | | | | | | | | | | | | | | | | | | | | When power cycling the hub ports, a misbehaving port will prevent all ports from being powered on because we quit at the first sign of trouble. Skip problematic ports instead of failing the entire power on. Cc: Marek Vasut <marex@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| * usb: ehci-omap: Don't softreset USB High-speed Host (UHH) ModuleRoger Quadros2013-07-29-12/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes NFS root problems with Beagle (3530 ES1.0) when used with external USB-ethernet adapter and "USB start" command used within u-boot. Soft resetting the UHH module causes instability issues on all OMAPs so we just avoid it. See OMAP36xx Errata i571: USB host EHCI may stall when entering smart-standby mode i660: USBHOST Configured In Smart-Idle Can Lead To a Deadlock On OMAP4/5, soft-resetting the UHH module can put it into Smart-Idle mode and lead to a deadlock. On OMAP3 this doesn't seem to be the case but still instabilities are observed on beagle (3530 ES1.0) if soft-reset is used. e.g. NFS root failures with Linux kernel. Signed-off-by: Roger Quadros <rogerq@ti.com>
| * dfu: Implementation of target reset after communication with dfu-util's -R ↵Lukasz Majewski2013-07-29-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | switch This patch extends dfu code to support transmission with -R switch specified at dfu-util. When -R is specified, the extra USB_REQ_DFU_DETACH request is sent after successful data transmission. Then dfu resources are released and reset command is issued. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
| * usb: mv_udc: Add bounce bufferMarek Vasut2013-07-29-8/+82
| | | | | | | | | | | | | | | | | | | | | | | | The requests sent to the controller are not properly cache aligned most of the time, thus implement a simple bounce buffer to avoid problem with cache. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * usb: mv_udc: Add proper cache managementMarek Vasut2013-07-29-5/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement functions to flush/invalidate dcache over QH and qTDs and make use of them where appropriate. Also use them to replace the old incorrect cache management attempt. This is the first step towards making this driver work with data cache enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * usb: mv_udc: Implement better qTD item accessorMarek Vasut2013-07-29-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | The code for retrieving qTD item for particular endpoint is hard to understand, moreover it's duplicated all over the driver. Move the code into single nice and documented function. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * usb: mv_udc: Improve allocation of qTD itemsMarek Vasut2013-07-29-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | Allocate the qTD items all at once instead of allocating them separately. Moreover, make sure each qTD is properly aligned to 32-bytes boundary and that cache can be safely flushed over each qTD touple. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * usb: mv_udc: Implement better QH accessorMarek Vasut2013-07-29-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | The code for retrieving QH for particular endpoint is hard to understand, moreover it's duplicated all over the driver. Move the code into single nice and documented function. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * usb: mv_udc: Add cacheline length checkMarek Vasut2013-07-29-0/+10
| | | | | | | | | | | | | | | | | | | | | | Check the length of system cacheline at compile-time and fail if the system uses too long cachelines. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * usb: mv_udc: Properly align the endpoint QH and qTD listMarek Vasut2013-07-29-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The endpoint QH list has to be aligned to 10-bit boundary. We also have to make sure the list is aligned on a cacheline boundary. Make sure it is. Furthermore, check if the memory allocation for the QH list didn't fail. Moveover, improve the comment about the QH list structure. Finally, the qTD item list has to be aligned only to 5-bit boundary, not 10-bit as it is now, fix this as well. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * usb: mv_udc: Move QH and qTD into mv_drvMarek Vasut2013-07-29-13/+15
| | | | | | | | | | | | | | | | | | | | | | Both the endpoint queue head and the endpoint item list is a controller specific thing. Move them both into controller private data. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * usb: mv_udc: Init mv_drv.gadget.ops staticallyMarek Vasut2013-07-29-3/+3
| | | | | | | | | | | | | | | | | | | | There is no need to init this field at runtime, so init it statically. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
generated by cgit v1.1 at 2024-12-23 15:50:27 +0000