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* PCIe, USB: Replace 'end point' references with 'endpoint'Peter Tyser2010-01-17-40/+40
| | | | | | | | | When referring to PCIe and USB 'endpoint' is the standard naming convention. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Remy Bohmer <linux@bohmer.net>
* Make getenv_IPaddr() globalDirk Behme2010-01-17-29/+58
| | | | | | | | | | | | | | | | | | | There are boards out there that do not have network support in U-Boot (CONFIG_CMD_NET not set), but they do so in Linux. This makes it desirable to be able to port network configuration (like the IP address) to the Linux kernel. We should not make the passing of the IP configuration to Linux dependent on U-Boot features / settings. For this, make getenv_IPaddr() global. This fixes build error u-boot/lib_xxx/board.c:360: undefined reference to `getenv_IPaddr' on various architectures. Signed-off-by: Dirk Behme <dirk.behme@googlemail.com> Acked-by: Ben Warren <biggerbadderben@gmail.com>
* malloc: return NULL if not initialized yetWolfgang Denk2010-01-15-0/+6
| | | | | | | | | | | When malloc() was called before it was properly initialized (as would happen if when used before relocation to RAM) it returned random, non-NULL values, which called all kinds of difficult to debug subsequent errors. Make sure to return NULL when initialization was not done yet. Signed-off-by: Wolfgang Denk <wd@denx.de>
* JFFS2: drop support for LZARI compression modeWolfgang Denk2010-01-15-279/+38
| | | | | | | | | | | | | | | | | | Support for LZARI compression mode was added based on a MTD CVS snapshot of March 13, 2005. However, fs/jffs2/compr_lzari.c contains contradictory licensing terms: the original copyright clause says "All rights reserved. Permission granted for non-commercial use.", but later reference to the file 'LICENCE' in the jffs2 directory was added which says GPL v2 or later. As no boards ever used LZARI compression, and this file is also not present in recent MTD code, we resolve this conflict by removing the conflicting file and references to it. Also copy the referenced but missing file 'LICENCE' from the current MTD source tree. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-01-12-72/+723
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| * ARM Update mach-typesTom Rix2010-01-06-10/+621
| | | | | | | | | | | | | | | | | | | | Fetched from http://www.arm.linux.org.uk/developer/machines/download.php And built with repo http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm commit c9f937e4a3f4ebf9924ec21d80632e5eb61d949c Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
| * Davinci: NAND enable ECC even when not in NAND boot modeNick Thompson2010-01-04-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | Davinci: NAND enable ECC even when not in NAND boot mode On Davinci platforms, the default NAND device is enabled (for ECC) in low level boot code when NAND boot mode is used. If booting in another mode, NAND ECC is not enabled. The driver should make sure ECC is enabled regardless of boot mode if NAND is configured in U-Boot. Signed-off-by: Nick Thompson <nick.thompson@ge.com>
| * Davinci: Configurable NAND chip selectsNick Thompson2010-01-04-18/+29
| | | | | | | | | | | | | | | | | | | | Davinci: Configurable NAND chip selects Add a CONFIG_SYS_NAND_CS setting to all davinci configs and use it to setup the NAND controller in the davinci_nand mtd driver. Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
| * Davinci: Table driven pinmux configurationNick Thompson2010-01-04-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Davinci: Table driven pinmux configuration Add code to allow pinmux_config tables to be grouped and configured as a single resource. This removes multiple calls to the pinmux configuration code from board_init and allows pinmuxes to be individually configured and added by data manipulation only. All related #ifdefs can the be removed from board_init code and since the compiler optimises away statics, #ifdefs can be reduced in the data definitions as well. Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
| * Remove superfluous uses of V_PROMPT macro.Robert P. J. Day2010-01-04-25/+10
| | | | | | | | | | | | | | | | A number of config files define the V_PROMPT macro for the command-line prompt, only to immediately use that macro to define CONFIG_SYS_PROMPT, making V_PROMPT entirely superfluous. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
| * pandora: don't enable VAUX3, VDAC and VPLL2 regulatorsGrazvydas Ignotas2010-01-04-1/+0
| | | | | | | | | | | | | | | | These regulators are not needed to start the kernel and only cause "incomplete constraints" warnings from kernel, so don't turn them on to save power. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
| * TWL4030: make LEDs selectable for twl4030_led_init()Grazvydas Ignotas2010-01-04-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | Not all boards have both LEDs hooked, so enabling both on boards with single LED will just waste power. Make it possible to choose LEDs by adding argument to twl4030_led_init(). Using this turn on only LEDB for pandora, leave both LEDs on for all other boards, as it was before this patch. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashWolfgang Denk2010-01-12-55/+154
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| * | onenand: Fix compile errors due to FlexOneNANDSanjeev Premi2010-01-06-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the compile error while trying to compile for omap3evm. env_onenand.c: In function 'env_relocate_spec': env_onenand.c:70: error: 'CONFIG_ENV_ADDR_FLEX' undeclared (first use in this function) env_onenand.c:70: error: (Each undeclared identifier is re ported only once env_onenand.c:70: error: for each function it appears in.) env_onenand.c: In function 'saveenv': env_onenand.c:106: error: 'CONFIG_ENV_ADDR_FLEX' undeclare d (first use in this function) env_onenand.c:107: error: 'CONFIG_ENV_SIZE_FLEX' undeclare d (first use in this function) Signed-off-by: Sanjeev Premi <premi@ti.com> Acked-by: Tom Rix <Tom.Rix@windriver.com>
| * | Davinci: davinci_nand.c performance enhancmentsNick Thompson2010-01-06-54/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduces various optimisations that approximately triple the read data rate from NAND when run on da830evm. Most of these optimisations depend on the endianess of the machine and most of them are very similar to optimisations already present in the Linux Kernel. Signed-off-by: Nick Thompson <nick.thompson@ge.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbWolfgang Denk2010-01-12-15/+1415
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| * | | usb: musb: add virtual root hub control supportBryan Wu2010-01-12-2/+482
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For MUSB devices that do not support multipoint (hubs), we have to emulate a root hub so that we can support core operations like resetting ports. Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | | Adds EHCI definitions to sequoia board configuration file.Chris Zhang2010-01-09-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds required definitions for EHCI support in sequoia configuration file. But still keeps the OHCI as default driver. Signed-off-by: Chris Zhang <chris@seamicro.com>
| * | | Add ppc440epx USB ehci support.Chris Zhang2010-01-09-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently ppc440epx uses OHCI for USB full-speed support. This change adds support for EHCI. Signed-off-by: Chris Zhang <chris@seamicro.com>
| * | | Fix EHCI port reset.Chris Zhang2010-01-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In USB ehci driver, the port reset is not terminated. EHCI spec says "A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds". Without termination, a port stays at reset state. This is observed on ppc4xx(sequoia) boards. Signed-off-by: Chris Zhang <chris@seamicro.com>
| * | | omap3: fix compile warningSanjeev Premi2010-01-09-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes this warning during compile: omap3.c: In function 'musb_platform_init': omap3.c:126: warning: label 'end' defined but not used Problem reported by: Dirk Behme[dirk.behme@googlemail.com] Signed-off-by: Sanjeev Premi <premi@ti.com>
| * | | usb: musb: add support for Blackfin MUSBBryan Wu2010-01-09-2/+528
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Remy Bohmer <linux@bohmer.net>
| * | | usb: musb: change rxcsr register from write to read/modify/writeBryan Wu2010-01-09-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RX Control/Status register has bits that we want to preserve, so don't just write out a single bit. Preserve the others bits in the process. The original code posted to the u-boot list had this behavior, but looks like it was lost somewhere along the way to merging. Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Remy Bohmer <linux@bohmer.net>
| * | | usb: musb: make multipoint optionalBryan Wu2010-01-09-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The multipoint handling under MUSB is optional, and some parts (like the Blackfin processor) do not implement support for it. Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Remy Bohmer <linux@bohmer.net>
| * | | usb: musb: make fifo support configurableBryan Wu2010-01-09-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dynamic FIFO handling under MUSB is optional, and some parts (like the Blackfin processor) do not implement support for it. Due to this, the FIFO reading/writing steps need special handling, so mark the common versions weak so drivers can override. Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Remy Bohmer <linux@bohmer.net>
| * | | usb: musb: make sure the register layout is packedMike Frysinger2010-01-09-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Remy Bohmer <linux@bohmer.net>
| * | | DA830: Add usb configAjay Kumar Gupta2010-01-09-5/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding USB configuration. Default is set for USB MSC host. Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: Swaminathan S <swami.iyer@ti.com>
| * | | DA8xx: Add MUSB host supportAjay Kumar Gupta2010-01-09-1/+244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested USB host functionality on DA830 EVM. Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: Swaminathan S <swami.iyer@ti.com>
| * | | DA8xx: Add GPIO register definitionsAjay Kumar Gupta2010-01-09-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added DA8xx GPIO base addresses in gpio_defs.h and pointers to different BANKs which can be used to program GPIOs. Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: Swaminathan S <swami.iyer@ti.com>
| * | | DA830: Add pinmux for USB0_DRVVBUSAjay Kumar Gupta2010-01-09-0/+8
| |/ / | | | | | | | | | | | | | | | | | | | | | USB0_DRVVBUS pinmux configuration is required for USB functinality in uboot. Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com> Signed-off-by: Swaminathan S <swami.iyer@ti.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2010-01-12-131/+455
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| * | | mpc83xx: add support configure bus parkingHeiko Schocher2010-01-07-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to configure bus parking mode and master in bus arbitration configuration (ACR). Add this for the kmeter1 port: Configure bus arbiter with recommended values from Freescale to improve bus latency/throughput for application with intensive QuiccEngine activity. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | mpc83xx: vme8349: Fix power up reset sequence for tsi148Reinhard Arlt2010-01-07-8/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove PCI reset, if there is a monarch PMC module. Signed-off-by: Reinhard Arlt <reinhard.arlt@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de> convert clrbits_be32 + setbits_be32 to clrsetbits_be32, use out_be32 to set gcr. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | mpc83xx: Add support for MPC8349 esd caddy2Reinhard Arlt2010-01-07-100/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The caddy2 is a variant of the already supported vme8349. So we just add the differences to this board port. To better support those two boards we switched from fixed SDRAM configuration to usage of spd_sdram(). This is done by providing a board specific SPD EEPROM routine with different values for both boards. Signed-off-by: Reinhard Arlt <reinhard.arlt@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de> changed to use mkconfig -t option instead, plus misc codingstyle fixes. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | mpc83xx: spd_sdram.c: Disable memory controller before initializingStefan Roese2010-01-07-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory controller could already be enabled, when spd_sdram() is called. This could be the case for example, when the SDRAM is initialized by the JTAG debugger. The "sync" after the register access via the accessor function is still needed, because the macro uses the sync before the real write is done. So until not all accesses are converted to using accessor functions, this sync still needs to be made "manually" here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd.eu> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | mpc83xx: Add NAND boot support for MPC8315E-RDB boardsAnton Vorontsov2010-01-07-23/+167
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core support for NAND booting is there already, so this patch is pretty straightforward. There is one trick though: top level Makefile expects nand_spl to be in nand_spl/board/$(BOARDDIR), but we can fully reuse the code from mpc8313erdb boards, and so to not duplicate the code we just symlink nand_spl/board/freescale/mpc8315erdb to mpc8313erdb. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> o silence make during ln echo o update documentation o and avoid: $ ./MAKEALL MPC8315ERDB_NAND Configuring for MPC8315ERDB board... sdram.o: In function `fixed_sdram': /home/r1aaha/git/u-boot/nand_spl/board/freescale/mpc8313erdb/sdram.c:72: undefined reference to `udelay' by renaming udelay -> __udelay in the spirit of commit 3eb90bad651fab39cffba750ec4421a9c01d60e7 "Generic udelay() with watchdog support". Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | | ppc/p4080: Add Corenet Platform Cache (CPC) registersBecky Bruce2010-01-05-0/+75
| | | | | | | | | | | | | | | Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleaveDave Liu2010-01-05-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | In chip-select interleaving case, we also need set the ODT_RD_CFG and ODT_WR_CFG in cs1_config register. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | fsl-ddr: add override for the Rtt_WrDave Liu2010-01-05-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Different boards may require different settings of Dynamic ODT (Rtt_Wr). We provide a means to allow the board specific code to provide its own value of Rtt_Wr. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | fsl-ddr: add the override for write levelingDave Liu2010-01-05-7/+21
| | | | | | | | | | | | | | | | | | | | | | | | add the override for write leveling sampling and start time according to specific board. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | fsl-ddr: Fix power-down timing settingsDave Liu2010-01-05-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but It should be set to tXP parameter, tXP=max(3CK, 7.5ns) 2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter We are setting the mode register MR0[A12]='1' Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | mpc85xx: Add 4-bits eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2010-01-05-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Thanks to "Errata to MPC8569E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 0" document, which describes all eSDHC pins, we can add 4-bits eSDHC support for MPC8569E-MDS boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | ppc/p4080: Fix reporting of PME & FM clock frequenciesKumar Gala2010-01-05-6/+6
| | | | | | | | | | | | | | | | | | | | | We incorrectly had the sense of PME_CLK_SEL, FM1_CLK_SEL, FM2_CLK_SEL backwards so we report the wrong frequency. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | fsl_law: add SRIO2 target id and law_size_bits() macroLi Yang2010-01-05-0/+3
| | | | | | | | | | | | | | | Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | ppc/85xx: Map boot page guarded for MP bootKumar Gala2010-01-05-6/+6
| | | | | | | | | | | | | | | | | | | | | We already map the page cache-inhibited. There is no reason we shouldn't also be marking it guarded to prevent speculative accesses. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | ppc: Added macro to test for specific SVR revisionKumar Gala2010-01-05-0/+3
| | | | | | | | | | | | | | | | | | | | | Various SoC errata are specific to a given revision of silicon. This patch gives us a simple macro to use when doing such tests. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | p4080: add readback to bootpage translation windowDave Liu2010-01-05-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | We need to add the readback to bootpage translation LAW to make it effect. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | ppc/85xx: Make flash TLB entry determined at runtime on FSL boardsKumar Gala2010-01-05-4/+4
| | | | | | | | | | | | | | | | | | | | | Rather than hard coding which TLB entry the FLASH is mapped with we can use find_tlb_idx to determine the entry. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | ppc/85xx: Remove CONFIG_SYS_DDR_TLB_STARTKumar Gala2010-01-05-4/+0
| | | | | | | | | | | | | | | | | | | | | Now that we dynamically determine TLB CAM entries to use we dont need CONFIG_SYS_DDR_TLB_START anymore. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocationKumar Gala2010-01-05-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Now that we track which TLB CAM entries are used we can allocate entries on the fly. Change the SPD DDR TLB setup code to assume we use at most 8 TLBs (or the number free, which ever is fewer). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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