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* powerpc/t2080qds: add support for t2080qds boardShengzhou Liu2013-11-25-0/+2126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The T2080QDS is a high-performance computing evaluation, development and test platform supporting the T2080 QorIQ Power Architecture processor. T2080QDS feature overview Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz Memory: - Single memory controller capable of supporting DDR3 and DDR3-LV devices - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support Ethernet interfaces: - Two 1Gbps RGMII on-board ports - Four 10Gbps XFI on-board cages - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes: - 16 lanes up to 10.3125GHz - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI IFC: - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA eSPI: - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) USB: - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB) PCIE: - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) SATA: - Two SATA 2.0 ports on-board SRIO: - Two Serial RapidIO 2.0 ports up to 5 GHz eSDHC: - Supports SD/SDHC/SDXC/eMMC Card I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports System Logic: - QIXIS-II FPGA system controll Debug Features: - Support Legacy, COP/JTAG, Aurora, Event and EVT Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: removed Makefile blank line at EOF, fix conflicts with moving DDR driver] Acked-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Add T2080/T2081 SoC supportShengzhou Liu2013-11-25-1/+512
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* net/fman: Add support for 10GEC3 and 10GEC4Shengzhou Liu2013-11-25-6/+48
| | | | | | | There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* Driver/IFC: Move Freescale IFC driver to a common driverYork Sun2013-11-25-13/+13
| | | | | | | | Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: Update DDR driver to allow non-zero base addressYork Sun2013-11-25-3/+3
| | | | | | | The DRAM base has been zero for Power SoCs. It could be non-zero for ARM SoCs. Use a macro instead of hard-coding to zero. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: Extend DDR registers' fieldsYork Sun2013-11-25-8/+12
| | | | | | | | | | | Some DDR registers' fields have expanded to accommodate larger values. These changes are backward compatible. Some fields are removed for newer DDR controllers. Writing to those fields are safely ignored. TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE automatically. It was a misunderstanding in commit c360ceac. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: Add Freescale DDR driver for ARMYork Sun2013-11-25-4/+230
| | | | | | | Make PowerPC specific code conditional so ARM SoCs can reuse this driver. Add DDR3 driver for ARM. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xxYork Sun2013-11-25-308/+175
| | | | | | | Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-25-408/+416
| | | | | | | Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
* p1010rdb: enable mtdparts for NANDZhao Qiang2013-11-25-0/+7
| | | | | | | | The default partition table matches the .dts files for these boards in Linux. This allows these partitions to be used by name with U-Boot's "nand" command. Signed-off-by: Zhao Qiang <B45475@freescale.com>
* mpc85xx: Fix the offset of register address errorTang Yuantian2013-11-25-2/+2
| | | | | | | | | The offset of register address within GPIO module is just CONFIG_SYS_MPC85xx_GPIO_ADDR. So, fix it. The following platforms are confirmed: MPC8572, P1023, P1020, P1022, P2020, P4080, P5020, P5040, T4240, B4860. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
* powerpc/t1040qds: Correct Maintainer name in boards.cfgPriyanka Jain2013-11-25-1/+1
| | | | | | Update T1040QDS naem to Poonam Aggrwal. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
* phy: introduce structure fixed-linkShaohui Xie2013-11-22-0/+8
| | | | | | | fixed-link is used in kernel for PHY-less MAC, so introduce this structure that U-boot can use it to fixup dtb dynamically. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* powerpc/p4080: enable support for PCIe SATAShaohui Xie2013-11-22-0/+6
| | | | | Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2013-11-17-3/+3
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| * malta: use unmapped flash base addressGabor Juhos2013-11-15-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The physical base address of the NOR flash is 0x1e000000 on the Malta boards. The hardware also maps the first 4MiB of the flash into the 0x1fc00000-0x1fffffff range. Currently, U-Boot uses the mapped address to access the flash, which does not work in recent qemu versions. Since commit a427338b222b43197c2776cbc996936df0302f51 (mips_malta: correct reading MIPS revision at 0x1fc00010) writing to the mapped address space causes a CPU exception. Due to the exception, U-Boot hangs during boot when it tries to detect the CFI flash chip. Use the correct physical address for the MALTA_FLASH_BASE constant to fix the problem. In order to avoid relocation problems, also update the CONFIG_SYS_{TEXT,MONITOR}_BASE constants. The change makes it possible to start U-Boot on a Malta board emulated with Qemu 1.6.1 and 1.7.0-rc0. It also works on older versions (tested with 1.1.1, 1.2.2, 1.4.2, 1.5.3). Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
* | fs: descend into sub directories when it is necessaryMasahiro Yamada2013-11-17-25/+23
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Makefile: move fs/fat/ entry to drivers/MakefileMasahiro Yamada2013-11-17-3/+7
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | arm: rmobile: Do not create a symbolic link to sh timerMasahiro Yamada2013-11-17-7/+1
| | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* | powerpc: mpc824x: Do not create a symbolic link to bedbug_603e.cMasahiro Yamada2013-11-17-7/+1
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | powerpc: mpc83xx: Do not create a symbolic link to ddr-gen2.cMasahiro Yamada2013-11-17-6/+1
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | powerpc: mpc83xx: delete unused rulesMasahiro Yamada2013-11-17-6/+0
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Makefile: delete unused linesMasahiro Yamada2013-11-17-6/+0
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | tools: Makefile: delete redundant linesMasahiro Yamada2013-11-17-2/+0
| | | | | | | | | | | | HOSTOS is defined and exported at the top Makefile. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | config.mk: delete unnecessary linesMasahiro Yamada2013-11-17-6/+0
| | | | | | | | | | | | | | SPL_BIN is already defined in spl/Makefile and it is used only in spl/Makefile. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Makefile: refactor a littleMasahiro Yamada2013-11-17-5/+2
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Makefile: rename all libraries to built-in.oMasahiro Yamada2013-11-17-181/+182
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | drivers/net/npe: descend only when CONFIG_IXP4XX_NPE=yMasahiro Yamada2013-11-17-4/+2
| | | | | | | | | | | | | | CONFIG_IXP4XX_NPE is defined only for CPU ixp. It is not necessary to filter by CPU ixp. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | drivers/net/fm: descend only when CONFIG_FMAN_ENET=yMasahiro Yamada2013-11-17-5/+1
| | | | | | | | | | | | | | CONFIG_FMAN_ENET is defined only for CPU mpc85xx. We do not need to filter by CPU mpc85xx. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | drivers/qe: move the entry to drivers/MakefileMasahiro Yamada2013-11-17-6/+3
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | powerpc: move mpc8xxx entry under arch/powerpc/cpu/Masahiro Yamada2013-11-17-20/+11
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Makefile: merge $(LIBBOARD) into $(LIBS)Masahiro Yamada2013-11-17-9/+4
| | | | | | | | | | | | We do not need to handle $(LIBBOARD) and $(LIBS) separately. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Makefile: make directories by Makefile.buildMasahiro Yamada2013-11-17-247/+7
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | drivers: tpm: clean up unused codeMasahiro Yamada2013-11-17-187/+0
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | lib: descend into sub directories only when it is necessaryMasahiro Yamada2013-11-17-10/+8
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | drivers: descend into sub directories only when it is necessaryMasahiro Yamada2013-11-17-5/+3
| | | | | | | | | | | | | | - Descend into drivers/fpga/ only when CONFIG_FPGA=y - Descend into drivers/bios_emulator only when CONFIG_BIOSEMU=y Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Makefile: specifiy an explicite object name rather than $(BOARD).oMasahiro Yamada2013-11-17-3/+3
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Makefile: abolish COBJS, SOBJS, etc.Masahiro Yamada2013-11-17-8/+4
| | | | | | | | | | | | | | | | The support for COBJS, COBJS-y, SOBJS, SOBJS-y, GLCOBJS, GLSOBJS from scripts/Makefile.build. Going forward we need to use Kbuild style consistently. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | board: Do not add -DCONFIG_SYS_TEXT_BASE in board config.mkMasahiro Yamada2013-11-17-55/+5
| | | | | | | | | | | | | | Board config.mk do not need to add -DCONFIG_SYS_TEXT_BASE to CPPFLAGS because the top level config.mk does instead. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | examples: remove the remainders of dead boardMasahiro Yamada2013-11-15-217/+1
| | | | | | | | | | | | | | | | | | Commit 309a292e deleted OXC board, but missed to remove the standalone example specific to OXC board. eepro100_eeprom.c has been an orphan file for a long term. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | cosmetic: README.scrapyard: Add eNET boardMasahiro Yamada2013-11-15-0/+1
| | | | | | | | | | | | | | | | | | | | | | Commit 7e8c53d7 removed eNET board but missed to add eNET to README.scrapyard. This commit adds it for the record. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Cc: Graeme Russ <graeme.russ@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | nios2: remove unnecessary header include pathMasahiro Yamada2013-11-15-6/+0
| | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Thomas Chou <thomas@wytron.com.tw>
* | board: cogent: include header files in a more natural wayMasahiro Yamada2013-11-15-21/+9
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | configs: clean up unused macro CONFIG_L2_OFFMasahiro Yamada2013-11-15-11/+0
| | | | | | | | | | | | | | | | Since commit c2dd0d455 and 45bf05854 introduced the new cache maintainance framework to ARM, CONFIG_L2_OFF has not been used at all. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | TI:omap: Update u-boot-spl.lds for i2c multibus/multiadapter updateTom Rini2013-11-15-1/+2
| | | | | | | | | | | | | | | | | | | | | | In 6789e84 we update u-boot-spl.lds for OMAP to ensure we include adapter information, as we use i2c during SPL. However, the regex used also means we included commands that may have been built. On omap5_uevm this leads to a failure as we include the command from the do_tca642x command, and fail to link. The fix is to restrict our regex to only the i2c list parts. Signed-off-by: Tom Rini <trini@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-11-14-213/+2353
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| * | powerpc/85xx: fix broken cpu "clock-frequency" propertyLaurentiu TUDOR2013-11-13-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When indexing freqProcessor[] we use the first value in the cpu's "reg" property, which on new e6500 cores IDs the threads. But freqProcessor[] should be indexed with a core index so, when fixing "the clock-frequency" cpu node property, access the freqProcessor[] with the core index derived from the "reg' property. If we don't do this, last half of the "cpu" nodes will have broken "clock-frequency" values. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: York Sun <yorksun@freescale.com>
| * | powerpc/t4240: fix per pci endpoint liodn offsetsLaurentiu TUDOR2013-11-13-5/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the code that builds the pci endpoint liodn offset list so that it doesn't overlap with other liodns and doesn't generate negative offsets like: fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf 0xffffffd1 0xffffffd3 0xffffffd5 0xffffffd7 0xffffffd9 0xffffffdb>; The update consists in adding a parameter to the function that builds the list to specify the base liodn. On PCI v2.4 use the old base = 256 and, on PCI 3.0 where some of the PCIE liodns are larger than 256, use a base = 1024. The version check is based on the PCI controller's version register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com>
| * | powerpc/t4240: set pcie liodn in the correct registerLaurentiu TUDOR2013-11-13-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The liodn for the T4240's PCIE controller is no longer set through a register in the guts register block but with one in the PCIE register block itself. Use the already existing SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com>
| * | powerpc/83xx: Define USB1 and USB2 base addr for MPC834xramneek mehresh2013-11-13-0/+5
| | | | | | | | | | | | | | | | | | | | | Define base addresse for both MPH(USB1) and DR(USB2) controllers for MPC834x socs Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
generated by cgit v1.1 at 2024-12-27 17:05:24 +0000