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* mx23evk: Turn on cachesFabio Estevam2013-02-12-2/+0
| | | | | | It is safe to turn on data and instruction caches for mx23. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx23evk: Remove CONFIG_SYS_BAUDRATE_TABLEFabio Estevam2013-02-12-1/+0
| | | | | | | | The baudrate is already defined by CONFIG_BAUDRATE and there is no need to keep CONFIG_SYS_BAUDRATE_TABLE. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* build: imx: Fix 'u-boot.imx' build without full OBJTREE referenceOtavio Salvador2013-02-12-4/+4
| | | | | | | | | | | | | | | | | | | When calling 'make u-boot.imx' the build were failing as it were expecting the full path for the file; this regression has been included by commit 71a988a (imximage.cfg: run files through C preprocessor). The direct references for u-boot.imx were replaced by $(obj) as config.mk handles the proper setting of it making it set to $(OBJTREE) when required. The build has been test using: - ./MAKEALL -s mx5 -s mx6 - make u-boot.imx - make O=/tmp/build Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mx6: Disable Power Down Bit of watchdogFabio Estevam2013-02-12-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted and it is not able to reach the Linux prompt. Comparing the watchdog behaviour on a revB versus revC board: - On a mx6qsabresd revB: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: WDOG ... - On a mx6qsabresd revC: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: POR So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR. Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and is also safe for all mx6 boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
* imx: mx6q DDR3 init: Benefit from available CL = 7Benoît Thébaudeau2013-02-12-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the users of mx6q_4x_mt41j128.cfg (DDR3-1333H Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and DDR3-1600K Micron MT41K128M16JT-125:K for i.MX6 SABRE SD) support the optional down binning to DDR3-1066F (CL = 7, CWL = 6), which is possible at 532 MHz, so use it. In these conditions: tRCD(min) = 13.125 ns tRP(min) = 13.125 ns tRC(min) = max(tRAS(min, DDR3-1333H), tRAS(min, DDR3-1600K)) + tRP(min) tRAS(min, DDR3-1333H) = 36 ns tRAS(min, DDR3-1600K) = 35 ns MMDC1_MDCFG0.tCL should be set to 7 nCK, encoded as 0x4 in the bit-field MMDC1_MDCFG0[3:0]. MR0.CL should be set as in MMDC1_MDCFG0.tCL, i.e. to 7 nCK, which is encoded as 0x6 in MRS.LMR.MR0.{A6:A4, A2} and MMDC1_MDSCR[22:20, 18]. MMDC1_MDCFG1.tCWL should be set to 6 nCK, encoded as 0x4 in the bit-field MMDC1_MDCFG1[2:0]. MMDC1_MDCFG1.tRCD should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded as 0x6 in the bit-field MMDC1_MDCFG1[31:29]. MMDC1_MDCFG1.tRP should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded as 0x6 in the bit-field MMDC1_MDCFG1[28:26]. MMDC1_MDCFG1.tRC should be set to 49.125 ns, which is 27 nCK at 532 MHz, encoded as 0x1A in the bit-field MMDC1_MDCFG1[25:21]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* imx: mx6q DDR3 init: Fix MR0.PPDBenoît Thébaudeau2013-02-12-2/+2
| | | | | | | MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* imx: mx6q DDR3 init: Fix RST_to_CKEBenoît Thébaudeau2013-02-12-1/+1
| | | | | | | | MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded as 0x23 for the bit-field MMDC1_MDOR[5:0]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* imx: mx6q DDR3 init: Fix SDE_to_RSTBenoît Thébaudeau2013-02-12-1/+1
| | | | | | | | MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded as 0x10 for the bit-field MMDC1_MDOR[13:8]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* imx: mx6q DDR3 init: Fix tXPRBenoît Thébaudeau2013-02-12-1/+1
| | | | | | | | | | | | | | | | | MMDC1_MDOR.tXPR should be set as specified for the JEDEC DDR3 timing tXPR. For all DDR3 speed bins: tXPR(min) = max(5 nCK, tRFC(min) + 10 ns) tRFC(2 Gb) = 160 ns All the users of mx6q_4x_mt41j128.cfg have a 2-Gb density (Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and Micron MT41K128M16JT-125:K for i.MX6 SABRE SD). Hence, MMDC1_MDOR.tXPR should be set to max(5 nCK, 170 ns), which is 170 ns and 91 nCK at 532 MHz, encoded as 0x5A in the bit-field MMDC1_MDOR[23:16]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* imx: mx6q DDR3 init: Fix tMRDBenoît Thébaudeau2013-02-12-1/+1
| | | | | | | | | | | | | | MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3. For all DDR3 speed bins: tMRD(min) = 4 nCK tMOD(min) = max(12 nCK, 15 ns) Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
* mx23evk: Add initial board supportOtavio Salvador2013-01-28-0/+441
| | | | | | | | | | The following features are supported: * 128 MB DDR1 SDRAM * DUART * SD/MMC Card Socket Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx23_olinuxino: Add default environmentOtavio Salvador2013-01-28-7/+70
| | | | | | This adds a default environment with support for MMC booting. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: mmc: mx23_olinuxino: Add MMC supportMarek Vasut2013-01-28-1/+42
| | | | | | | | | Add support for the MMC attached to SSP1. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* mxs: mmc: Fix the MMC driver for MX23Marek Vasut2013-01-28-5/+22
| | | | | | | | | | The MX23 has different layout of DMA channels. Fix the MMC driver to support MX23. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* mxs: mmc: Allow overriding default card detect implementationMarek Vasut2013-01-28-7/+19
| | | | | | | | | | Some MXS based boards do not implement the card-detect signal. Allow user to specify alternate card-detect implementation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* mxs: mmc: Fix MMC reset on iMX23Otavio Salvador2013-01-28-5/+11
| | | | | | | | | | This does the same reset mask as done in v3.7 Linux kernel code. The block is properly configured for MMC operation that way. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* mxs: ssp: Add SSP registers map for MX23Marek Vasut2013-01-28-0/+36
| | | | | | | | | | The MX23 SSP register layout differs from MX28 in certain bits, adjust the register layout accordingly. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* mxs: dma: Fix APBH DMA driver for MX23Marek Vasut2013-01-28-2/+129
| | | | | | | | | | | The MX23 has less channels for the APBH DMA, sligtly different register layout and some bits in those registers are placed differently. Reflect this in the driver. This patch fixes MMC/DMA issue on MX23. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* mx6qsabrelite: search mii phy address 4-7Troy Kisky2013-01-28-3/+21
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* net: fec_mxc: get phydev before fec_probeTroy Kisky2013-01-28-43/+83
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* net: fec_mxc: only call phy_connect in fec_probeTroy Kisky2013-01-28-21/+12
| | | | | | | This allows us to create the phydev before calling fec_probe in later patch. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* net: fec_mxc: use fec_set_dev_name to set nameTroy Kisky2013-01-28-8/+8
| | | | | | | This allows us to create the phydev before calling fec_probe in later patch. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* phy: add phy_find_by_mask/phy_connect_devTroy Kisky2013-01-28-50/+81
| | | | | | | | | | | | It is useful to be able to try a range of possible phy addresses to connect. Also, an ethernet device is not required to use phy_find_by_mask leading to better separation of mii vs ethernet, as suggested by Andy Fleming. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* net: fec_mxc: have fecmxc_initialize call fecmxc_initialize_multiTroy Kisky2013-01-28-16/+8
| | | | | | | Having only one call to fec_probe will ease the changing of its parameters. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* net: fec_mxc: change fec_mii_setspeed parameterTroy Kisky2013-01-28-5/+5
| | | | | | | | | | | | | Only the hardware ethernet registers are needed for this function, so don't pass the more general structure. I'm trying to separate MII and fec. This also fixes MX28 fec_mii_setspeed use on secondary ethernet port This was found by inspection of the code and should be checked on real hardware. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* net: fec_mxc: delete CONFIG_FEC_MXC_MULTITroy Kisky2013-01-28-4/+1
| | | | | | | It is more logical to test for CONFIG_FEC_MXC_PHYADDR to determine whether to define the function fecmxc_initialize. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* doc/README.fec_mxc: add documentationTroy Kisky2013-01-28-0/+27
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mxs: Use __weak annotation to simplify codeFabio Estevam2013-01-28-7/+4
| | | | | | | Using the __weak annotation can make the code cleaner. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* tools: imximage: Let .name field be more genericFabio Estevam2013-01-28-1/+1
| | | | | | | Since this structure is not i.MX5x specific, remove the '5x' to make it more generic. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6qsabre_common: Let mmc partition be board specificFabio Estevam2013-01-28-1/+2
| | | | | | | | | | commit 49ea0ff5 (49ea0ff5) introduced CONFIG_SYS_MMC_ENV_PART into mx6qsabresd.h to store the mmc partition, but in order for it to have effect we should place it into 'mmcpart' variable. Also add CONFIG_SYS_MMC_ENV_PART into mx6qsabreauto.h. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6qsabreauto: enable USB host interfaceKnut Wohlrab2013-01-28-0/+11
| | | | | | The USB host interface is routed to plug USB1/J30 on the mother board. Signed-off-by: Knut Wohlrab <knut.wohlrab@de.bosch.com>
* mxs: Boost the memory power supplyMarek Vasut2013-01-28-3/+3
| | | | | | | | | | | The memory power supply on MX23 didn't pump out enough juice into the DRAM chip, thus caused occasional memory corruption. Fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* imximage.cfg: run files through C preprocessorTroy Kisky2013-01-22-703/+791
| | | | | | | | | | | | The '#' used as comments in the files cause the preprocessor trouble, so change to /* */. The mkimage command which uses this preprocessor output was moved to arch/arm/imx-common/Makefile .gitignore was updated to ignore .cfgtmp files. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mxs: Add MX23 quirks into the clock codeOtavio Salvador2013-01-21-11/+32
| | | | | | | | | | The MX23 has different handling of the SSP clock and GPMI NAND clock sources, add necessary quirks into the clock code to properly handle these. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* woodburn: Set Write Protection GPIO as inputFabio Estevam2013-01-21-1/+2
| | | | | | Set Write Protection GPIO as input. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mxs: Add MX23 olinuxino board supportMarek Vasut2013-01-21-0/+325
| | | | | | | | | This patch adds support for MX23-based Olinuxino board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* mxs: Linux uses ttyAMA0 as DUARTMarek Vasut2013-01-21-1/+1
| | | | | | | Replace use of ttyAM0 with ttyAMA0 as default serial console. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* mxs: Fix the memory init for MX23Otavio Salvador2013-01-21-15/+78
| | | | | | | | | | The memory init is slightly different on MX23, thus split the memory init for mx23 and mx28 into different functions. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* mxs: Add function to ungate the power block on MX23Marek Vasut2013-01-21-0/+12
| | | | | | | | | | The power block on MX23 must first be ungated before it can be operated. Add function to MXS power init that ungates it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* mmc: Limit the number of used SSP ports on MX23Marek Vasut2013-01-21-1/+11
| | | | | | | | | | The MX23 can only use two SSP ports. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* mx23: config: Enable mxsboot tool for i.MX23 based boardsOtavio Salvador2013-01-21-0/+2
| | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* mx23: config: Enable building of u-boot.sb binaryOtavio Salvador2013-01-21-0/+19
| | | | | | | | | For i.MX23 we need to pass imx23 as elftosb param. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* mx23: SPL: Initialize DDR at 133MHzOtavio Salvador2013-01-21-0/+20
| | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* mx23: SPL: Add boot mode supportOtavio Salvador2013-01-21-0/+25
| | | | | | | | | This adds the boot mode support for i.MX23 processors. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* mx23: Add boot mode descriptionOtavio Salvador2013-01-21-0/+12
| | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* mx23: Add support on print_cpuinfo()Otavio Salvador2013-01-21-1/+19
| | | | | | | | | Add information to identify i.MX23 chips and its known revisions. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* mx23: ssp: Fix ssp-regs.h for MX23Marek Vasut2013-01-21-0/+2
| | | | | | | | | Disable SSP2 and SSP3 ports on MX23. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* mx23: Add POWER and CLKCTRL register definitionsMarek Vasut2013-01-21-1/+585
| | | | | | | | | | | Add register definitions for the i.MX23 power control block and clock control block. These are essential for the basic bootstrap of the i.MX23. Also, properly include them in imx-regs.h . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* mx23: Add iomux-mx23.hOtavio Salvador2013-01-21-0/+361
| | | | | | | | | This has been copied from Linux source at revision 786f02b719f. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* mx23: Add register base addressesOtavio Salvador2013-01-21-5/+51
| | | | | | | | | | | This adds the base addresses of i.MX23 and easy the detection of wrong order in board setup, in case no SoC has been set, an error is raised during build. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
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