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* arm/km: replace suenx targets with km_kirkwoodHolger Brunck2011-07-04-60/+25
| | | | | | | | | | | | | | suen3 and suen8 were in first HW version quite different, but now they are from a u-boot point of view similar. So these two boards can use the same header file. Other keymile boards differ only in the usage of the PCI interface. Therefore a target km_kirkwood_pci was introduced. All targets use the same header file. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Heiko Schocher <hs@denx.de>
* arm/km: ethernet support for mgcoge3unValentin Longchamp2011-07-04-1/+38
| | | | | | | | | | The phy is also configured with "RGMII clock transitions when data stable" and "Class A driver for the direct backplane connection". Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Heiko Schocher <hs@denx.de>
* arm/km: use board KM_ENV_BUS for CONFIG_I2C_ENV_EEPROM_BUSValentin Longchamp2011-07-04-1/+1
| | | | | | | | | | | This is defined for all km_kirkwood boards and was not used up to now. This value was the same for all boards but it could be changed for some boards (and thus needs to be defined for every board). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Heiko Schocher <hs@denx.de>
* arm/km: remove unneeded defineHolger Brunck2011-07-04-2/+0
| | | | | | | | | | | CONFIG_ENV_SIZE for NAND was later in this file overwritten because we have the environment in i2c eeprom, so remove this define. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Heiko Schocher <hs@denx.de>
* arm/km: fix u-boot.kwb build breakageHolger Brunck2011-07-04-22/+7
| | | | | | | | | | | | | | | | | | | commit 010a958b (arm/km: remove CONFIG_SYS_KWD_CONFIG from keymile-common.h) breaks building keymile arm targets, when u-boot.kwb tries to generate the binary with mkimage. A simple make <board> or MAKEALL succeeded because it don't try to build the kirwood binary at the end. Due this commit we use the CONFIG_SYS_KWD_CONFIG from the arch-kirkwood/config.h and it was removed from the board config. But it was forgotten to include the header. Now the header is included in km_arm.h. Some other defines were obsolete due to this include, these are also removed in this commit. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Heiko Schocher <hs@denx.de>
* arm/kirkwood: if CONFIG_SOFT_I2C is set don't set CONFIG_I2C_MVTWSIHolger Brunck2011-07-04-0/+2
| | | | | | | | | | | Some boards e.g. keymile arm boards have CONFIG_CMD_I2C switched on but they use soft i2c on kirkwood. So don't switch CONFIG_I2C_MVTWSI on in this case. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Heiko Schocher <hs@denx.de>
* Fix compiler error for cpu at91sam9, if lowlevel init is enabledJens Scharsig2011-07-04-1/+1
| | | | | | | * Fix compiler error for cpu at91sam9, if lowlevel init is enabled * use correct ATMEL_ name scheme to define ATMEL_BASE_SDRAMC Signed-off-by: Jens Scharsig
* atstk100x: switch to common cfi driverAndreas Bießmann2011-07-04-261/+8
| | | | | | | | | This patch removes the board implemenatation for flash driver which can now safely switched to the common cfi driver. Compile tested for all atstk100x boards, runtime tested on atstk1002. Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
* driver/serial: delete at91rm9200_usartAndreas Bießmann2011-07-04-127/+0
| | | | | | The at91rm9200_usart driver could be fully replaced by atmel_usart driver. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* cpuat91: use atmel_usartAndreas Bießmann2011-07-04-3/+12
| | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Eric Bénard <eric@eukrea.com>
* eb_cpux9k2: use atmel_usartAndreas Bießmann2011-07-04-2/+11
| | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> CC: Jens Scharsig <js_at_ng@scharsoft.de> Acked-by: Jens Scharsig<js_at_ng@scharsoft.de> Tested-by: Jens Scharsig<js_at_ng@scharsoft.de> (for eb_cpux9k2 board)
* at91rm9200ek: use atmel_usartAndreas Bießmann2011-07-04-2/+12
| | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm920t/at91: add at91rm9200_devices.cAndreas Bießmann2011-07-04-2/+93
| | | | | | | This is a copy of arm926ejs/at91 api for perpherial initialisation. At the moment we just need the usart part of the api. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm920t/at91: use new clock.c featuresAndreas Bießmann2011-07-04-4/+53
| | | | | | | | | This patch enables the new clock features from arm920t/at91/clock.c. This is an required step to get at91rm9200_usart replaced by atmel_usart driver. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Jens Scharsig <js_at_ng@scharsoft.de> Cc: Eric Bénard <eric@eukrea.com>
* arm920t/at91: add clock.cAndreas Bießmann2011-07-04-40/+198
| | | | | | | This patch adds an copy of arm926ejs/at91/clock.c to arm920t/at91. The arm926ejs specialities are removed from arm920t version and vice versa. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* at91rm9200.h: fix ATMEL_PMX_AA_TXD2Andreas Bießmann2011-07-04-1/+1
| | | | | | | | | This patch sets the ATMEL_PMX_AA_TXD2 to the correct value. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> CC: Jens Scharsig <js_at_ng@scharsoft.de> CC: eric@eukrea.com Acked-by: Eric Bénard <eric@eukrea.com>
* vision2: Fix build due to WEIM registers name changeFabio Estevam2011-07-04-5/+5
| | | | | | | | | commit 0015de1a (MX5: Make the weim structure complete) fixed the name for the WEIM registers in order to match with the MX51/MX53 manuals. Fix the WEIM register for vision2 board so that it can build again. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* MX53: Add initial support for MX53ARDFabio Estevam2011-07-04-0/+650
| | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* MX5: Introduce a function for setting the chip select sizeFabio Estevam2011-07-04-1/+36
| | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* MX5: Add iomux structureFabio Estevam2011-07-04-0/+23
| | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* MX5: Make the weim structure completeFabio Estevam2011-07-04-6/+125
| | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* arm: Update jadecpu boardMatthias Weisser2011-07-04-14/+16
| | | | | | | | Enable dcache and arch memset/memcpy for speed reasons Remove of config.mk and some environment overwrites Some generic cleanup Signed-off-by: Matthias Weisser <weisserm@arcor.de>
* arm: omap2: apollon: fix broken buildIgor Grinberg2011-07-04-0/+4
| | | | | | | | Define CONFIG_SYS_SDRAM_BASE to physical SDRAM address and CONFIG_SYS_INIT_SP_ADDR to physical SRAM address Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Cc: Kyungmin Park <kyungmin.park@samsung.com>
* OMAP[34]: fix broken timerJohn Rigby2011-07-04-3/+4
| | | | | | | | | | | | | | | | | | | | As implemented now the timer used to implement __udelay counts to 0xffffffff and then gets stuck there because the the programmed reload value is 0xffffffff. This value is not only wrong but illegal according to the reference manual. One can reproduce the bug by leaving a board at the u-boot prompt for sometime then issuing a sleep command. The sleep will hang forever. The timer is a count up timer that reloads as it rolls over from 0xffffffff so the correct load value is 0. Change TIMER_LOAD_VAL from 0xffffffff to 0 and introduce a new constant called TIMER_OVERFLOW_VAL set to 0xffffffff. Signed-off-by: John Rigby <john.rigby@linaro.org> Tested-by: Igor Grinberg <grinberg@compulab.co.il>
* arm: Tegra2: GPIO: enable GPIO for Tegra2 boardsTom Warren2011-07-04-0/+2
| | | | Signed-off-by: Tom Warren <twarren@nvidia.com>
* GPIO: Tegra2: add GPIO driver for Tegra2Tom Warren2011-07-04-10/+534
| | | | Signed-off-by: Tom Warren <twarren@nvidia.com>
* VCMA9: various cleanups/code style fixesDavid Müller (ELSOFT AG)2011-07-04-591/+634
| | | | Signed-off-by: David Müller <d.mueller@elsoft.ch>
* VCMA9: use CFI driver (and remove the old one)David Müller (ELSOFT AG)2011-07-04-452/+22
| | | | Signed-off-by: David Müller <d.mueller@elsoft.ch>
* VCMA9: remove unneeded config.mkDavid Müller (ELSOFT AG)2011-07-04-24/+2
| | | | Signed-off-by: David Müller <d.mueller@elsoft.ch>
* armv7: adapt s5pc1xx to the new cache maintenance frameworkAneesh V2011-07-04-85/+6
| | | | | | adapt s5pc1xx to the new layered cache maintenance framework Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: adapt omap3 to the new cache maintenance frameworkAneesh V2011-07-04-286/+176
| | | | | | adapt omap3 to the new layered cache maintenance framework Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: adapt omap4 to the new cache maintenance frameworkAneesh V2011-07-04-7/+32
| | | | | | adapt omap4 to the new layered cache maintenance framework Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: add PL310 support to u-bootAneesh V2011-07-04-0/+195
| | | | | | | | | | | | | PL310 is the L2$ controller from ARM used in many SoCs including the Cortex-A9 based OMAP4430 Add support for some of the key PL310 operations - Invalidate all - Invalidate range - Flush(clean & invalidate) all - Flush range Signed-off-by: Aneesh V <aneesh@ti.com>
* arm: minor fixes for cache and mmu handlingAneesh V2011-07-04-2/+18
| | | | | | | | | | | 1. make sure that page table setup is not done multiple times 2. flush_dcache_all() is more appropriate while disabling cache than a range flush on the entire memory(flush_cache()) Provide a default implementation for flush_dcache_all() for backward compatibility and to avoid build issues. Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: integrate cache maintenance supportAneesh V2011-07-04-32/+51
| | | | | | | | | | - Enable I-cache on bootup - Enable MMU and D-cache immediately after relocation - Do necessary initialization before enabling d-cache and MMU - Changes to cleanup_before_linux() - Make changes according to the new framework Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: rename cache related CONFIG flagsAneesh V2011-07-04-45/+42
| | | | | | | | | | | | | | | | Replace the cache related CONFIG flags with more meaningful names. Following are the changes: CONFIG_L2_OFF -> CONFIG_SYS_L2CACHE_OFF CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF Signed-off-by: Aneesh V <aneesh@ti.com> V2: * Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE V4: * Changed all three flags to the final names suggested as above and accordingly changed the commit message
* armv7: cache maintenance operations for armv7Aneesh V2011-07-04-2/+527
| | | | | | | | | | | | | | | | | | | | | | | | | | - Add a framework for layered cache maintenance - separate out SOC specific outer cache maintenance from maintenance of caches known to CPU - Add generic ARMv7 cache maintenance operations that affect all caches known to ARMv7 CPUs. For instance in Cortex-A8 these opertions will affect both L1 and L2 caches. In Cortex-A9 these will affect only L1 cache - D-cache operations supported: - Invalidate entire D-cache - Invalidate D-cache range - Flush(clean & invalidate) entire D-cache - Flush D-cache range - I-cache operations supported: - Invalidate entire I-cache - Add maintenance functions for TLB, branch predictor array etc. - Enable -march=armv7-a so that armv7 assembly instructions can be used Signed-off-by: Aneesh V <aneesh@ti.com>
* arm: make default implementation of cache_flush() weakly linkedAneesh V2011-07-04-1/+3
| | | | | | | make default implementation of cache_flush() weakly linked so that sub-architectures can override it Signed-off-by: Aneesh V <aneesh@ti.com>
* Makefile: need to remove generated u-boot-nand_spl.ldsKumar Gala2011-07-01-1/+1
| | | | | | | | On MPC85xx based NAND_SPL builds we generate a u-boot-nand_spl.lds based on output from preprocessor. We where never removed it. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: Add 16bit NAND support for the NDFCAlex Waterman2011-07-01-7/+45
| | | | | | | | | | | | | | | | | | | This patch adds support for 16 bit NAND devices attached to the NDFC on ppc4xx processors. Two config entries were added: CONFIG_SYS_NDFC_16 - Setting this tells the NDFC that a 16 bit device is attached. CONFIG_SYS_NDFC_EBC0_CFG - This is for the External Bus Controller configuration register. Also, a new ndfc_read_byte() function was added which does not first convert the data to little endian. The NAND SPL was also modified to do 16bit bad block testing when a 16 bit chip is being used. Signed-off-by: Alex Waterman <awaterman@dawning.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* cmd_nand: add nand write.trimffs commandBen Gardiner2011-07-01-0/+26
| | | | | | | | | | | | | | | | | | Add another nand write. variant, trimffs. This command will request of nand_write_skip_bad() that all trailing all-0xff pages will be dropped from eraseblocks when they are written to flash as-per the reccommended behaviour of the UBI FAQ [1]. The function that implements this timming is the drop_ffs() function by Artem Bityutskiy, ported from the mtd-utils tree. [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> CC: Artem Bityutskiy <dedekind1@gmail.com> CC: Detlev Zundel <dzu@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* nand_util: drop trailing all-0xff pages if requestedBen Gardiner2011-07-01-3/+38
| | | | | | | | | | | | | | | | | | | | Add a flag to nand_read_skip_bad() such that if true, any trailing pages in an eraseblock whose contents are entirely 0xff will be dropped. The implementation is via a new drop_ffs() function which is based on the function of the same name from the ubiformat utility by Artem Bityutskiy. This is as-per the reccomendations of the UBI FAQ [1] [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> CC: Artem Bityutskiy <dedekind1@gmail.com> Acked-by: Detlev Zundel <dzu@denx.de> CC: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* nand_util: treat WITH_YAFFS_OOB as a modeBen Gardiner2011-07-01-1/+6
| | | | | | | | | | | | | When specified in the flags argument of nand_write, WITH_YAFFS_OOB causes an operation which is mutually exclusive with the 'usual' way of writing. Add a check that client code does not specify WITH_YAFFS_OOB along with any other flags and add a comment indicating that the WITH_YAFFS_OOB flag should not be mixed with other flags. Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> CC: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* nand_util: convert nand_write_skip_bad() to flagsBen Gardiner2011-07-01-6/+10
| | | | | | | | | | | | | | | | | | | | | | In a future commit the behaviour of nand_write_skip_bad() will be further extended. Convert the only flag currently passed to the nand_write_ skip_bad() function to a bitfield of only one allocated member. This should avoid an explosion of int's at the end of the parameter list or the ambiguous calls like nand_write_skip_bad(info, offset, len, buf, 0, 1, 1); nand_write_skip_bad(info, offset, len, buf, 0, 1, 0); Instead there will be: nand_write_skip_bad(info, offset, len, buf, WITH_YAFFS_OOB | WITH_OTHER); Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> Acked-by: Detlev Zundel <dzu@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* nand_base: trivial: fix comment read/write commentBen Gardiner2011-07-01-1/+1
| | | | | | | | Replace an incorrect 'read' with 'write' in a comment. Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> Acked-by: Detlev Zundel <dzu@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Merge branch 'next' of git://git.denx.de/u-boot-niosWolfgang Denk2011-07-01-17/+2
|\ | | | | | | | | * 'next' of git://git.denx.de/u-boot-nios: nios2: move generic config to boards.cfg
| * nios2: move generic config to boards.cfgMike Frysinger2011-06-30-17/+2
| | | | | | | | | | | | | | | | | | I can't build test this, but just looking at the config files written and it seems OK ... Tested-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | cfi_flash: reverse geometry for newer STM partsMike Frysinger2011-06-29-0/+4
|/ | | | | | | | | | | | | | | | | | | | | | | | | | For newer STM parts where CFI >= 1.1, there is a byte in the extended structure that declares the flash layout type (just like the AMD parts), so key off of that to find out when we need to reverse the geometry. This can be seen with M29W640 parts where U-Boot does: Bank # 1: CFI conformant FLASH (16 x 16) Size: 8 MB in 135 Sectors AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x22ED Erase timeout: 8192 ms, write timeout: 1 ms Buffer write timeout: 1 ms, buffer size: 16 bytes Sector Start Addresses: 20000000 RO 20002000 RO 20004000 RO 20006000 RO 20008000 RO 2000A000 RO 2000C000 RO 2000E000 RO 20010000 RO 20020000 RO ... But Linux does: physmap platform flash device: 00800000 at 20000000 physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank. Manufacturer ID 0x000020 Chip ID 0x0022ed physmap-flash.0: Swapping erase regions for top-boot CFI table. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Stefan Roese <sr@denx.de>
* Prepare v2011.06v2011.06Wolfgang Denk2011-06-27-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Minor coding style fixes.Wolfgang Denk2011-06-27-8/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
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