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* cm-t35: reduce the environment sizeIgor Grinberg2012-07-07-2/+1
| | | | | | | | Reduce the environment size (128KB => 16KB) to improve the environment operations time (e.g. reading, ecc calculation). Also, remove the unused CONFIG_SYS_ENV_SECT_SIZE. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* ARM: OMAP4: Correct the lpddr2 io settings register value.SRICHARAN R2012-07-07-1/+1
| | | | | | | | | | To meet certain timing requirements on the lpddr2 cmd and data phy interfaces ,lpddr iopads have to be configured as differential buffers and a Vref has to be internally generated and provided to these buffers. Correcting the above settings here. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* OMAP5: Change voltages for omap5432Lokesh Vutla2012-07-07-10/+31
| | | | | | Change voltages for OMAP5432 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: DPLL core lock for OMAP5432Lokesh Vutla2012-07-07-6/+25
| | | | | | | No need to Unlock DPLL initially. DDR3 can work at normal OPP from initialozation Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: EMIF: Add support for DDR3 deviceLokesh Vutla2012-07-07-4/+166
| | | | | | | | | In OMAP5432 EMIF controlller supports DDR3 device. This patch adds support for ddr3 device intialization and configuration. Initialization sequence is done as specified in JEDEC specs. This also adds support for ddr3 leveling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: ADD precalculated timings for ddr3Lokesh Vutla2012-07-07-1/+55
| | | | | | | Adding precalculated timings for ddr3 with 1cs adding required registers for ddr3 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: Configure the io settings for omap5432 uevm boardLokesh Vutla2012-07-07-20/+93
| | | | | | This patch adds the IO settings required for OMAP5432 uevm's DDR3 pads Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: ADD chip detection for OMAP5432 SOCLokesh Vutla2012-07-07-2/+12
| | | | | | This patch adds chip detection for OMAP5432 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: Adding correct Control id code for OMAP5430Lokesh Vutla2012-07-07-1/+1
| | | | | | | Control id code for omap5430 ES1.0 is hard coded with a wrong value. This patch corrects the value Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* omap3evm: Add CONFIG_CMD_ASKENVTom Rini2012-07-07-0/+2
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* omap3_beagle: Add CONFIG_CMD_ASKENVTom Rini2012-07-07-0/+2
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* omap3evm: Set BOOTDELAY to 3Tom Rini2012-07-07-1/+1
| | | | | | | We reduce the bootdelay from 10s to 3s to give users a short but usable window to interrupt the boot process if needed. Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3 Beagle: Set BOOTDELAY to 3Tom Rini2012-07-07-1/+1
| | | | | | | We change the bootdelay to give users a little bit longer to break in if needed. Signed-off-by: Tom Rini <trini@ti.com>
* omap24xx_i2c: Add AM33XX supportTom Rini2012-07-07-3/+3
| | | | | | | | | The same places that check for CONFIG_OMAP44XX need to check for CONFIG_AM33XX as we share the same i2c block. Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
* am33xx: Fix i2c sampling rate typoTom Rini2012-07-07-1/+1
| | | | | Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
* am33xx: Fill in more cm_wkuppll / cm_perpllTom Rini2012-07-07-10/+30
| | | | | Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
* am335x: Correct i2c sysc offsetTom Rini2012-07-07-3/+3
| | | | | Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
* Revert "I2C: OMAP: detect more devices when probing an i2c bus"Tom Rini2012-07-07-11/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 0e57968a215d1b9d271f3fa5bebeddeaea0c8075. The short version of the original commit is that some i2c devices cannot be probed via read as they NAK the first cycle, so try and probe via a write that we abort before it writes to the device. This however is not allowed by the TRM for any of these parts. The section on I2C_CON (table 17-35 I2C_CON for am/dm37x for example) says you must not change the register while STT has been set. On these parts, the unpredictable behavior that the chip exhibits is not problematic. On OMAP4 however it results in the chip being in a bad state: Panda # i2c probe Valid chip addresses: 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Panda # i2c md 50 0 timed out in wait_for_pin: I2C_STAT=0 I2C read: I/O error Error reading the chip. We must revert the original behavior to bring probe back into line with the TRM. Cc: Nick Thompson <nick.thompson@ge.com> Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
* DaVinci: fix ddr2 vtp i/o calibrationTroy Kisky2012-07-07-4/+3
| | | | | | | | | | | | | | | | | | | | | Previously, only the low 5 bits (NCH) were being transfered from DDRVTPR to DDRVTPIOCR, the bits 5-9 where zeroed. VTP_RECAL should be bit 15, not 18. The only mainline board affected by this change is davinci_sonata. The other Davinci boards define CONFIG_SKIP_LOWLEVEL_INIT. However, if the program that loads u-boot on these boards copied the code from u-boot, they will need fixed as well. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Please get tested by acks before applying, where tested by means an overnight memory test. Thanks Troy
* ARM: OMAP5: Correct the DRAM_ADDR_SPACE_END macro.SRICHARAN R2012-07-07-1/+1
| | | | | | | OMAP5 evm board has 2GB of memory. So correct the macro to take in to account of the full dram size. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP5: Align memory used for testing to the power of 2SRICHARAN R2012-07-07-0/+3
| | | | | | | | | | | | get_ram_size checks the given memory range for valid ram, but expects the size of memory to be aligned to the power of 2. In case of OMAP5 evm board the memory available is 2GB - 16MB(used for TRAP section) = 2032MB. So always ensure that the size of memory used for testing is aligned to the power of 2. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP5: dmm: Create a tiler trap section.SRICHARAN R2012-07-07-3/+3
| | | | | | | | | | | | | | | | | The unmapped entries in tiler space are set with values 0xFF. So creating a DMM section of size 16MB at 0xFF000000 with ADDRSPACE set to 0x2. This way all the unmapped entry accesses to tiler will be trapped by the EMIF and a error response is sent to the L3 interconnect. L3 errors are inturn reported to MPU. Note that here the tiler trap section is overlapping with the actual ddr physical space and we lose 16MB out of the total 2GB. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP4+: dmm: Take care of overlapping dmm and trap sections.SRICHARAN R2012-07-07-2/+18
| | | | | | | | | | | | | The DMM sections can be overlapping with each other, with sections 3 to 0 having the highest to lowest priority in that order. There could also be a section that is used trap the unmapped Tiler entries and this trap section could be overlapping with the actual sdram area. So take care of the above scenarios while calculating the size of the actual ram. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* arm,davinci: update for enbw_cmc boardHeiko Schocher2012-07-07-28/+364
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - change gpio pin settings: - gpio pin 6[13] (PLC reset) default value low - gpio pin 6[0] (TPM reset) default value low - 4 new GPIO pins pin i/o name - 3[9] input Board Type - 2[7] input HW-ID0 - 2[6] input HW-ID1 - 2[3] input HW-ID2 - read board type and hw id from gpio pins on the enbw_cmc board, and use board type for setting up different gpio pin settings. - do not pass "davinci_mmc.use_dma=0" to linux, as MMC now works with DMA. - update logbuf support: store post word in RTC scratch register - add support for configuring KSZ8864RMN switch through a config file on u-boot startup. For more infos see: doc/README.switch_config Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tom Rini <tom.rini@gmail.com> Cc: Christian Riesch <christian.riesch@omicron.at> Cc: Sandeep Paulraj <s-paulraj@ti.com>
* am33xx: Do not call init_timer twiceTom Rini2012-07-07-28/+17
| | | | | | | We do not need to call init_timer both in SPL and U-Boot itself, just SPL needs to initialize the timer. Signed-off-by: Tom Rini <trini@ti.com>
* omap4/5: Use CPUDIR for .lds scriptThomas Weber2012-07-07-2/+2
| | | | Signed-off-by: Thomas Weber <thomas@tomweber.eu>
* tegra: trimslice: fix a couple typosStephen Warren2012-07-07-2/+2
| | | | | | | | | | Fix the .dts file USB unit addresses not to duplicate each-other. Fix the board name string to indicate the vendor is Compulab not NVIDIA. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* arm: Tegra: Use ODMDATA from BCT in IRAMTom Warren2012-07-07-9/+25
| | | | | | | | | | | | | | | | Walk the BIT and BCT to find the ODMDATA word in the CustomerData field and put it into Scratch20 reg for use by kernel, etc. Built all Tegra builds OK; Booted on Seaboard and saw ODMDATA in PMC scratch20 was the same as the value in my burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities will have to specify the odmdata (nvflash --odmdata n) on the command line or via a cfg file, or built in to their BCT. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
* tegra: seaboard: disable SPI, move environment to eMMCStephen Warren2012-07-07-25/+4
| | | | | | | | | | | | | | | | | | | | | | | | | The SPI hardware on Seaboard is too broken to use; it is muxed with the console UART and requires evil interactions between the SPI and UART drivers to work even partially. The current code in U-Boot is not sufficient to make this work correctly; auto boot is aborted due to corruption in the UART RX channel interrupting it. Instead, move the environment to eMMC, at the end of the second boot sector. This should not conflict with any other eMMC usage, irrespective of whether the board boots from SPI, NAND, or eMMC: if U-Boot is stored in eMMC, it will be stored well below this location. The kernel only uses the general area of the eMMC once booted, not the boot sectors. Boards that are derivatives of Seaboard don't have the muxing issue, and should/could have a separate U-Boot configuration file that does enable SPI if desired. Alternatively, the environment could be stored in NAND flash, but we currently have no driver for that controller. Signed-off-by: Stephen Warren <swarren@nvidia.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: paz00: store environment in eMMCStephen Warren2012-07-07-2/+4
| | | | | | | | | | Store the environment in eMMC, at the end of the second boot sector. This should not conflict with any other eMMC usage: U-Boot is stored well below this location, and the kernel only uses the general area of the eMMC once booted, not the boot sectors. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: trimslice: store environment in SPI flashStephen Warren2012-07-07-2/+14
| | | | | | | The chosen flash offset matches Compulab's downstream U-Boot. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* gpio: tegra2: rename tegra2_gpio.* to tegra_gpio.*Tom Warren2012-07-07-7/+8
| | | | | | | | In anticipation of Tegra3 support, continue removing/renaming Tegra2-specific files. No functional changes (yet). Updated copyrights to 2012. Signed-off-by: Tom Warren <twarren@nvidia.com>
* mmc: tegra2: rename tegra2_mmc.* to tegra_mmc.*Tom Warren2012-07-07-20/+20
| | | | | | | | In anticipation of Tegra3 support, continue removing/renaming Tegra2-specific files. No functional changes (yet). Updated copyrights to 2012. Signed-off-by: Tom Warren <twarren@nvidia.com>
* spi: tegra2: rename tegra2_spi.* to tegra_spi.*Tom Warren2012-07-07-10/+9
| | | | | | | | In anticipation of Tegra3 support, start removing/renaming Tegra2-specific files. No functional changes (yet). Also updated copyright to 2012. Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: whistler: store environment in eMMCStephen Warren2012-07-07-2/+9
| | | | | | | | | | | | | | | Store the environment in eMMC, at the end of the second boot sector. This should not conflict with any other eMMC usage: U-Boot is stored well below this location, and the kernel only uses the general area of the eMMC once booted, not the boot sectors. Note: This assumes the user plugged the standard 8MB MoviNAND card into J29/HSMMC/POP. If they didn't, the boot sector layout may be different. However, use of that particular card is standard practice as far as I know. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: ventana: store environment in eMMCStephen Warren2012-07-07-2/+4
| | | | | | | | | | Store the environment in eMMC, at the end of the second boot sector. This should not conflict with any other eMMC usage: U-Boot is stored well below this location, and the kernel only uses the general area of the eMMC once booted, not the boot sectors. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* sf: winbond: Add support for the Winbond W25Q80BLStephen Warren2012-07-07-0/+8
| | | | | | | This chip is present on the Compulab TrimSlice. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* env_mmc: align buffers using ALLOC_CACHE_ALIGN_BUFFERStephen Warren2012-07-07-5/+5
| | | | | | | | | This allows MMC drivers to perform cache flusing on the bufffers without issue. Signed-off-by: Stephen Warren <swarren@nvidia.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: ventana: add own device tree, enable USBStephen Warren2012-07-07-1/+72
| | | | | | | | | | Add a device tree for Ventana; the Seaboard file no longer represents the HW present on Ventana. Enable USB on Ventana. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: remove CONFIG_USB_ETHER_SMSC95XX from boards without itStephen Warren2012-07-07-4/+0
| | | | | | | | | | | | | | The SMSC95xx series may exist either directly on a main board, or as a USB to Ethernet dongle. However, dongles containing these chips are very rare. Hence, remove this config option, except on Harmony where such a chip is actually present on the board. The asix option remains, since it's a popular chip, and I actively use a dongle containing this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* tegra: override compiler flags for low level init codeamartin@nvidia.com2012-07-07-2/+5
| | | | | | | | | | | | | | | Override -march setting for tegra to -march=armv4t for files that are necessary for low level init on tegra. The recent change to use -march=armv7-a for armv7 caused a regression on tegra because tegra starts boot on a arm7tdmi processor before transferring control to the cortex-a9. While still executing on the arm7tdmi there are calls to getenv_ulong() and memset() that cause an illegal instruction exception if compiled for armv7. Signed-off-by: Allen Martin <amartin@nvidia.com> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Correct PLL access in ap20.c and clock.cSimon Glass2012-07-07-6/+9
| | | | | | | | | | | | | Correct this warning seen by Albert: ap20.c:44:18: warning: array subscript is above array bounds There is a subtle bug here which currently causes no errors, but might in future if people use PCI or the 32KHz clock. So take the opportunity to correct the logic now. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: paz00: add device tree supportStephen Warren2012-07-07-1/+78
| | | | | | | ... to enable USB host support, which enables Ethernet support. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: harmony: add device tree supportStephen Warren2012-07-07-1/+78
| | | | | | | ... to enable USB host support, which enables Ethernet support. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Compulab TrimSlice board supportStephen Warren2012-07-07-0/+270
| | | | | Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: add SDMMC1 on SDIO1 funcmux entryStephen Warren2012-07-07-0/+8
| | | | | | | This will be used on TrimSlice. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: add SDIO1 funcmux entry for UARTALucas Stach2012-07-07-0/+8
| | | | | | | | | | | | | | | This is based on top of: tegra: add alternate UART1 funcmux entry tegra: add UART1 on GPU funcmux entry v2: remove enum change Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Tom Warren <twarren@nvidia.com> CC: Marek Vasut <marex@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: sync SDIO1 pingroup enum name with TRMLucas Stach2012-07-07-4/+4
| | | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> CC: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: add UART1 on GPU funcmux entryStephen Warren2012-07-07-1/+9
| | | | | | | TrimSlice uses UART1 on the GPU pingroup. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: seaboard: add support for USB networkingStephen Warren2012-07-07-0/+9
| | | | | Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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