| Commit message (Collapse) | Author | Age | Lines |
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Add fec support for sabreauto board
Need hardware rework:
1. Add R450 10.0k
2. Remove R1105 1k
3. short Pin 1,2 of u516, will impact CAN1
Signed-off-by: Hake Huang <b20222@freescale.com>
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The root cause is the L1 I-cache need invalidation,
now we don't need this workaround, so remove it.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Disable the uboot workaround. It will crash the MFGTOOL.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Align latest boot command with user guide.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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We need to check CPU temperature in uboot, if cpu
is too hot, we will let it waiting there until cpu
temperature drop to save region, then go on boot
up.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Fix fastboot can't used on mmc1 device on android.
caused by the mmc part number use strtoul but it need the partition number < 0 .
So this caused such error.
Fixed by change strtoul to strtol.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Fix incorrect VDDSOC voltage setting in uboot.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add workaround for POR/wdog reset issue, we need to
do a CORE LDO reset everytime POR/wdog reset, otherwise
kernel will crash or hang when we booting more than 2
cores. Root cause is still under investigation, it is
analog/power related issue, may take long time to
identify the root cause, we need to add workaround to make
function ready first. The flow of workaround is as below:
1. Check CORE LDO reset flag, currently stored in SNVS_LPGPR[0];
2. If it is there, clear it, go on boot up system; If not,
Set the flag, configure wdog to timeout in 0.5 seconds, then
disable CORE LDO and wait for wdog timeout;
This workaround will bring 0.5~1 seconds delay of booting.
Signed-off-by: Anson Huang <b20788@freescale.com>
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- When the system is very busy(such as play 1080p streaming in local)
the WIFI & FEC performance were very low.
- Enable the patch in uboot for WIFI and FEC performance:
If WIFI connect to PORT2, enable the config:
CONFIG_ADJUST_WIFI_FEC_PERFORMANCE
CONFIG_WIFI_SDHC_PORT2
If WIFI connect to port3, enable the config:
CONFIG_ADJUST_WIFI_FEC_PERFORMANCE
CONFIG_WIFI_SDHC_PORT3
- The solution of the patch:
I. Changing M4IF dynamic jump value to zero, which can guarantee FEC the
high rate of accessing bus.
II. Increase Master 4 priority for FEC.
Increase Master 2 and AHBMAX priority for WIFI.
- Test result:
i.MX53 FEC bandwidth (1080p streaming playback in local): 47.1 Mbits/sec.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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- "bootp" command sometime cannot work well in i.MX53 platform.
- Cause:
Phy detect cable link need some time, so need wait the complete
of cable detect.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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For uImage's size of mx6q is larger than 3M, we enlarge mmc read size to
4M in default env.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Fix the ENET PHY settings on MX6 Sabre-lite to enable Master mode
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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Fix recovery key detection, the VOL_DN key is low assert.
Or it will always enter recovery mode.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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As we want TF to be default boot media.
Then SD slot can be used by WIFI dongle.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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add android mx6q sabrelite configure file.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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add mx6q sabrelite board support for fastboot and recovery.
add recovery key check, same key as in MX53_SMD.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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add support for otg in MX6Q uboot to enable fastboot function.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Add support for MX6Q ARM2 LPDDR2 POP CPU Board. Change thing include
- TEXT_BASE
- RAM address and size
- Initialization DCD
- MMU related code
Use mx6q_arm2_lpddr2pop_config as the build config. After u-boot.bin is
generated, set the board to serial download mode, use sb loader to run the
bootloader.
There is one line in the original DDR initialization script
setmem /32 0x00B00000 = 0x1
however this address can not be accessed by DCD. A try to add it later in
"dram_init" block the boot up. Waiting for IC team to give an explanation
on it. Hold temperorily
The MMU Change can be concluded as the following
- Cacheable and Uncacheable SDRAM allocation changes to
Phys Virtual Size Property
---------- ---------- -------- ----------
0x10000000 0x10000000 256M cacheable
0x80000000 0x20000000 16M uncacheable
0x81000000 0x21000000 240M cacheable
- TEXT_BASE change to 0x10800000, which reserves 8MB of memory at the start
of SDRAM. This address makes sure that the text section of U-boot have the
same Physical and Virtural address, thus the PC don't need to change when
MMU is enabled. Also the text section is all allocated in cacheable memory,
which may increase excecution performance.
- Since this SDRAM allocation avoid overlap in physical memory between
cacheable and uncacheable memory, the implementation of __ioremap can be
ignored
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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Fix for DDR3 initialization based on the MX6Q ARD. This will
reflect 2GB of RAM onboard.
Signed-off-by: Prabhu Sundararaj <prabhu.sundararaj@freescale.com>
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add i2c recovery function in board_lateinit,merge the patch of ENGR00163704
Signed-off-by: Robin Gong <B38343@freescale.com>
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Enabled the functioon of DDR auto-calibration in flash_header.S
of HW PCBA.
Signed-off-by: Robin Gong <B38343@freescale.com>
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Implement the power off function when push the PWR key for 4s
Signed-off-by: Robin Gong <B38343@freescale.com>
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This patch add a i2c bus recovery function, the i2c bus busy
because some device pull down the I2C SDA line. This happens
when Host is reading some byte from slave, and then host is
reset/reboot.
Since in this case, device is controlling i2c SDA line, the
only thing host can do this give the clock on SCL and sending
NAK, and STOP to finish this transaction.
To fix this issue:
when we found SDA is low, we generate 8 clock to let device
send data, then send a NAK, and STOP to finish this I2C
transaction , after this the clock will be clean.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Add "download_mode" command to U-Boot. It will force a system reset and let
boot running in "boot from serial rom" mode, which can be used by manufacturing
tool.
The command will triggle a write to SRC_GPR9 and SRC_GPR10, then triggle a
watchdog reset. GPR9 and GPR10 can maintain their value during the reset, the
value in it make ROM to start in "boot from serial rom" mode. After that GPR9
and GPR10 are written by their original value for normal boot.
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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Fix minor error when adding recovery related code.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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current schema is to enable this extra charging circuit, and
then enable or disable it by checking VBatt is less or more
than 3.4v. If VBatt is less than 3.4v, enable it; otherwise
disable it.
Signed-off-by: Robby Cai <R63905@freescale.com>
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there's some incorrect setting in spi mode, fixed in this patch.
Signed-off-by: Robby Cai <R63905@freescale.com>
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- Descript:
Ethernet can't work in uboot and kernel DHCP throught press
'reset' key when send sleep command 'echo mem > /sys/power/state'
- Cause:
FEC driver will power down phy when system sleep. If just reset the
board, FEC driver cannot run resume function. So, need power on phy
in uboot and linux driver.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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mx53_smd, mx53_loco DA9053: reset da9053 i2c by sending
9 dummy clock and start/stop when bootup and add dummy write
when accessing da9053 registers.
Signed-off-by: Wayne Zou <b36644@freescale.com>
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- Issue description:
Fec can not get ip address to download kernel if insert the
cable after powering up the board more than 20 seconds.
- Patch:
Restart init FEC interface when net cannot get packets. The
cause maybe cabel are unplugin or FEC are not ready.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Add download_mode command in uboot to enter MFG dowload mode ,
you can try download mode command in uboot and enter download mode.
it first set srtc register, then before enter linux,
it will clear these register to prevent the up comming watchdog
reset will enter mfgtool mode.
only add mx53 now.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Add enet clk change support for mx6.
Signed-off-by: Terry Lv <r65388@freescale.com>
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1. Change RAM size from 2GB to 1GB
2. Default boot from MMC Dev 2
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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Implement a key press check on recovery mode check.
User can press Vol- key to enter recovery mode when boot.
Idealy, should be a combo key press together, but on SMD
it only can Vol+ or Vol- but it can't press together.
More usuful for user and less bug.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Set the VDDSOC LDO to increase the VDDSOC cap to 1.2V.
This is required for correct functioning of GPU and when the
ARM LDO is set to 1.225V (when ARM core is at 1GHz).
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Rev C of pcba will connect mc34708 by spi default, so uboot should support it:
1. add spi support in mx53_pcba
2. move pmic voltage config from board_init to board_late_init
3. support both I2C and SPI on mc34708 in one image
Signed-off-by: Robin Gong <B38343@freescale.com>
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If we replace DCD mode with plug-in mode in u-boot , we found DDR not stable.
We should enable "Force Measurement" after the delay line
parameters is configured in the plug-in code, for example:
0x63fd9088 = 0x34333936
0x63fd9090 = 0x49434942
0x63fd90F8 = 0x00000800 "Force Measurement"
update all of mx53 DDR script, include mx53_smd,mx53_loco,mx53_evk,mx53_ard,
mx53_pcba, at the same time, mx53_pcba will change from DCD mode to plug-in
mode in flash_header.S
Signed-off-by: Robin Gong <B38343@freescale.com>
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Remove u-boot build warnings for mx6q.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add the MACRO define CONFIG_APBH_DMA which missed in last commit
Signed-off-by: Allen Xu <allen.xu@freescale.com>
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set IPU AXI-id0 Qos=0xf(bypass) and AXI-id1 Qos=0x7,
mx6q use AXI-id0 for IPU display channel, it should has
highest priority(bypass), and AXI-id1 for other IPU channel,
it has high priority.
Signed-off-by: Jason Chen <b02280@freescale.com>
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Add support for the manufacturing tool on MX6 Sabre-lite
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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Ungate the clocks to SD1 and SD2 ports (on baseboard of ARM2 system)
so that the above cmds do not hang waiting for cmd to complete or
timeout.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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set charging current limit to 1p5
Signed-off-by: Robby Cai <R63905@freescale.com>
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set IPU AXI-id0 Qos=0xf(bypass) and AXI-id1 Qos=0x7,
mx6q use AXI-id0 for IPU display channel, it should has
highest priority(bypass), and AXI-id1 for other IPU channel,
it has high priority.
Signed-off-by: Jason Chen <b02280@freescale.com>
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- Add plugin DRAM init script in flash_header.S file.
- Define CONFIG_FLASH_PLUG_IN in mx6q_sabreauto.h to switch plugin mode.
- DDR support 528MHz and 480MHz in plugin mode.
Switch DDR clock to 480M according to define CONFIG_IPG_40M_FR_PLL3.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Move the code to read the mac address from the fuse to SoC file
and out of the board file
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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Allow boot to either SD card through 6q_bootscript.
Define clearenv command to restore factory defaults
Add upgradeu command to upgrade u-boot if required
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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Add iomux and clock setting in Uboot code to support NAND, due to
the conflict between NAND and SD, NAND function is not enabled in
default configuration.
Signed-off-by: Allen Xu <allen.xu@freescale.com>
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Fix the code to read the MAC address correctly from the fuses
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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Add support to read and program fuses in the MX6 Sabre-lite
Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
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