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* ENGR00215515 MX6: Move IPU QoS and VDOA/IPU/VPU AXI Cache config to kernelWayne Zou2012-07-02-70/+18
| | | | | | | Move IPU QoS and VDOA/IPU/VPU AXI Cache config to linux kernel in order to reduce code duplicate Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00214947 MX6 UBOOT : default enable wait mode as default parametersEric Sun2012-06-26-8/+6
| | | | | | | | For historical reasons U-Boot set "enable_wait_mode=off" in default U-Boot parameter. Now wait mode is OK for these platforms so we remove these settings. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00214866 MX6SL ARM2, UBoot : Apply V0.91 LPDDR2 ScriptEric Sun2012-06-26-463/+397
| | | | | | | | | | | Validation team released lateset LPDDR2 script V0.91, See "http://compass.freescale.net/livelink/livelin k?func=ll&objId=226435628&objAction=browse&viewType=1" This change is necessary for bus freq scaling Apply it for both DCD mode and plugin mode. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00213689 - U-Boot: EPDC Splash Screen failing for MX 6DL/SDanny Nold2012-06-14-4/+4
| | | | | | | | | | | Fix a hang and a garbage update to the E Ink panel with the following changes for both MX 6DL/S SabreSD and MX 6DL/S ARM2: - Update the address for the EPDC waveform file to 6MB offset in SD card. - Update the waveform file size to cover the default Pearl panel waveform file. Signed-off-by: Danny Nold <dannynold@freescale.com>
* ENGR00212229 [MX6SL_ARM2]uboot: 8bit MMC cards failed to boot on SD1.Ryan QIAN2012-06-08-4/+4
| | | | | | | | | | | | issue: SD1 connector on ARM2 is an MS-SD combo one which can not make good contact with DAT4~DAT7 of 8bit mmc cards. It is an hw limitation which will cause boot failure from 8bit mmc. solution: disable SD1 8bit mode on MX6SL arm2 board. Signed-off-by: Ryan QIAN <b32804@freescale.com>
* ENGR00212571 [MX6]Change DRAM ODT setting to save powerAnson Huang2012-06-06-17/+17
| | | | | | | | | | | | | | | | We can use weak ODT setting, it will save about 50% DDR power in runtime. Now we use 0x00007 MMDC0_MPODTCTRL MMDC1_MPODTCTRL, (Ohm) Setting DDR_ODT imx_ODT Max_overclocking 0x22227 120 060 615MHz 0x11117 120 120 604MHz 0x00007 120 000 576MHz 0x00000 000 000 556MHz Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00212287 - U-Boot EPDC splash screen: Disable EPDC splash by defaultDanny Nold2012-06-04-4/+4
| | | | | | | | | | - EPDC splash screen changed to be disabled by default in the config file for MX6DL_SABRESD and MX6DL_ARM2. If left enabled, the U-Boot image will not boot correctly (hang), since some additional content on the boot device (waveform file) is required for EPDC splash to work correctly. - Fixes U-Boot break introduced with commit for ENGR00212287 Signed-off-by: Danny Nold <dannynold@freescale.com>
* ENGR00211117 - U-Boot: Add EPDC splash screen for MX 6DL/S platformsDanny Nold2012-05-30-10/+653
| | | | | | | | | - EPDC Splash support for MX6DL/S Sabre SD - EPDC Splash support for MX6DL/S ARM2 - Currently, splash screen consists of a simple black border around a white screen. Done this way to save in memory footprint. Signed-off-by: Danny Nold <dannynold@freescale.com>
* ENGR00211038 Fix the PAD_LVE implementationMahesh Mahadevan2012-05-30-2/+2
| | | | | | Fix the PAD_LVE implementation used on MX6SL. Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@freescale.com>
* ENGR00210918-2 cleanup android support, build pass all boardsZhang Jiejing2012-05-29-367/+220
| | | | | | | | | | - move recovery.h to common inlcude place. - move supported_reco_envs to soc related, not board related, - user can change this via configure header, don't needs this in every board file. - pass build for all mx5/mx6 android configs. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00210918-1 android: add mx6sl android supportZhang Jiejing2012-05-29-5/+116
| | | | | | | | | | - add android build config for mx6sl_arm2 board. - add gpio support for mx6sl - add boot image support - add android recovery support - add fastboot support, but fastboot cannot transfer file. Signed-off-by Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00209910 Add support for MX6SL mfgtools firmware supportFrank Li2012-05-21-0/+288
| | | | | | Add support for MX6SL mfgtools firmware support Signed-off-by: Frank Li <Frank.Li@freescale.com>
* ENGR00209899-2 MX6Q: cleanup: cleanup fastboot, udc warnning.Zhang Jiejing2012-05-21-5/+14
| | | | | | cleanup android fastboot and udc build warnnings. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00209899-1 mx6x: add generic gpio interface.Zhang Jiejing2012-05-21-44/+210
| | | | | | | | | | | | | | | | | | | | | | Add generic gpio interface in uboot. Seems more and more gpio operation invoke in uboot, without RAW register operation, we should use generic gpio interface. you should define the CONFIG_MXC_GPIO use generic gpio interface: gpio_request, gpio_direction_output, gpio_direction_input, gpio_set_value, gpio_get_value, etc. Test on MX6Q, MX6DL. Other MX6X should also define this config. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00210014 i.mx6 : i.mx6sl : add PAD_CTL_LVE support for pad configurationEric Sun2012-05-18-7/+14
| | | | | | | | | | | Original pad configuration don't provide enough bitfield width to hold all necessary information. For MX6Sololite, a "PAD_CTL_LVE" is needed to be configed for many pins. iomux_v3_cfg_t is re-orgnized to address this issue. PAD_CTRL is extended by 1 bit to hold the "PAD_CTL_LVE". Which is mapped to proper bit location when configure the PAD config register. Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00180103 MX6 sabreauto: Adjust IPU AXI-id0/1 Qos valueWayne Zou2012-05-16-6/+6
| | | | | | | | | set IPU AXI-id0 Qos=0xf(bypass) and AXI-id1 Qos=0x7, mx6q use AXI-id0 for IPU display channel, it should has highest priority(bypass), and AXI-id1 for other IPU channel, it has high priority. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00209306 i.mx6:i.mx6sl: fixup the load address for i.mx6sl uImageJason Liu2012-05-15-0/+6
| | | | | | | | | In order to support one uImage for the i.mx6 soc family, the bootloader must need fix up the load/entry address by adding the offset 0x70000000 for MX6SL parts due to the ddr physical address start from 0x80000000 on MX6SL,but 0x10000000 for the soc other than i.mx6sl Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00209059 android: refine fastboot and recovery support.imx-android-r13.3Zhang Jiejing2012-05-14-191/+115
| | | | | | | | | | 1. add check asrc register to enter recovery mode, rather then check the file. 2. fix the boot.img can not fastboot flash function. 3. consolidate and cleanup fastboot code. 4. clean up many build warnning message. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00182459 fastboot: change vid pid to align with winXP fastboot driver.Zhang Jiejing2012-05-11-20/+20
| | | | | | align vid, pid to let windows fastboot driver can be install. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00182739 sabresd I2C:add i2c recovery function in board_lateinitRobin Gong2012-05-11-4/+286
| | | | | | | | | | This issue have been found in mx53_smd(ENGR00163704), and found in sabresd if accessing pfuze while system reboot or reset, I2C bus will be blocked even if reboot,then pfuze will be failed to be probed, all device driver which use pfuze regulator will be impacted. In u-boot, we can check the SDA line low or high, if low, generate SCL and STOP signal to tell I2C device release I2C bus. Please check ENGR00163704 Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00182426 MX6DL: add fastboot support for MX6DL.Zhang Jiejing2012-05-09-2/+2
| | | | | | | | fix mx6dl usb init issue, due to leak of reset phy, it was only called on MX6Q. Signed-off-by: Shi Make <make.shi@freescale.com> Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00182017 mx6dl sabresd I2C: fix build error and support mx6dl_sabresdRobin Gong2012-05-07-3/+4
| | | | | | | | | | | | | | 1.fix build error : mx6q_sabresd.c: In function 'setup_i2c': mx6q_sabresd.c:382: error: expected ')' before ';' token mx6q_sabresd.c:393: error: expected ';' before '}' token mx6q_sabresd.c: In function 'setup_pmic_voltages': mx6q_sabresd.c:399: warning: unused variable 'val' make[1]: *** [mx6q_sabresd.o] Error 1 2.modify mx6dl_sabresd_config to support pfuze on mx6dl sabresd board Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00181348 pfuze sabresd: pfuze support in u-bootRobin Gong2012-05-04-2/+131
| | | | | | add pfuze and I2C support, support cpu internal LDO bypass which can be enabled by CONFIG_MX6_INTER_LDO_BYPASS Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00181621 : MX6Solo SABREAI - Set default boot up to SD CardPrabhu Sundararaj2012-05-03-1/+1
| | | | | | Set default boot to SD Card Signed-off-by: Prabhu Sundararaj <b36876@freescale.com>
* ENGR00181337-4 i.mx6 : i.mx6sl: Fix FEC RX CRC ErrorEric Sun2012-05-03-1/+10
| | | | | | | | | | | Since FEC_RX_ER is not connected with PHY(LAN8720A), we need either configure FEC_RX_ER PAD to other mode than FEC_RX_ER, or configure FEC_RX_ER PAD to FEC_RX_ER but need pull it down, otherwise, FEC MAC will report CRC error always. We configure FEC_RX_ER PAD to GPIO mode here and remove the SW hack which ignore the CRC error in fec driver Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00181337-3 i.mx6: i.mx6sl: add initial support for i.mx6sl ARM2 boardEric Sun2012-05-03-0/+2236
| | | | | | | | | | | | | | | | | This patch is to add the initial support for i.mx6sl ARM2 board, the patch does: - implemention of LPDDR2 init script - Plug-in/DCD mode support to do DDR initialization - Debug UART(UART1) support - SPI-NOR(M25P32, 4MB) flash support - FEC support, PHY(LAN8720A, RMII mode) - SD/MMC card support, SD1/SD2/SD3 Signed-off-by: Danny Nold <dannynold@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com> Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00181337-2 i.mx6 : i.mx6sl arm2 add EPDC supportEric Sun2012-05-03-41/+223
| | | | | | Add EPDC splash screen support for U-Boot Signed-off-by: Danny Nold <dannynold@freescale.com>
* ENGR00181337-1 i.mx6 : add initial support for i.mx6slEric Sun2012-05-02-20/+3152
| | | | | | | | | | | | | | This patch is to add the initial support for Freescale i.mx6sl chip. i.mx6sl is the SoloLite verison of Freescale i.mx6 family. The patch does: - memory layout support, - iomux support, - clock support, Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Ryan QIAN <b32804@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00180955 mx6q sabresd snvs TKT104835: fix long press ONOFF failed in u-bootRobin Gong2012-04-26-0/+11
| | | | | | | | | | | Need set Power Supply Glitch to 0x41736166 and clear Power Supply Glitch Detect bit when POR or reboot or power on, otherwise system could not be power off anymore, it will power up auto agian. These steps may be move to ROM code or fix by soc team in the future(PDM ticket number:TKT104835), anyway,u-boot fix the issue firsly. Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00180623 fastboot: add fastboot in MX6Q_SABERSD boardsZhang Jiejing2012-04-24-20/+55
| | | | | | | | add fastboot function back in MX6Q_SABERSD board. the MX6DL_SABERSD have usb init related issue which will keep RESET, but left as later developement. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* MX: Added definition file for MC13892Stefano Babic2012-04-20-0/+160
| | | | | | | | The MC13892 is a Power Controller used with processors of the family MX.51. The file adds definitions to be used to setup the internal registers via SPI. Signed-off-by: Stefano Babic <sbabic@denx.de>
* IMX: uniform GPIO interface using GPIO frameworkStefano Babic2012-04-20-73/+519
| | | | | | | | | IMX processors has a slightly different interface to access GPIOs and do not make use of the provided GPIO framework. The patch substitutes mxc_ specific functions and make use of the API in asm/gpio.h Signed-off-by: Stefano Babic <sbabic@denx.de>
* Add generic gpio.h in asm-genericSimon Glass2012-04-20-0/+74
| | | | | | | Since we want want to have a standard GPIO interface, this adds a definition for this into include/asm-generic/gpio.h. Signed-off-by: Simon Glass <sjg@chromium.org>
* misc: pmic: fix regression in pmic_fsl.c (SPI)Helmut Raiger2012-04-20-6/+2
| | | | | | | | | This fixes write access to PMIC registers, the bug was introduced partly in commit 64aac65099 and in commit c9fe76dd91. It was tested on an i.mx31 with a mc13783. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Acked-by: Stefano Babic <sbabic@denx.de>
* misc: pmic: addI2C support to pmic_fsl driverStefano Babic2012-04-20-200/+66
| | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* misc: pmic: use I2C_SET_BUS in pmic I2CStefano Babic2012-04-20-1/+1
| | | | | | | | Instead of using directly the i2c_set_bus() function, the I2C_SET_BUS macro must be used to avoid build errors for targets without multibus I2C. Signed-off-by: Stefano Babic <sbabic@denx.de>
* misc:pmic:core New generic PMIC driverŁukasz Majewski2012-04-20-1/+422
| | | | | | | | | | | | | | I2C or SPI PMIC devices can be accessed. Separate files: pmic_i2c.c and pmic_spi.c are responsible for handling transmission over I2C or SPI bus. New flags: CONFIG_PMIC - enable PMIC general device. CONFIG_PMIC_I2C/SPI - specify the interface to be used. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Stefano Babic <sbabic@denx.de>
* MX: Added Freescale Power Management DriverStefano Babic2012-04-20-0/+329
| | | | | | | | | The patch add supports for the Freescale's Power Management Controller (known as Atlas) used together with i.MX31/51 processors. It was tested with a MC13783 (MX31) and MC13892 (MX51). Signed-off-by: Stefano Babic <sbabic@denx.de>
* ENGR00179762: i.MX6: print the SOC revision correctlyJason Liu2012-04-18-4/+11
| | | | | | | | | | For example: The soc rev on i.mx6dl rev 1.0 not print correctly: CPU: Freescale i.MX 6 family 0.0V at 792 MHz This patch help u-boot print out the SOC revision correctly: CPU: Freescale i.MX6 family TO1.0 at 792 MHz Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00179013 : MX6Solo/Quad : SABREAUTO: Add Parallel NOR SupportPrabhu Sundararaj2012-04-13-11/+179
| | | | | | | | | | | | | -Added u-boot config CONFIG_CMD_WEIMNOR for MX6Solo/Quad SABREAUTO to support WEIM NOR. - CONFIG_FLASH_HEADER_OFFSET is 0x1000 for WEIM NOR. -SPI NOR and WEIM NOR has pin conflicts, either one can be enabled. - mx6q_sabreauto_config, mx6solo_sabreauto_config configured default for SPI NOR. -In order to enable the read/write commands and to boot from WEIM NOR, need to enable the CONFIG_CMD_WEIMNOR. This will disable SPI-NOR Signed-off-by: Prabhu Sundararaj <b36876@freescale.com>
* ENGR00179000 i.mx6q/dl: sabresd: Add the splash screen supportJason Liu2012-04-13-102/+17
| | | | | | | | | | | | | | | | | | | | This patch will add the splash screen support for the i.mx6q/dl splash screen support. In order to enable the splash screen, you need make sure the following env variable has been set correctly: splashimage=0x30000000 splashpos=m,m lvds_num=0 The splash screen is default OFF, to enable it, please add: on i.mx6dq sabresd platform: define CONFIG_SPLASH_SCREEN in include/configs/mx6q_sabresd.h or on i.mx6dl sabresd platform: define CONFIG_SPLASH_SCREEN in include/configs/mx6dl_sabresd.h Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00179437-2 u-boot: mx6q: iomux: code clean upimx-android-r13.2.1imx_v2009.08Jason Liu2012-04-13-16/+1
| | | | | | | Remove the dead definiton which never used by iomux-v3 framework And move the SION bit definiton to arch-mx6/iomux-v3.h for sharing Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00179437-1: u-boot: iomux: NO_PAD_I/NO_PAD_MUX not set corretlyJason Liu2012-04-13-4/+4
| | | | | | | | NO_PAD_I/NO_PAD_MUX not defined correctly, which will cause build error. And According to iomux-v3.h, the NO_PAD_I/NO_PAD_MUX should be 0 for the pins which does not have PAD/MUX config. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00179150 MX6Q_ARM2 HAB Boot : avoid uImage authentication on un-fused chipEric Sun2012-04-09-25/+81
| | | | | | | | | Before running authentication on uImage in DDR, u-boot first check if SEC_CONFIG[1] (OTP_CFG5[1]) is burned. If so, it means the chip is in secure configuration, the authentication continues; if not, the chip in not in secure configuration, just bypass the authentication Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00176537 mx6qsabreauto: i2c3_sda route settingAdrian Alonso2012-04-05-2/+24
| | | | | | | | | | * In RevB boards a steer logic circuit enables the route path of I2C3_SDA signal and is controlled by EIM_A24__GPIO_5_4 pad. * Configure GPIO_5_4 as as output and enable steer logic circuit. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* ENGR00178989: Disable secrity boot configs.Terry Lv2012-04-05-1/+3
| | | | | | | Security boot need to use fuse item. Thus it should not be enabled as default. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00139223-2 [MX6Q] Secure Boot, enable HAB on ARM2 platform (Stage 2)Eric Sun2012-04-01-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | authenticate_image is called to verify uImage when excecuting "bootm", the uImage togehter with its CSF data should has been located in DDR. The new uImage layout is as the following: +------------+ 0x0 (0x10800000) \ | Header | | +------------+ 0x40 | | | | | | | | | | | | | | Image Data | | . | | . | > Stuff to be authenticated ------+ . | | | | | | | | | | | +------------+ | | | | | | | Fill Data | | | | | | | +------------+ 0x003F_DFE0 | | | IVT | | | +------------+ 0x003F_E000 / | | | | | CSF DATA | <--------------------------------------------------------+ | | +------------+ | | | Fill Data | | | +------------+ 0x0040_0000 Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00139223-1 [MX6Q] Secure Boot, enable HAB on ARM2 platform (Stage 1)Eric Sun2012-04-01-2/+221
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first stage of High Assurance Boot (HAB) is the authentication of U-boot. A CST tool is used to generate the CSF data, which include public key, certificate and instruction of authentication process. Then it is attached to the original u-boot.bin The IVT should be modified to contain a pointer to the CSF data. The original u-boot.bin is with size between 0x27000 to 0x28000. For convinence, we first extend the u-boot.bin to 0x2F000 (with fill 0xFF). Then concatenate it with the CSF data. The combined image is again extend to a fixed length (0x31000), which is used as the IVT size parameter. The new memory layout is as the following. U-Boot Image +-------------+ | Blank | |-------------| 0x400 | IVT |-----------------------+ |-------------| | | | | | | | | | | |Remaining UB | | CSF pointer | | | | | | | | | |-------------| | | | | | Fill Data | | | | | |-------------| 0x2F000 <-------------+ | | | CSF Data | | | |-------------| | | | Fill Data | | | +-------------+ 0x31000 HAB APIs are ROM implemented, the entry table is located in a fixed location in the ROM. We export them so that during the HAB we can have some information about the secure boot process. For convinience some wrapper API is implemented based on the HAB APIs. - get_hab_status : used to dump information of authentication result - authenticate_image : used by u-boot to authenticate uImage For security hardware to function, CAAM related clock (CG0[4~6]) must be open. They are default closed in the original U-boot. "hab_caam_clock_enable" and "hab_caam_clock_disable" are created to open and close these clock gates. The generation of CSF data is not in the scope of this patch. CST tool will be used for this purpose. The procedure will be introduced in another document. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00176837-4 - FEC:enable some macro define for all chipFugang Duan2012-03-31-1/+1
| | | | | | | | | | | | | - Enable below macro define for all chip. Firstly, the marcos will be used in later version for later i.MX. Secondly, fix the build error in the former i.MX series chip before i.MX6. #define PHY_MIPSCR_LINK_UP (0x1 << 10) #define PHY_MIPSCR_SPEED_MASK (0x3 << 14) #define PHY_MIPSCR_1000M (0x2 << 14) #define PHY_MIPSCR_100M (0x1 << 14) #define PHY_MIPSCR_FULL_DUPLEX (0x1 << 13) Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00176834-4 - [imx]:add macro define to include chip head fileFugang Duan2012-03-31-1/+3
| | | | | | | - Different chip will include different head file, so add macro define to limit the use range. Signed-off-by: Fugang Duan <B38611@freescale.com>
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