| Commit message (Collapse) | Author | Age | Lines |
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MX6DQ and MX6DL share the common board file, but only MX6DQ has built-in
SATA, for the SATA PDDQ should be enabled default, so it needs to add
code to distinguish different chip ID.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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The SATA PHY PDDQ configuration is depended on the CONFIG_CMD_SATA
defined or not in board config file. If SATA feature is not config,
then the PDDQ will not be set, SATA PHY will not entry in Low Power
Mode, and it will consume some power even there is no sata devices
on board.
This patch:
1 Enable SATA PHY PDDQ default no matter the SATA is enabled or not in
board config file, SATA module will disable PDDQ first when used phy,
so default enable PDDQ will not affect SATA feature.
2 It needs a delay to wait for SATA PHY initialize after enable it,
otherwise write the phy registers will fail.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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The SATA PHY PDDQ configuration is depended on the CONFIG_CMD_SATA
defined or not in board config file. If SATA feature is not config,
then the PDDQ will not be set, SATA PHY will not entry in Low Power
Mode, and it will consume some power even there is no sata devices
on board.
This patch:
1 Enable SATA PHY PDDQ default no matter the SATA is enabled or not in
board config file, SATA module will disable PDDQ first when used phy,
so default enable PDDQ will not affect SATA feature.
2 It needs a delay to wait for SATA PHY initialize after enable it,
otherwise write the phy registers will fail.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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The SATA PHY PDDQ configuration is depended on the CONFIG_CMD_SATA
defined or not in board config file. If SATA feature is not config,
then the PDDQ will not be set, SATA PHY will not entry in Low Power
Mode, and it will consume some power even there is no sata devices
on board.
This patch:
1 Enable SATA PHY PDDQ default no matter the SATA is enabled or not in
board config file, SATA module will disable PDDQ first when used phy,
so default enable PDDQ will not affect SATA feature.
2 It needs a delay to wait for SATA PHY initialize after enable it,
otherwise write the phy registers will fail.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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The SATA PHY PDDQ configuration is depended on the CONFIG_CMD_SATA
defined or not in board config file. If SATA feature is not config,
then the PDDQ will not be set, SATA PHY will not entry in Low Power
Mode, and it will consume some power even there is no sata devices
on board.
This patch:
1 Enable SATA PHY PDDQ default no matter the SATA is enabled or not in
board config file, SATA module will disable PDDQ first when used phy,
so default enable PDDQ will not affect SATA feature.
2 It needs a delay to wait for SATA PHY initialize after enable it,
otherwise write the phy registers will fail.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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Add partition table for nand boot.
Signed-off-by: b02247 <b02247@freescale.com>
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1. Correct oversight of setup and endpoint complete irq handler sequence
2. Add check to string descriptor index
Signed-off-by: LiGang <b41990@freescale.com>
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Add nand config for android sabreauto
Signed-off-by: b02247 <b02247@freescale.com>
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1. Add more check before writing image to storage
2. Fix failure when using nand storagea
Signed-off-by: LiGang <b41990@freescale.com>
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EPDC will be used when splash screen is shown, EPDC io setup is done
before 3V3 digitial power, which cause critical chip burn-out for all
platforms.
To follow the E-Ink specification, setup EPDC I/O after V3p3 is enable.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Remove mx6dl_arm2 and mx6dl_sabresd config file epdc macro
redefinition to avoid build warning.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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add MFG support for mx6solo sabresd board
Signed-off-by: Jason Liu <r64343@freescale.com>
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make system prompt indicate solo config when using mx6solo_sabresd:
"MX6Solo SABRESD U-Boot > "
Signed-off-by: Jason Liu <r64343@freescale.com>
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1. the new fastboot is an add-on feature, the original fastboot is reserved
2. the new fastboot is a subset of original fastboot, only support "download"
and "flash" command
3. type "fastboot" in uboot to launch the original fastboot utility,
type "fastboot q" in uboot to launch the new fastboot utility
Signed-off-by: LiGang <b41990@freescale.com>
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Add support for Processor UID ATAG in uboot for iMX53. The UID is
present in Fuses bank 0 at offset 0x20.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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Support fastboot and recovery
Signed-off-by: b02247 <b02247@freescale.com>
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Update DDR script of ARD solo emulation, the ddr script
based on the following commit from ddr-scripts-rel git:
dfde48e Added MX6Solo ARD DDR3 init.
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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This patch update the DDR script for mx6solo_sabresd board. The DDR script
based on the following commit from ddr-scripts-rel.git
9d4e11a Added MX6Solo SabreSD DDR3 script
Signed-off-by: Jason Liu <r64343@freescale.com>
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PFDs need to be gate/ungate after PLL lock to reset
PFDs to right state. Otherwise PFDs may lose correct
state in state-machine, then no output clock.
For i.MX6DL and i.MX6SL, ROM have taken care of PFD396
already since the bus clock needs it.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add support for Android fastboot and recovery reboot
commands for iMX5.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
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After using POR reset, the content in SRC will be reset.
See RM: 63.5.1.2.3 IPP_RESET_B(POR)
Because POR reset will reset most of register in IC, so use
SNVS_LP General Purpose Register (LPGPR) to store the boot mode value.
Below copy from SNVS_BlockGuide.pdf:
The SNVS_LP General Purpose Register provides a 32 bit read write
register, which can be used by any application for retaining 32 bit
data during a power-down mode
This Patch will use [7,8] bits of this register.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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This issue due to PODF is not used correcly, need use the following instead:
ACLK_EMI_SLOW_PODF_OFFSET, the original used ACLK_EMI_PODF_OFFSET was wrong.
Signed-off-by: Jason Liu <r64343@freescale.com>
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The issue is caused by DDR script changed io pads to DDR differential mode
but forget to do the calibration data update.
This patch updated the DDR script on MX6DL ARD board based on
the commit on the ddr-scripts-rel:
53121e0 Updated MX6DL and MX6DQ ARD and SabreSD scripts with new
calibration values for IO pads set to differential mode;
Signed-off-by: Jason Liu <r64343@freescale.com>
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The original plugin code uses hard coded assembly address for the code jump
to "pu_irom_hwcnfg_setup", it can only works for specific chip version, for
a new TO, the assembly address will change, and the plugin code simply fails.
In fact there is an API entry table in a fixed ROM location, it contains the
entry to the "pu_irom_hwcnfg_setup". This patch retrieve the jump address
from this API table, thus avoid the limitation for current implementation.
Apply to all plugin enabled platforms, MX6Q/DL ARM2, MX6SL ARM2/EVK
Signed-off-by: Eric Sun <jian.sun@freescale.com>
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Add HDMIdongle board for imx6Q/DL under board/freescale.
Signed-off-by: Zhang Xiaodong <B39117@freescale.com>
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Aligning the flash header to remove the boot plugin as in previous release.
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
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This commit update the DDR script for i.MX6Q sabresd board
based on the top of the following commit on ddr-scripts-rel:
02b8a73 removed some verbage (comments) from init, no changes to actual init
Signed-off-by: Jason Liu <r64343@freescale.com>
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* Remove EIM_A24 nor pads as this are used for
io steer control and are not connectted to NOR
flash memory.
* Fix conflict access when it's used as io control
gpio.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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* Fix redundant enviroment offset
* Disable I2C support as they share pads
* Enable flash empty information
* weim-nor partition layout
+-----------------+ 0x08000000
+ u-boot +
+-----------------+ 0x08040000 (256k)
+ u-boot env +
+-----------------+ 0x08060000 (128k)
+ u-boot redundat +
+-----------------+ 0x08080000 (128k)
+ Kernel +
+-----------------+ 0x08480000 (4M)
+ Rootfs +
+-----------------+ (~27M)
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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* Fix weim-nor boot failure
* Group weim-nor conflict modules
If not defined CONFIG_CMD_WEIMNOR
enable SPI-NOR and I2C (default)
else enable weim-nor
* Remove FLASH_SIZE macro, size is query by
CFI driver
* Enable flash empty information
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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move LDO bypass code and one PFUZE1.0 workaround code to kernel. Remove
CONFIG_MX6_INTER_LDO_BYPASS in u-boot
Signed-off-by: Robin Gong <b38343@freescale.com>
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This patch update the DDR script for the i.MX6DL sabresd board
The script is based on top the commit on ddr-scripts-rel:
02b8a73 removed some verbage (comments) from init, no changes to actual init
Signed-off-by: Jason Liu <r64343@freescale.com>
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This commit update the DDR script for i.MX6Q Sabreauto(AI) board.
The script is based on top the commit on ddr-scripts-rel:
02b8a73 removed some verbage (comments) from init, no changes to actual init
Signed-off-by: Jason Liu <r64343@freescale.com>
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This commit update the DDR script for i.MX6DL Sabreauto(AI) board.
The script is based on top the commit on ddr-scripts-rel:
02b8a73 removed some verbage (comments) from init, no changes to actual init
Signed-off-by: Jason Liu <r64343@freescale.com>
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On mx6q_sabresd RevC board, there is camera streaks issue, after HW check, they
think there is current limit risk because VDDHIGH_IN and camera 2.8V power
share the same VGEN5, they suggest seprate them, so we use VGEN5 as VDDHIGH_IN
and use VGEN3 as camera 2.8V power supply. Also increase VDDHIG_IN from 2.8V to
3.0V to align with latest datasheet
Signed-off-by: Robin Gong <B38343@freescale.com>
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* Fix spi-nor boot failure
* Fix unconfigured gpio pad setting when spi-nor or
weim-nor on steer control gpios
* Group gpio access only when I2C is enabled and restore
route paths to avoid conflicts on shared pads
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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* Aling spi-nor environment offsset to 256k
this allows a partition layout
+-----------------+ 0x0
+ bootloader +
+-----------------+ 0x40000 (256k)
+ boot env +
+-----------------+ 0x42000 (8k)
+ kernel +
+-----------------+ Remaining space (~3.7M)
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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There is no more tolerance issue on PFUZE, it will be only 25mV, so that we no
need increase VDDSOC_IN from 1.375V to 1.425V.
Signed-off-by: Robin Gong <B38343@freescale.com>
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* Adding the config option CONFIG_SECURE_BOOT to the SabreSD board,
but defaulting it to be disabled. Removed the CONFIG_SECURE_BOOT
key from mx6q_arm2_android.h so that it is only in one file,
include/configs/mx6q_arm2.h
* Fixed up an address alignment check in authenticate_image(). The
test would fail in the event the address is already aligned.
Also, added some debug code which can be enabled to assist in
testing secure images.
* Added support for authenticating an image when using booti.
* Adding support for secure boot to the Sabre SD board.
* Added support for encrypted boot to mx6q arm2 board linker script.
Signed-off-by: Dan Douglass <dan.douglass@freescale.com>
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the same as TKT104835 reported on MX6Q/DL
Need set Power Supply Glitch to 0x41736166 and clear Power Supply
Glitch Detect bit when POR or reboot or power on, otherwise system could
not be power off anymore, it will power up auto agian.
Signed-off-by: Lin Fuzhen <fuzhen.lin@freescale.com>
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In some imx6sl evk boards, fec cannot work fine while doing
cycle reboot via to execute command "reboot" in kernel.
The root cause: phys clock source is closed when reboot system,
and LAN8720 status machine is in disorder. So it needs to do phy
hardware reset to make phy enter normal state machine.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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add a new config for NAND boot in the mx6q-arm2 board.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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We may use the 8K page nand now. So expand the page size from 4k
to 8K. Also expand the oobsize to 1K size.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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We have get the right infomation when we call the set_geometry().
So we replace the hardcode with the proper gpmi_info's values.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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This patch removes the 'semiconductor' word in the freescale
reversed color logo to align with the standard(preferred) one
which can be found at the link:
http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-logosdisclaim
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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In the mx23/mx28, the DATA0_SIZE/DATAN_SIZE of the BCH's
HW_BCH_FLASH1LAYOUT0/HW_BCH_FLASH0LAYOUT1 should be the real
bytes length of the data chunk 0 and data chunk 1.
But in the mx6q/mx50, the DATA0_SIZE/DATAN_SIZE of the BCH's
HW_BCH_FLASH1LAYOUT0/HW_BCH_FLASH0LAYOUT1 should be multiple of 4 bytes.
this patch fixes the wrong macros.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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1. Add matrix key support
2. Add recovery mode support by pressing power key and volume down key
when boot
SW10 on MX6SL-EVK board configed as volume down key.
SW1 on MX6SL-EVK board configed as power key
Signed-off-by: LiGang <b41990@freescale.com>
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We need to check reg bit to decide I2C parent clock.
Signed-off-by: Terry Lv <r65388@freescale.com>
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To save power, set all switches to PFM mode in standby,although PFM mode need
6% tolerance.But it will be implemented in kernel, and move the workaround
which all buck switches need be configured PWM mode on PF100 1.0
Another two change is:
1. u-boot will print PFUZE device id and revision id.
2. add value check for i2c write and read.
Signed-off-by: Robin Gong <B38343@freescale.com>
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- currently only a work around can be applied, the root cause is not
identified yet
The workaround is to disable wait mode, so all the mfgtool uboot
need to add "enable_wait_mode=off" in the cmd line pass to kernel
Signed-off-by: Tony LIU <junjie.liu@freescale.com>
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