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* mmc: rename CONFIG_ROCKCHIP_DWMMC to CONFIG_MMC_DW_ROCKCHIPMasahiro Yamada2017-01-11-14/+14
| | | | | | | | | | | | | I am trying to make all DesignWare-based driver options prefixed with CONFIG_MMC_DW_. This commit was generated as follows: find . -name .git -prune -o -type f -print | \ xargs sed -i -e 's/ROCKCHIP_DWMMC/MMC_DW_ROCKCHIP/g' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
* ARM: socfpga: remove unused CONFIG option and cleanup README.socfpgaMasahiro Yamada2017-01-11-27/+0
| | | | | | | | | | | | | CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH is defined in the socfpga_common.h, but not referenced at all. Remove. Also, clean-up the README.socfpga. CONFIG_MMC should not be defined in the header since it was moved to Kconfig by commit c27269953b94 ("mmc: complete unfinished move of CONFIG_MMC"). I see no grep hit for the others. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
* power: change from meaningless value to error numberJaehoon Chung2017-01-11-67/+64
| | | | | | | | '-1' is absolutely meaningless value. This patch changed from meaningless value to error number. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mmc: uniphier-sd: fix Kconfig dependencyMasahiro Yamada2017-01-11-2/+2
| | | | | | | | | | | | | | | | | Some MMC drivers describe operations with the DM_MMC_OPS form, but there are still several drivers with older implementation. We can not compile drivers from different groups at the same time because the core framework is shared with #ifdef CONFIG_DM_MMC_OPS. Every driver should have "depends on DM_MMC_OPS" (or !DM_MMC_OPS) explicitly to express which framework it is based on. This will avoid enabling drivers with incompatible interface at the same time. It is incorrect to make a driver "select DM_MMC_OPS". While we are here, add "depends on OF_CONTROL" as well because this driver can be configured only by Device Tree. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: sdhci-cadence: add Cadence SD4HC supportMasahiro Yamada2017-01-11-0/+138
| | | | | | Add a driver for the Cadence SD4HC SD/SDIO/eMMC Controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: sdhci: combine the Host controller v3.0 feature into one conditionJaehoon Chung2017-01-11-10/+7
| | | | | | It doesn't need to seperate the condition. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: remove the SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWERJaehoon Chung2017-01-11-4/+0
| | | | | | Ther is no usage anywhere. It doesn't need to maintain this bit. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: use the bitops APIs in sdhci.hJaehoon Chung2017-01-11-56/+56
| | | | | | The using the bitops is too easy controlling than now. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: move the callback function into sdhci_opsJaehoon Chung2017-01-11-16/+19
| | | | | | | | callback function should be moved into sdhci_ops struct. Other controller can use these ops for controlling clock or their own specific register. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: s5p_sdhci: add the s5p_set_clock functionJaehoon Chung2017-01-11-1/+7
| | | | | | | | Add the s5p_set_clock function. It's not good that "set_mmc_clk" is assigned directly. In future, it should be changed to use the clock framework. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: change the set_ios return type from void to intJaehoon Chung2017-01-11-30/+60
| | | | | | To maintain consistency, set_ios type of legacy mmc_ops changed to int. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: remove the SDHCI_QUIRK_NO_CDJaehoon Chung2017-01-11-6/+3
| | | | | | | This quirk doesn't need anymore. It's replaced to get_cd callback function. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: pic32_sdhci: move the code to pic32_sdhci.cJaehoon Chung2017-01-11-6/+17
| | | | | | | | This code is used for only pic32_sdhci controller. To remove the "#ifdef", moves to pic32_sdhci.c. And use the get_cd callback function. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: remove the unused code about testing Card detectJaehoon Chung2017-01-11-11/+0
| | | | | | This code is dead code..There is no usage anywhere. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: add the get_cd callback function in sdhci_opsJaehoon Chung2017-01-11-0/+1
| | | | | | | | Some SoCs can have their own card dect scheme. Then they may use this get_cd callback function after implementing init in their drivers. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: sdhci: disable the 8bit mode when host doesn't support itJaehoon Chung2017-01-11-3/+2
| | | | | | | | | | | | | Buswidth is depeneded on Hardware schematic. Evne though host can support the 8bit buswidth, if hardware doesn't support 8bit mode, it doesn't work fine. So the buswidth mode selection leaves a matter in each SoC drivers. On the contrary to this, hardware supports 8bit mode, but host doesn't support it. then controller has to disable the MMC_MODE_8BIT. (Host can check whether 8bit mode is supported or not, since V3.0) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2017-01-10-18/+194
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| * scsi: dm: Unbind all scsi based block devices before new scanMichal Simek2017-01-09-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New scan should unbind all block devices not to be listed again. Without this patch if scsi reset or scan is called new block devices are created which point to the same id and lun. For example: ZynqMP> scsi scan scsi_scan: if_type=2, devnum=0: sdhci@ff170000.blk, 6, 0 scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 0 scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 1 scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 2 scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 3 scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 4 scanning bus for devices... Device 0: (1:0) Vendor: ATA Prod.: KINGSTON SVP200S Rev: 501A Type: Hard Disk Capacity: 57241.8 MB = 55.9 GB (117231408 x 512) Reported-by: Ken Ma <make@marvell.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
| * defconfig: am335x_evm: enable usb driver modelMugunthan V N2017-01-09-0/+3
| | | | | | | | | | | | | | | | enable usb driver model for am335x bbb as musb supports driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * am335x_evm: enable usb ether gadget as it supports DM_ETHMugunthan V N2017-01-09-3/+0
| | | | | | | | | | | | | | | | Since usb ether gadget have support for driver model, so enable usb ether gadget. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * am33xx: board: init usb ether gadget for rndis supportMugunthan V N2017-01-09-0/+8
| | | | | | | | | | | | | | | | Add usb ether gadget device with usb_ether_init() when CONFIG_DM_ETH and CONFIG_USB_ETHER are defined. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * drivers: usb: gadget: ether/rndis: convert driver to adopt device driver modelMugunthan V N2017-01-09-15/+181
| | | | | | | | | | | | Adopt usb ether gadget and rndis driver to adopt driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* | mips: Use common _AC macro now.Tom Rini2017-01-10-3/+0
| | | | | | | | | | | | | | MIPS no longer needs to have its own version of this macro now. Fixes: 2a6713b09b8d ("move UL() macro from armv8/mmu.h into common.h") Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2017-01-10-196/+564
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| * sunxi: A64: enable SPLAndre Przywara2017-01-04-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the SPL is ready to be compiled in AArch64 and the DRAM init code is ready, enable SPL support for the A64 SoC and in the Pine64 defconfig. For now we keep the boot0 header in the U-Boot proper, as this allows to still use boot0 as an SPL replacement without hurting the SPL use case. We disable FEL support for now by making its compilation conditional and disabling it for ARM64, as the code isn't ready yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: DRAM: fix H3 DRAM size display on aarch64Andre Przywara2017-01-04-1/+1
| | | | | | | | | | | | | | | | | | | | Fix the output of the DRAM size on AArch64 SPLs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: H3/A64: fix non-ODT settingAndre Przywara2017-01-04-1/+7
| | | | | | | | | | | | | | | | | | According to Jens disabling the on-die-termination should set bit 5, not bit 1 in the respective register. Fix this. Reported-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: A64: use H3 DRAM initialization code for A64 as wellJens Kuske2017-01-04-56/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The A64 DRAM controller is very similar to the H3 one, so the code can be reused with some small changes. This refactoring does not change the code size for the existing H3 part. [Andre: rework from #ifdefs to using socid parameters in static functions, minor fixes, merging in fixes from Jens] Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: clocks: Use the correct pattern register for PLL11Philipp Tomsich2017-01-04-1/+1
| | | | | | | | | | | | | | Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: H3: add DRAM controller single bit delay supportJens Kuske2017-01-04-27/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far the DRAM driver for the H3 SoC (and apparently boot0/libdram as well) only applied coarse delay line settings, with one delay value for all the data lines in each byte lane and one value for the control lines. Instead of setting the delays for whole bytes only allow setting it for each individual bit. Also add support for address/command lane delays. For the purpose of this patch the rules for the existing coarse settings were just applied to the new scheme, so the actual register writes don't change for the H3. Other SoCs will utilize this feature later properly. With a stock GCC 5.3.0 this increases the dram_sun8i_h3.o code size from 2296 to 2344 Bytes. [Andre: move delay parameters into macros to ease later sharing, use defines for numbers of delay registers, extend commit message] Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: H3: add and rename some DRAM contoller registersJens Kuske2017-01-04-36/+41
| | | | | | | | | | | | | | | | | | The IOCR registers got renamed to BDLR to match the public documentation of similar controllers. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: H3: Rework MBUS priority setupPhilipp Tomsich2017-01-04-24/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far the MBUS priority setup was done by writing "magic" values taken from a DRAM controller register dump after a boot0 run. By peeking at the Linux (sic!) MBUS driver [1] from the Allwinner BSP kernel, we learned more about the actual meaning of those bits. Add macros and refactor the setup function to make the MBUS setup much more readable and meaningful. The actual values used now are a transformation of the values used before, which are assembled by the new code to result in the same register writes. So this rework does not change any settings, also the code size stays the same. The respective source files in the BSP kernel had a proper GPL header, so lifting this code and information into U-Boot is legal. [Andre: provide a convenience macro to fit definitions on one line] [1] https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65/drivers/bus/sunxi_mbus.c Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: provide default DRAM config for sun50i in KconfigAndre Przywara2017-01-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | To avoid enumerating the very same DRAM values in defconfig files for each and every Allwinner A64 board out there, let's put some sane default values in the Kconfig file. Boards with different needs can override them at any time. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: A64: do an RMR switch if started in AArch32 modeAndre Przywara2017-01-04-0/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A64 SoC starts execution in AArch32 mode, and both the boot ROM and Allwinner's boot0 keep running in this mode. So U-Boot gets entered in 32-bit, although we want it to run in AArch64. By using a "magic" instruction, which happens to be an almost-NOP in AArch64 and a branch in AArch32, we differentiate between being entered in 64-bit or 32-bit mode. If in 64-bit mode, we proceed with the branch to reset, but in 32-bit mode we trigger an RMR write to bring the core into AArch64/EL3 and re-enter U-Boot at CONFIG_SYS_TEXT_BASE. This allows a 64-bit U-Boot to be both entered in 32 and 64-bit mode, so we can use the same start code for the SPL and the U-Boot proper. We use the existing custom header (boot0.h) functionality, but restrict the existing boot0 header reservation to the non-SPL build now. A SPL wouldn't need such header anyway. This allows to have both options defined and lets us use one for the SPL and the other for U-Boot proper. Also add arch/arm/mach-sunxi/rmr_switch.S, which contains the original ARM assembly code and instructions how to re-generate the encoded version. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: introduce extra config option for boot0 headerAndre Przywara2017-01-04-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | The ENABLE_ARM_SOC_BOOT0_HOOK option is a generic option shared with other boards. To allow alternative code to be inserted, we create another, now function specific config symbol on top of it to simplify later additions. No functional change at this time. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * ARM: boot0 hook: remove macro, include whole header fileAndre Przywara2017-01-04-23/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For prepending some board specific header area to U-Boot images we were so far including a header file with a macro definition containing the actual header specification. This works fine if there are just a few statements and if there is only one alternative. However adding more complex code quickly gets messy with this approach, so let's just drop that intermediate macro and let the #include actually insert the code directly. This converts the callers and the callees, but doesn't change anything at this point. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Steve Rae <steve.rae@raedomain.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * armv8: move reset branch into boot hookAndre Przywara2017-01-04-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The boot0 hook we have so far is applied _after_ the initial branch to the "reset" entry point. An upcoming change requires even this branch to be changed, so we apply the hook macro at the earliest point, and have the branch in the hook file as well. This is no functional change at this point, just refactoring to simplify upcoming patches. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * armv8: add simple sdelay implementationAndre Przywara2017-01-04-0/+14
| | | | | | | | | | | | | | | | | | The sunxi DRAM setup code needs an sdelay() implementation, which wasn't defined for armv8 so far. Shamelessly copy the armv7 version and adjust it to work in AArch64. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * SPL: make struct spl_image 64-bit safeAndre Przywara2017-01-04-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since entry_point and load_addr are addresses, they should be represented as longs to cover the whole address space and to avoid warning when compiling the SPL in 64-bit. Also adjust debug prints to add the 'l' specifier, where needed. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * move UL() macro from armv8/mmu.h into common.hAndre Przywara2017-01-04-9/+12
| | | | | | | | | | | | | | | | | | | | | | The UL() macro is pretty useful in sharing constants between assembly and C files while still being able to specify a type for C. Move the macro from an armv8 specific header into a common header file to be able to use it by arm code (for instance) as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * SPL: tiny-printf: ignore "-" modifierAndre Przywara2017-01-04-0/+3
| | | | | | | | | | | | | | | | | | | | tiny-printf does not know about the "-" modifier, which aligns numbers. This is used by some SPL code, but as it's purely cosmetical, we just ignore this modifier here to avoid changing correct printf strings. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * SPL: tiny-printf: add "l" modifierAndre Przywara2017-01-04-11/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tiny-printf does not know about the "l" modifier so far, which breaks the crash dump on AArch64, because it uses %lx to print the registers. Add an easy way of handling longs correctly. Using a relatively decent compiler (GCC 5.3.0) this does _not_ increase the code size of tiny-printf.o for 32-bit builds (where long and int are actually the same), actually it looses three (ARM Thumb2) instructions from the actual SPL (numbers for orangepi_plus_defconfig): text data bss dec hex filename 758 0 0 758 2f6 spl/lib/tiny-printf.o before 18839 488 232 19559 4c67 spl/u-boot-spl before 758 0 0 758 2f6 spl/lib/tiny-printf.o after 18833 488 232 19553 4c61 spl/u-boot-spl after This adds some substantial amount of code to a 64-bit build, though: (taken after a later commit, which enables the ARM64 SPL build for sunxi) text data bss dec hex filename 1542 0 0 1542 606 spl/lib/tiny-printf.o before 25830 392 360 26582 67d6 spl/u-boot-spl before 1758 0 0 1758 6de spl/lib/tiny-printf.o after 26040 392 360 26792 68a8 spl/u-boot-spl after Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * armv8: add lowlevel_init.SAndre Przywara2017-01-04-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | For boards that call s_init() when the SPL runs, we are expected to setup an early stack before calling this C function. Implement the proper AArch64 version of this based on the ARMv7 code. This allows sunxi boards to setup the basic peripherals even with a 64-bit SPL. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * armv8: prevent using THUMBAndre Przywara2017-01-04-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The predominantely 32-bit ARM targets try to compile the SPL in Thumb mode to reduce code size. The 64-bit AArch64 instruction set does not know an alternative, concise encoding, so the Thumb build option should only be set for 32-bit targets. Likewise -marm machine options are only valid for ARMv7 targets. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sun6i: Restrict some register initialization to Allwinner A31 SoCAndre Przywara2017-01-04-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These days many Allwinner SoCs use clock_sun6i.c, although out of them only the (original sun6i) A31 has a second MBUS clock register. Also the requirement for setting up the PRCM PLL_CTLR1 register to provide the proper voltage seems to be a property of older SoCs only as well. Restrict the MBUS initialization to this SoC only to avoid writing bogus values to (undefined) registers in other chips. I can only verify that the PLL voltage setup is not needed for H3 and A64, so for now we only spare those two SoCs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * spl: sunxi: Fix build error with CONFIG_SPL_SPI_SUNXIPriit Laes2017-01-04-1/+1
| | | | | | | | | | | | | | Fix typo introduced in ebc4ef61d76fc182773fe225151adc9b913c62eb Signed-off-by: Priit Laes <plaes@plaes.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | Prepare v2017.01Tom Rini2017-01-09-1/+1
| | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* | lib: gitignore *.elf and *.so generated by efi_loaderLadislav Michl2017-01-09-0/+2
| | | | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* | scripts/config_whitelist.txt: ResyncTom Rini2017-01-08-125/+0
| | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* | mx6ullevk: Add missing MAINTAINERS for mx6ull_14x14_evk_plugin_defconfigJagan Teki2017-01-08-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add 'Peng Fan' as MAINTAINERS of configs/mx6ull_14x14_evk_plugin_defconfig which is missing in below commit "imx: mx6ull_14x14_evk: add plugin defconfig" (sha1: b90ebf49bb8f74afe68f696f59a0e24cc79f2031) Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jagan@openedev.com>
generated by cgit v1.1 at 2024-07-05 03:42:50 +0000