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* lpc32xx: remove surplus clock cycle in PL175 WAIT_OEN configVladimir Zapolskiy2015-10-11-2/+2
| | | | | | | | | | | | | | According to ARM PrimeCell PL175 documentation WAIT_OEN config value is defined without any additional clocks added to the value set by a client, the change fixes the wrong interface to WAIT_OEN config. The change also touches a single user of LPC32xx EMC and corrects configured "output enable delay" value on its side according to the changed interface. No functional change intended. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* nand: omap_gpmc: Change correctable bit-flips messages to debug()Ezequiel García2015-10-11-3/+3
| | | | | | | | Messages on corrected bit-flips are not really useful, as bit-flips are perfectly normal. Let's avoid cluttering the console and make them debug. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
* Fix variation in timestamps caused by timezone differences.Vagrant Cascadian2015-10-11-5/+1
| | | | | | | | | | | When building with SOURCE_DATE_EPOCH set, avoid use of mktime in default_image.c, which converts the timestamp into localtime. This causes variation based on timezone when building u-boot.img and u-boot-sunxi-with-spl.bin targets. Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Tested-by: Paul Kocialkowski <contact@paulk.fr> Acked-by: Paul Kocialkowski <contact@paulk.fr>
* common/image.c: Make boot_get_ramdisk() perform a check for Android imagesTom Rini2015-10-11-0/+9
| | | | | | | | | | | | | | | In 2dd4632 the check for where a ramdisk is found on an Android image was got moved into the "normal" loop here, causing people to have to pass the kernel address in the ramdisk address location in order to have Android boot still. This changed previous behavior so perform a check early in the function to see if we have an Android image and if so use that as where to look for the ramdisk (which is what the rest of the code here expects). We allow for this to still be overridden with an explicit ramdisk address to be passed as normal. Cc: Rob Herring <robh@kernel.org> Reported-by: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Tom Rini <trini@konsulko.com>
* tools/mkimage.c: Clarify help text for -D slightlyTom Rini2015-10-11-1/+1
| | | | | | | Try and make it clear that -D will replace all arguments passed to dtc and is not appending them. Signed-off-by: Tom Rini <trini@konsulko.com>
* arndale: Apply Cortex-A15 errata #773022 and #774769Ian Campbell2015-10-11-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We run 4 Arndale boards in our automated test framework, they have been running quite happily for quite some time using a Debian Wheezy userspace. However when upgrading to a Debian Jessie we started seeing frequent segmentation faults from gcc when building the kernel, to the extent that it is unable to successfully build the kernel twice in a row, and often fails on the first attempt. Searching around I found https://bugs.launchpad.net/arndale/+bug/1081417 which pointed towards http://www.spinics.net/lists/kvm-arm/msg03723.html and CPU Errata 773022 and 774769. This errata needs to be applied to all processors in an SMP system, meaning that the usual strategy of applying them in arch/arm/cpu/armv7/start.S is not appropriate (since that applies to the boot processor only). Instead we apply these errata in the secure monitor which is code that is traversed by all processors as they are brought up. The net affect on Arndale is that ACTLR changes from 0x40 to 0x2000042. I ran 17 kernel compile iterations overnight with no segfaults. Runtime testing was done on our v2014.10 based branch and forward ported (with only minimal and trivial contextual conflicts) to current master, where it has been build tested only. I suppose in theory these errata apply to any Exynos5250 based boards, but Arndale is the only one I have access to and I have therefore chosen to be conservative and only apply it there. Also, reorder CONFIG_ARM_ERRATA_794072 in README to make the list numerically sorted. Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
* image: fix support for Android boot images with no ramdiskRob Herring2015-10-11-1/+3
| | | | | | | | If an Android boot image does not contain a ramdisk, make sure rd_len and rd_data are returned to indicate no ramdisk rather than just relying on returning an error. Signed-off-by: Rob Herring <robh@kernel.org>
* Add support for LZ4 decompression algorithmJulius Werner2015-10-11-0/+471
| | | | | | | | | | | | | | | This patch adds support for LZ4-compressed FIT image contents. This algorithm has a slightly worse compression ration than LZO while being nearly twice as fast to decompress. When loading images from a fast storage medium this usually results in a boot time win. Sandbox-tested only since I don't have a U-Boot development system set up right now. The code was imported unchanged from coreboot where it's proven to work, though. I'm mostly interested in getting this recognized by mkImage for use in a downstream project. Signed-off-by: Julius Werner <jwerner@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* ppc4xx: Remove lcd4_lwmon5 supportStefan Roese2015-10-11-80/+1
| | | | | | | This platform has not gone into production. So lets remove it. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* ppc4xx: Convert lwmon5 board to generic boardStefan Roese2015-10-11-0/+6
| | | | | | | | Add CONFIG_SYS_GENERIC_BOARD to lwmon5.h and CONFIG_DISPLAY_BOARDINFO to Kconfig file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* Revert "powerpc: ppc4xx: remove lwmon5 support"Stefan Roese2015-10-11-2/+2128
| | | | | | | | | | This reverts commit 8fe11b8901a31d11990488c82bc23612589d57be. I'll add support to lwmon5 in the next patch and will remove support for the broken lcd4_lwmon5 as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* fs/fat/fat_write: Fix management of empty filesBenoît Thébaudeau2015-10-11-21/+64
| | | | | | | | | | | | Overwriting an empty file not created by U-Boot did not work, and it could even corrupt the FAT. Moreover, creating empty files or emptying existing files allocated a cluster, which is not standard. Fix this by always keeping empty files clusterless as specified by Microsoft (the start cluster must be set to 0 in the directory entry in that case), and by supporting overwriting such files. Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
* fs/fat/fat_write: Factor out duplicate codeBenoît Thébaudeau2015-10-11-48/+20
| | | | Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
* fs/fat/fat_write: Fix curclust/newclust mix-upBenoît Thébaudeau2015-10-11-3/+3
| | | | | | | curclust was used instead of newclust in the debug() calls and in one CHECK_CLUST() call, which could skip a failure case. Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
* fs/fat/fat_write: Merge calls to set_cluster()Benoît Thébaudeau2015-10-11-12/+1
| | | | | | | | set_contents() had uselessly split calls to set_cluster(). Merge these calls, which removes some cases of set_cluster() being called with a size of zero. Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
* fs/fat/fat_write: Fix buffer alignmentsBenoît Thébaudeau2015-10-11-14/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | set_cluster() was using a temporary buffer without enforcing its alignment for DMA and cache. Moreover, it did not check the alignment of the passed buffer, which can come directly from applicative code or from the user. This could cause random data corruption, which has been observed on i.MX25 writing to an SD card. Fix this by only passing ARCH_DMA_MINALIGN-aligned buffers to disk_write(), which requires the introduction of a buffer bouncing mechanism for the misaligned buffers passed to set_cluster(). By the way, improve the handling of the corresponding return values from disk_write(): - print them with debug() in case of error, - consider that there is an error is disk_write() returns a smaller block count than the requested one, not only if its return value is negative. After this change, set_cluster() and get_cluster() are almost symmetrical. Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>
* ti: omap3: config: remove 1 from boolean defineIgor Grinberg2015-10-11-1/+1
| | | | | | | | CONFIG_TWL4030_POWER is a boolean define variable. It is either defined or not defined and should not have a value assigned to it. Remove the value. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* vexpress64: juno: use /dev/sda2Ryan Harkin2015-10-11-1/+1
| | | | | | | | | | | | | | This patch changes the default "root=" parameter to "/dev/sda2". Many linux based distros use /dev/sda1 for their boot partition; this is often not a rootfs that can be used by the "root=" parameter. Linaro images use /dev/sda1 as a boot partition, although this of a different nature to a distro image. Linaro uses /dev/sda2 for the rootfs partition. Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* vexpress64: juno: add alternate kernel and device tree filenamesRyan Harkin2015-10-11-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | The latest Juno firmware stores the files in NOR flash as "norkern" for kernel binary, "board.dtb" for the device tree binary. The "old" firmware used the name "Image" for the kernel binary and "juno" for the device tree binary. Rather than just change the default U-Boot configuration to use the new names, breaking users with the old firmware, attempt to load the default filename first. If that fails, attempt to load the alternate filename. I've echo'd that we are loading the alternate file to counter the output from "afs load" shown if the first load attempt fails. For example, I see output like this on my Juno board when it's configured the with the "old" firmware: image "norkern" not found in flash Loading Image instead of norkern loaded region 0 from 08500000 to 80000000, 00AB6318 bytes image "board.dtb" not found in flash Loading juno instead of board.dtb loaded region 0 from 0A000000 to 83000000, 00003188 bytes Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* vexpress64: juno: add optional initrdRyan Harkin2015-10-11-1/+8
| | | | | | | | | | | Some OS images require an initrd on Juno. If the file ramdisk.img exists in NOR flash, then we load it and pass the address to the kernel. Otherwise, we pass the "-" parameter as before. Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* common/armflash: load_image returns success or failureRyan Harkin2015-10-11-5/+6
| | | | | | | | | | | | | | | | Change the load_image so that it returns success or failure of the command (using CMD_RET_SUCCESS or CMD_RET_FAILURE). This way, hush scripts can optionally load different files depending upon the system configuration. A simple example: if afs load ${kernel_name} ${kernel_addr}; then echo loaded; else echo \ not loaded; fi Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* common/armflash: add command to check if image existsRyan Harkin2015-10-11-1/+21
| | | | | | | | | | | | | | | | Add a command to the ARM flash support to check if an image exists or not. If the image is found, it will return CMD_RET_SUCCESS, else CMD_RET_FAILURE. This allows hush scripts to conditionally load images. A simple example: if afs exists ${kernel_name}; then echo found; else echo \ not found; fi Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* vexpress64: juno: add androidboot.hardware=junoRyan Harkin2015-10-11-0/+1
| | | | | | | | | | | Linaro's Juno Android builds requires the androidboot.hardware parameter be set to a know board name. Non-Android kernels ignore this extra parameter because they don't contain code to parse it. Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* vexpress64: fvp dram: add DRAM configurationRyan Harkin2015-10-11-3/+57
| | | | | | | | | | | | | | | | | | | | Create an additional FVP configuration to boot images pre-loaded into DRAM. Sometimes it's preferential to boot the model by loading the files directly into DRAM via model parameters, rather than using SemiHosting. An example of model parmaters that are used to pre-load the files into DRAM: --data cluster0.cpu0=Image@0x80080000 \ --data cluster0.cpu0=fvp-base-gicv2-psci.dtb@0x83000000 \ --data cluster0.cpu0=uInitrd@0x84000000 Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> [trini: Update board/armltd/vexpress64/Kconfig logic] Signed-off-by: Tom Rini <trini@konsulko.com>
* vexpress64: increase max gunzip sizeRyan Harkin2015-10-11-0/+2
| | | | | | | | | | | | vexpress64 kernels are usually over 8 MBytes in length, so setting the max uImage length to 64 Mbytes should give us plenty of scope for expansion. I mostly chose this length to match other board configs that use "(64 << 20)". Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* vexpress64: Kconfig: tidy upRyan Harkin2015-10-11-14/+1
| | | | | | | | | | The FVP and Juno settings were identical, but duplicated, so I removed the duplication with this patch. Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> [trini: Adjust logic to keep if/endif in the file] Signed-off-by: Tom Rini <trini@konsulko.com>
* vexpress64: fix checkpatch warningsRyan Harkin2015-10-11-2/+4
| | | | | | | This patch fixes a couple of checkpatch warnings on the vexpress64 config. Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* configs: ls1021atwr: Enable DSPI for LS1021ATWRYao Yuan2015-10-11-1/+5
| | | | | | | DSPI2 can be verified when boot from QSPI now. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* mtd: sf: Add support AT26DF081A chipYao Yuan2015-10-11-0/+1
| | | | | | | | AT26DF081A is the spi flash type of TWR-MEM(SCH-26248) card. We can access the flash through DSPI2 on LS1021ATWR board. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* dm: dts: ls1021a-twr: Enable DSPI2 on LS1021ATWRYuan Yao2015-10-11-0/+16
| | | | | | | | | Erratum A-008022 has been fixed on LS1021A Rev2.0. So we can use DSPI2 now, this patch enable DSPI2 in dts for LS1021ATWR. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: tegra20: Add support for mode selectionMirza Krak2015-10-11-0/+21
| | | | | | | Respect the mode passed in set_mode ops. Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: zynq_spi: Fix to configure CPOL, CPHA maskJagan Teki2015-10-11-3/+4
| | | | | | | | | | | | | priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: xilinx_spi: Fix to configure CPOL, CPHA maskJagan Teki2015-10-11-5/+5
| | | | | | | | | | | | | priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki <jteki@openedev.com>
* sunxi: Fix USB regulators in Linksprite_pcDuino_defconfigSiarhei Siamashka2015-10-10-0/+2
| | | | | | | | | | | | | | | | | | | | | | The pcDuino1 board unconditionally provides 5V to USB host receptacles. The pcDuino2 board has a voltage regulator, controlled by the PD2 pin which is pulled-up by default (so that the USB power is also enabled by default). Not specifying pins for enabling USB power in the defconfig means that the PH3 and PH6 pins are driven high by default. The PH6 pin is available on the Arduino-compatible expansion header and touching it is not nice (this may be even dangerous, depending on what kind of role is assigned to this particular pin by various Arduino shields). This patch explicitly configures the USB VBUS pins to "", which means that no pins should be touched. The patch has been tested on a pcDuino2 board and USB still works. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Fix pcDuino reliability by downclocking DRAM to 360MHzSiarhei Siamashka2015-10-10-1/+0
| | | | | | | | | | | | | | | | | Linksprite_pcDuino_defconfig is a generic config for pcDuino1 and pcDuino2 boards. The pcDuino2 board exists at least in two variants (with DDR3 chips from HYNIX or NANYA). At least one pcDuino2 board with HYNIX DDR3 fails the lima-memtester reliability test unless the DRAM clock speed is reduced to 360MHz. A detailed analysis report, generated by the a10-tpr3-scan tool with the explanations why the DRAM is failing at 408MHz, is available at: http://linux-sunxi.org/index.php?title=User:Ssvb/pcDuino2_with_HYNIX_DDR3_reliability_test&oldid=15152 http://web.archive.org/web/20151008190210/http://linux-sunxi.org/User:Ssvb/pcDuino2_with_HYNIX_DDR3_reliability_test Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-10-09-0/+1
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| * pci: Fix expansion ROM programming for multi-function devicesBin Meng2015-10-08-0/+1
| | | | | | | | | | | | | | | | | | PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator for multi-function devices. We should mask it off before using it as the header type. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-arcTom Rini2015-10-08-1/+1
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| * | board: axs10x - cap max SDIO clock value to bus/2Alexey Brodkin2015-10-07-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turned out with some boards (FPGA firmwares?) and cards combos current clock settings doesn't work as expected leading to strange card freezes or corrupted data being read from the card. Especially this was seen with Transcend 2Gb cards shipped as a part of ARC SDP: ----------------->8--------------- AXS# mmcinfo Device: Synopsys Mobile storage Manufacturer ID: 74 OEM: 4a60 Name: SDC Tran Speed: 50000000 Rd Block Len: 512 SD version 3.0 High Capacity: No Capacity: 1.8 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes AXS# fatload mmc 0 ** Unrecognized filesystem type ** ----------------->8--------------- With this change that problem is fixed. Note "Tran Speed" above doesn't match clock value set in DW MMC. It is max value for card's speed class. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2015-10-08-4/+17
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| * | sandbox: Correct operaion of 'reset' commandSimon Glass2015-10-05-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently 'reset' only works with the test device tree. When run without a device tree, or with the normal device tree, the following error is displayed: Reset not supported on this platform Fix the driver and the standard device tree to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
| * | dm: test: Show the amount of leaked memory on errorSimon Glass2015-10-05-1/+6
| | | | | | | | | | | | | | | | | | | | | Adjust the memory leak tests to show the amount of memory leaked. This can be a useful signal as to what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Don't use pinctrl for the root deviceSimon Glass2015-10-05-2/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when driver model starts up it finds the root uclass and the pinctrl uclass. This is because even the root node handles pinctrl processing. But this is not useful. The root node is not a real hardware device so cannot require any particular pinmux settings. Also it means that the memory leak tests fails, since they end up freeing more memory than they allocate: the marker it set after the root device and pinctrl uclass are allocated, and later once the pinctrl uclass is freed the memory used by driver model is less than when the marker was set. If a platform needs 'core' pin mulitplex settings it can do this with a driver that is probed on start-up. It would be an abuse of the root node to use this for pinctrl. To avoid this problem, only process pinctrl settings for non-root nodes. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Reconfigure the malloc based to point to system memorySjoerd Simons2015-10-03-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When malloc_base initially gets setup in the SPL it is based on the current (early) stack pointer, which for rockchip is pointing into SRAM. This means simple memory allocations happen in SRAM space, which is somewhat unfortunate. Specifically a bounce buffer for the mmc allocated in SRAM space seems to cause the mmc engine to stall/fail causing timeouts and a failure to load the main u-boot image. To resolve this, reconfigure the malloc_base to start at the relocated stack pointer after DRAM has been setup. For reference, things did work fine on rockchip before 596380db was merged to fix memalign_simple due to a combination of rockchip SDRAM starting at address 0 and the dw_mmc driver not checking errors from bounce_buffer_start. As a result, when a bounce buffer needed to be allocated mem_align simple would fail and return NULL. The mmc driver ignored the error and happily continued with the bounce buffer address being set to 0, which just happened to work fine.. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Simon Glass <sjg@chromium.org>
* | serial: rockchip: make ROCKCHIP_SERIAL depend on ARCH_ROCKCHIPMasahiro Yamada2015-10-03-1/+1
|/ | | | | | | It looks like this line was copy-pasted, but not modified. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-fdtTom Rini2015-10-03-17/+26
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| * trats: fdt: disable unused DW MMCPrzemyslaw Marczak2015-10-03-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This device uses SDHCI driver, for eMMC and SD cards. Trying bind the DW MMC driver with fdt node without all required properties, causes printing an error. This commit disables the DW MMC node. Tested-on: Trats Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Łukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * mach-exynos: clock: restore calling dead exynos4_get_mmc_clk()Przemyslaw Marczak2015-10-03-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After rework of code by: commit: d952796 Exynos5: Use clock_get_periph_rate generic API function get_mmc_clk() always returns -1 for Exynos 4. This was caused by omitting, that SDHCI driver for Exynos 4, calls get_mmc_clk(), with mmc device number as argument, instead of pinmux peripheral id, like DW MMC driver for Exynos 5. By this commit, the code directly calls a proper function to get mmc clock for Exynos 4, without checking the peripheral id. Tested on: Odroid U3/X2, Trats, Trats2, Odroid XU3, Snow (by Simon). Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * gpio: s5p: call: dev_get_addr() instead of fdtdec_get_addr()Przemyslaw Marczak2015-10-03-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After rework in lib/fdtdec.c, the function fdtdec_get_addr() doesn't work for nodes with #size-cells property set to 0. To get GPIO's 'reg' property, the code should use one of: fdtdec_get_addr_size_auto_no/parent() function. Fortunately dm core provides a function to get the property. This commit reworks function gpio_exynos_bind(), to properly use dev_get_addr() for GPIO device. This prevents setting a wrong base register for Exynos GPIOs. Tested on: Odroid U3/X2, Trats, Trats2, Odroid XU3, Snow (by Simon). Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * fdtdec: fix parsing 'reg' property with zero value in '#size-cells'Przemyslaw Marczak2015-10-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After rework of lib/fdtdec.c by: commit: 02464e3 fdt: add new fdt address parsing functions the function fdtdec_get_addr() doesn't work as previous, because the implementation assumes that properties '#address-cells' and '#size-cells' are equal to 1, which can be not true sometimes. The new API introduced fdtdec_get_addr_size_auto_parent() for the 'reg' property parsing, but the implementation assumes, that #size-cells can't be less than 1. This causes that the following children's 'reg' property can't be reached: parent@0x0 { #address-cells = <1>; #size-cells = <0>; children@0x100 { reg = < 0x100 >; }; }; Change the condition value from '1' to '0', which allows parsing property with at least zero #size-cells, fixes the issue. Now, fdtdec_get_addr_size_auto_parent() works properly. Tested on: Odroid U3/X2, Trats, Trats2, Odroid XU3, Snow (by Simon). Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
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