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* arm: am335x: siemens board use in DFU mode fullspeed onlyHeiko Schocher2014-10-06-1/+1
| | | | | | | | | | | | Siemens boards are now using DFU in fullspeed only. For this CONFIG_USB_GADGET_DUALSPEED is undefined. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Liu Bin <b-liu@ti.com> Cc: Lukas Stockmann <lukas.stockmann@siemens.com>
* usb: dfu: add fullspeed support for DFUHeiko Schocher2014-10-06-0/+3
| | | | | | | | | | | DFU now can use also fullspeed. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Liu Bin <b-liu@ti.com> Cc: Lukas Stockmann <lukas.stockmann@siemens.com>
* usb: dfu: thor: gadget: Remove dead codeLukasz Majewski2014-10-06-18/+0
| | | | | | | This code is not used anymore in the current DFU implementation and can be safely removed. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
* usb: kbd: Allow "usb reset" to continue when an usb kbd is usedHans de Goede2014-10-06-7/+7
| | | | | | | | Use the new force parameter to make the stdio_deregister succeed, replacing stdin with a nulldev, and assume that the usb keyboard will come back after the reset. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* stdio: Add force parameter to stdio_deregisterHans de Goede2014-10-06-7/+14
| | | | | | | In some cases we really want to move forward with a deregister, add a force parameter to allow this, and replace the dev with a nulldev in this case. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* usb: kbd: Remove check for already being registeredHans de Goede2014-10-06-11/+1
| | | | | | | We now always properly deregister the keyboard before calling drv_usb_kbd_init(), so we can drop the check for already being registered. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* usb: kbd: On a "usb reset" call usb_kbd_deregister() before calling usb_stop()Hans de Goede2014-10-06-12/+15
| | | | | | | | | | | | | | | | | | | | | We need to call usb_kbd_deregister() before calling usb_stop(). usbkbd's stdio_dev->priv points to the usb_device, and usb_kbd_testc dereferences usb_device->privptr. usb_stop zeros usb_device, leaving usb_device->privptr NULL, causing bad things (tm) to happen once control returns to the main loop and usb_kbd_testc gets called. Calling usb_kbd_deregister() avoids this. Note that we do not allow the "usb reset" to continue when the deregister fails. This will be fixed in a later patch. For the same reasons always fail "usb stop" if the usb_kbd_deregister() fails, even in the force path. This can happen when CONFIG_SYS_STDIO_DEREGISTER is not set. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* usb: kbd: Do not treat -ENODEV as an error for usb_kbd_deregisterHans de Goede2014-10-06-1/+6
| | | | | | | ENODEV menas no usb keyboard was registered, threat this as a successful usb_kbd_deregister. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* usb: kbd: Fix unaligned buffer usage in usb_kbd_setled()Hans de Goede2014-10-06-2/+3
| | | | Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* usb: ehci: Make periodic_schedules a per controller variableHans de Goede2014-10-06-5/+5
| | | | | | | | Periodic schedules tracks how many int_queue-s are active, and decides whether or not to en/disable the periodic schedule based on this. This is clearly a per controller thing. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* usb: ehci: poll_int_queue check real qtd, not the overlayHans de Goede2014-10-06-8/+10
| | | | | | | | | | | | | | | When we first start an int queue, the qh's overlay area is all zeros. This gets filled by the hc with the actual qtd values as soon as it advances the queue, but we may call poll_int_queue before then, in which case we would think the transfer has completed as the hc has not yet copied the qt_token to the overlay, so the active flag is not set. This fixes this by checking the actual qtd token, rather then the overlay. This also fixes a (theoretical) race where we see the completion in the overlay and free and re-use the qtd before the hc has completed writing back the overlay to the actual qtd. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* usb: ehci: Add missing cache flush to destroy_int_queueHans de Goede2014-10-06-0/+2
| | | | Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* usb: ehci: Properly set hub devnum and portnr with usb-1 hubs in the chainHans de Goede2014-10-06-8/+28
| | | | | | | | For full / low speed devices we need to get the devnum and portnr of the tt, so of the first upstream usb-2 hub, not of the parent device (which may be a usb-1 hub). Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* dw_mmc: cleanupsPavel Machek2014-10-03-11/+13
| | | | | | | | | dw_mmc driver was responding to errors with debug(). Change that to prinf so that any errors are immediately obvious. Also adjust english in comments. Signed-off-by: Pavel Machek <pavel@denx.de> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* cmd_mmc: fix bootpart-resize maxarg to 4Wally Yeh2014-10-03-1/+1
| | | | | | | | | | | | | | | sub-command 'bootpart-resize' check for argc == 4, it will retrun CMD_RET_FAILURE when argc value not matched. but bootpart-resize's maxarg is 3, which means you never execute this sub-command successfully. fix it by change bootpart-resize maxarg to 4. Signed-off-by: wally.yeh <wally.yeh@atrustcorp.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pierre Aubert <p.aubert@staubli.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: Fix mmc bus widthMario Schuknecht2014-10-03-2/+3
| | | | | | | | | | | | | After setting the bus width, the extended CSD register is read. Some selected fields are compared with previously read extended CSD register fields. In this comparison the EXT_CSD_ERASE_GROUP_DEF field is compared. But this field is previously written under certain circumstances. And then the comparison fails. Only compare read-only fields. Therefore compare field EXT_CSD_HC_WP_GRP_SIZE instead of field EXT_CSD_ERASE_GROUP_DEF. Signed-off-by: Mario Schuknecht <mario.schuknecht@dresearch-fe.de> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mvebu_mmc: Driver additionMario Schuknecht2014-10-03-1/+61
| | | | | | | | | | | | | | | | In function mvebu_mmc_write notice command timeout. It is possible that a command is done, but a timeout occurred. Enable timeout in set bus function. Set window registers. Without that I could not use the driver on a Kirkwood 88F6282 SoC. Set high capacity and 52MHz driver feature. Signed-off-by: Mario Schuknecht <mario.schuknecht@dresearch-fe.de> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* env_mmc: correct fini partition to match init partitionPeter Bigot2014-10-03-1/+1
| | | | | | | | | | | The code to set the MMC partition uses an weak function to obtain the correct partition number. Use that instead of the compile-time default when deciding whether it needs to switch back. Fixes: 6e7b7df4df43574 ("env_mmc: support env partition setup in runtime") Signed-off-by: Peter A. Bigot <pab@pabigot.com> Acked-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: restore capacity when switching to partition 0Peter Bigot2014-10-03-3/+8
| | | | | | | | | | | | | The capacity and lba for an MMC device with part_num 0 reflects the whole device. When mmc_switch_part() successfully switches to a partition, the capacity is changed to that partition. As partition 0 does not physically exist, attempts to switch back to the whole device will indicate an error, but the capacity setting for the whole device must still be restored to match the partition. Signed-off-by: Peter A. Bigot <pab@pabigot.com> Tested-by: Tom Rini <trini@ti.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: fix ERASE_GRP_DEF handlingHannes Petermaier2014-10-03-0/+2
| | | | | | | | | | | if we set manually this bit on the eMMC card using mmc_switch(...), we also have to set it within our (before read) internal structure 'ext_csd'. Otherwise following checks on this will fail. Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
* mmc: set correct block size value in bfin sdh driverSonic Zhang2014-10-03-3/+4
| | | | | | | | Wait data transfer till the data end bit other than the data block end bit is set. Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* Merge branch 'for-tom' of git://git.denx.de/u-boot-dmTom Rini2014-09-26-110/+89
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| * spi: Add brackets and tidy defines in spi.hSimon Glass2014-09-26-12/+12
| | | | | | | | | | | | | | | | Some of the #defines in spi.h are not bracketed. To avoid future mistakes add brackets. Also add an explanatory comment for SPI_CONN_DUAL_... Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * dm: spi: Move cmd device code into its own functionSimon Glass2014-09-26-21/+32
| | | | | | | | | | | | | | | | In preparation for changing the error handling in this code for driver model, move it into its own function. Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: config: Enable all SPI flash chipsSimon Glass2014-09-26-1/+7
| | | | | | | | | | | | | | | | | | Sandbox may as well support everything. This increases the amount of code that is built/tested by sandbox, and also provides access to all the supported SPI flash devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sandbox: Convert SPI flash emulation to use sf_paramsSimon Glass2014-09-26-76/+38
| | | | | | | | | | | | | | | | | | | | | | At present sandbox has its own table of supported SPI flash chips. Now that the SPI flash system is fully consolidated and has its own list, sandbox should use that. This enables us to expand the number of chips that sandbox supports. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-09-26-251/+1018
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| * | board/ls1021aqds: Add DDR4 supportYork Sun2014-09-25-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig for this variant to enable DDR4 support. RAW timing parameters are not added for DDR4. The board timing parameters are only tuned for single- rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM availability. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com>
| * | driver/ddr/fsl: Fix DDR4 driverYork Sun2014-09-25-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins are not actually connected. Also fix a bug when reading from DDR register to use proper accessor for correct endianess. Signed-off-by: York Sun <yorksun@freescale.com>
| * | ARMv8/ls2085a: Move u-boot location to make room for RCWYork Sun2014-09-25-1/+1
| | | | | | | | | | | | | | | | | | When booting with SP, RCW resides at the beginning of IFC NOR flash. Signed-off-by: York Sun <yorksun@freescale.com>
| * | ARMv8/ls2085a: Enable secondary coresYork Sun2014-09-25-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Spin table is at the very beginning of boot code. Each core has an individual release address within the spin table, the ft_cpu_setup fn updates the "cpu-release-addr" property of each cpu node with the corresponding release address. Also fix CPU_RELEASE_ADDR to point to secondary_boot_func. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
| * | armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot PageYork Sun2014-09-25-89/+518
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
| * | fdt_support: Make of_bus_default_count_cells non staticArnab Basu2014-09-25-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_bus_default_count_cells can be used to get the #address-cells and #size-cells defined by the current node's parent node. This is required when using of_read_number to read from FDT nodes that can be 32 or 64 bytes depending on values defined by the parent. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> CC: Scott Wood <scottwood@freescale.com>
| * | fdt_support: Move of_read_number to fdt_support.hArnab Basu2014-09-25-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is being done so that it can be used outside 'fdt_support.c'. Making life more convenient when reading device node properties that can be 32 or 64 bits long. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Cc: Scott Wood <scottwood@freescale.com>
| * | driver/ddr/fsl: Fix tXP and tCKEYork Sun2014-09-25-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | The driver was written using old DDR3 spec which only covers low speeds. The value would be suboptimal for higher speeds. Fix both timing according to latest DDR3 spec, remove tCKE as an config option. Signed-off-by: York Sun <yorksun@freescale.com>
| * | ARMv8/ls2085a_emu: Enable DP-DDR as standalone memory blockYork Sun2014-09-25-5/+89
| | | | | | | | | | | | | | | | | | | | | DP-DDR is used for DPAA, separated from main memory pool for general use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit). Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/ddr: Restruct driver to allow standalone memory spaceYork Sun2014-09-25-108/+238
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-boot has been initializing DDR for the main memory. The presumption is the memory stays as a big continuous block, either linear or interleaved. This change is to support putting some DDR controllers to separated space without counting into main memory. The standalone memory controller could use different number of DIMM slots. Signed-off-by: York Sun <yorksun@freescale.com>
| * | board/ls2085a: Add support of NOR and NAND flash for simulatorPrabhakar Kushwaha2014-09-25-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of NOR and NAND flash for simulator target. Here IFC - CS0: NOR flash IFC - CS1: NAND flash Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver/mtd: Use generic timer API for FSL IFC, eLBCPrabhakar Kushwaha2014-09-25-15/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's flash control driver is using architecture specific timer API i.e. usec2ticks Replace usec2ticks with get_timer() (generic timer API) Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | board/ls2085a: Update env_addr after NOR flash relocationPrabhakar Kushwaha2014-09-24-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2085a has 2 regions in system memory map. Region1 is default map from where system boots. Once u-boot is moved to DDR, IFC is re-mapped to Region2. So, update gd->env_addr to reflect correct address. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-09-26-39/+82
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| * | powerpc: add --bss-plt to LDFLAGSChris Packham2014-09-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With some versions of gcc (that we know of 4.6.3 and 4.8.2 are affected) it is necessary to specify --bss-plt to get the final blrl in the _GOT2_TABLE_. Without this the last symbol does not get it's address relocated. For the P2041RDB board this ended up being NetArpWaitTimerStart which caused the ARP packets to timeout immediately. Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se> Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joakim Tjernlund <joakim.tjernlund@transmode.se> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | board/t1040qds: Add sgmii ports support in 0xA7 protocolPriyanka Jain2014-09-24-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1042QDS (T1042 is T1040 Personality without L2 switch) supports following sgmii interfaces with serdes protocol 0xA7 -SGMII-MAC3 on Lane B - slot 7 -SGMII-MAC5 on Lane H - slot 7 -SGMII2.5G-MAC1 on Lane C - slot 6 -SGMII2.5G-MAC2 on Lane D - slot 5 Add support of above sgmii interfaces Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
| * | powerpc/t104xrdb: Set DDR ODT to 75ohmPriyanka Jain2014-09-24-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR-ODT require cfg_dram_type switch set properly as per DDR type. T1040RDB, T1042RDB boards have DDR3L type DDR, so cfg_dram_type should be set to OFF for DDR3L Update t104xrdb/README for switch setting Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/mpc85xx: Serdes protocol "00" is supportedEbony Zhu2014-09-24-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | "0x00" is a valid serdes protocol for QorIQ parts, and can not be used to test whether the serdes is enabled or disabled. Signed-off-by: Ebony Zhu <b45385@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | B4860QDS: Enable mac command supportShaveta Leekha2014-09-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | One of the I2C EEPROM is used to store/save and edit mac addresses of ports. this patch add required CONFIG to support the same Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
| * | powerpc/b4860: Updated default hwconfig to enable only cpc2Shaveta Leekha2014-09-24-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPC1 is not being enabled by default as powerpc is supposed to use only CPC2. Though by editing hwconfig en_cpc option, CPC1 can also be enabled. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/8xxx: Fix in USB device-tree fixupramneek mehresh2014-09-24-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix following issues in USB device-tree fixup: - returns when either dr_mode or phy_type not defined. This was terminating fix-up when only either property was defined in hwconfig string - updates dr_mode_type or dr_phy_type with junk value when their index is -1. Now these are updated only when their respective index is pointing to relevant types in modes[] and phys[] array - dr_mode_type and dr_phy_type were not NULL for each controller Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/t104xrdb: Add T1042RDB board supportvijay rai2014-09-24-10/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1042RDB is a Freescale reference board that hosts the T1042 SoC (and variants). The board is similar to T1040RDB, T1042 is a reduced personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch). T1042RDB is configured with serdes protocol 0x86 which can support following interfaces - 2 RGMII's on DTSEC4, DTSEC5 - 1 SGMII on DTSEC3 DTSEC1, DTSEC2 are not connected on board. This Patch - add T1042RDB support - updates README file for T1042RDB details and update commands for switching to alternate banks from vBank0 to vBank4 and vice versa This patch also does minor clean ups for fdt defines for T1042RDB and T1042RDB_PI board Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/t104xrdb: Add Support of rcw for T1042RDB in u-bootvijay rai2014-09-24-4/+14
| |/ | | | | | | | | | | | | | | | | | | | | | | This patch adds support of rcw for T1042RDB, it makes following changes : - Adds t1042_rcw.cfg file for serdes protocol 0x86 for T1042RDB - Renames t1042_pi_rcw.cfg file from t1042_rcw.cfg and also updates comments for valid serdes protocol which is 0x06 - Also updates CONFIG_SYS_FSL_PBL_RCW for T1042RDB Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-09-17 18:10:19 +0000