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| * armv8: Enable CPUECTLR.SMPEN for coherencyMingkai Hu2017-01-18-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is set. The SMPEN bit should be set before enabling the data cache. If not enabled, the cache is not coherent with other cores and data corruption could occur. For A57/A72, SMPEN bit enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster. This bit should be set before enabling the caches and MMU, or performing any cache and TLB maintenance operations. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: layerscape: Enable UUID & GPT partition for NXP's ARM SoCPrabhakar Kushwaha2017-01-18-0/+44
| | | | | | | | | | | | | | | | | | | | Enable UUID and GPT partition support for NXP's ARM based SoCs i.e. LS1012A, LS1021A, LS1043A, LS1046A and LS2080A. Also enable DOS partition for LS1012AFRDM boards. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1012: Enable CONFIG_DM_USB in defconfigsTang Yuantian2017-01-18-0/+3
| | | | | | | | | | | | | | | | Enables driver model flag CONFIG_DM_USB for LS1012A platform in defconfigs. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1012: added usb nodes in dtsTang Yuantian2017-01-18-0/+15
| | | | | | | | | | | | | | | | | | | | The LS1012A processor has two integrated USB controllers. One is USB2.0 controller, the other is USB3.0 controller that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl_lsch2: Add the OCRAM initializationHou Zhiqiang2017-01-18-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Clear the content to zero and the ECC error bit of OCRAM1/2. The OCRAM must be initialized to ZERO by the unit of 8-Byte before accessing it, or else it will generate ECC error. And the IBR has accessed the OCRAM before this initialization, so the ECC error status bit should to be cleared. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv8/fsl-layerscape: Correct the OCRAM sizeHou Zhiqiang2017-01-18-7/+9
| | | | | | | | | | | | | | | | | | The real size of OCRAM is 128KiB, so correct the size of OCRAM. And OCRAM reserved 2MiB space, then add a new macro to describe it, which is used for MMU setup. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * kconfig: move FSL_PCIE_COMPAT to platform KconfigHou Zhiqiang2017-01-18-12/+23
| | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * pci: layerscape: remove unnecessary legacy codeMinghuan Lian2017-01-18-716/+1
| | | | | | | | | | | | | | | | | | | | All Layerscape SoCs have supported new PCIe driver based on DM. The lagecy PCIe driver code is unused and can be removed. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: Enable PCIe in defconfigsMinghuan Lian2017-01-18-39/+28
| | | | | | | | | | | | | | | | | | The patch enables PCIe in ls2080a defconfigs and removes unused PCIe related macro defines. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046a: Enable PCIe and E1000 in defconfigsMinghuan Lian2017-01-18-0/+48
| | | | | | | | | | | | | | | | The patch enables PCIe and E1000 in ls1046a related defconfigs. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1043a: Enable PCIe and E1000 in defconfigsMinghuan Lian2017-01-18-28/+66
| | | | | | | | | | | | | | | | | | The patch enables PCIe and E1000 in ls1043a defconfigs and removes unused PCIe related macro defines. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: ls1012a: Enable PCIe and E1000 in defconfigsMinghuan Lian2017-01-18-34/+13
| | | | | | | | | | | | | | | | | | The patch enables PCIe and E1000 in ls1012a defconfigs and removes unused PCIe related macro defines Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: ls1021a: Enable PCIe in defconfigsMinghuan Lian2017-01-18-67/+72
| | | | | | | | | | | | | | | | | | The patch enables PCIe in ls1021a defconfigs and removes unused PCIe related macro defines. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * pci: layerscape: add pci driver based on DMMinghuan Lian2017-01-18-0/+754
| | | | | | | | | | | | | | | | | | | | | | | | | | There are more than five kinds of Layerscape SoCs. unfortunately, PCIe controller of each SoC is a little bit different. In order to avoid too many macro definitions, the patch addes a new implementation of PCIe driver based on DM. PCIe dts node is used to describe the difference. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * pci: layerscape: move kernel DT fixup to a separate fileHou Zhiqiang2017-01-18-311/+343
| | | | | | | | | | | | | | | | | | To make the layerscape pcie driver clear, move the kernel DT fixup code from pcie_layerscape.c to pcie_layerscape_fixup.c. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: add PCIe dts nodeMinghuan Lian2017-01-18-0/+60
| | | | | | | | | | | | Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046a: add PCIe dts nodeMinghuan Lian2017-01-18-0/+49
| | | | | | | | | | | | Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1043a: add PCIe dts nodeMinghuan Lian2017-01-18-0/+46
| | | | | | | | | | | | Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: ls1012a: add PCIe dts nodeMinghuan Lian2017-01-18-0/+15
| | | | | | | | | | | | Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: ls1021a: add PCIe dts nodeMinghuan Lian2017-01-18-0/+31
| | | | | | | | | | | | Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * dm: pci: remove pci_bus_to_hose(0) callingMinghuan Lian2017-01-18-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There may be multiple PCIe controllers in a SoC. It is not correct that always calling pci_bus_to_hose(0) to get the first PCIe controller for the PCIe device connected other controllers. We just remove this calling because hose always point the correct PCIe controller. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * dm: pci: return the real controller in pci_bus_to_hose()Minghuan Lian2017-01-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | for the legacy PCI driver, the function pci_bus_to_hose() returns the real PCIe controller. To keep consistency, this function is changed to return the PCIe controller pointer of the root bus instead of the current PCIe bus. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * configs: ls1021a: enable DT and DM supportHou Zhiqiang2017-01-18-0/+12
| | | | | | | | | | | | | | | | Enable DT to support Driver Model. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/layerscape: remove unnecessary function declaresMinghuan Lian2017-01-18-4/+0
| | | | | | | | | | | | | | | | | | For the function alloc_stream_ids() append_mmu_masters() and fdt_fixup_smmu_pcie() there are no related definitions and they are never called. So the patch removes the unnecessary declares. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape, ccn504: Set forced-order mode in RNI-6, RNI-20Priyanka Jain2017-01-18-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | It is recommended to set forced-order mode in RNI-6, RNI-20 for performance optimization in LS2088A. Both LS2080A, LS2088A families has CONFIG_LS2080A define. As above update is required only for LS2088A, skip this for LS2080A SoC family. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl/usb: enable usb feature for ls1046ardbjerry.huang@nxp.com2017-01-18-1/+13
| | | | | | | | | | | | | | Enable usb feature for ls1046ardb Signed-off-by: Changming Huang <jerry.huang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2017-01-18-63/+149
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| * | i2c: i2c-cdns: No need for dedicated probe functionMoritz Fischer2017-01-18-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The generic probe code in dm works, so get rid of the leftover cruft. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Heiko Schocher <hs@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: u-boot@lists.denx.de
| * | i2c: i2c-cdns: Implement workaround for hold quirk of the rev 1.0Moritz Fischer2017-01-18-30/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revision 1.0 of this IP has a quirk where if during a long read transfer the transfer_size register will go to 0, the master will send a NACK to the slave prematurely. The way to work around this is to reprogram the transfer_size register mid-transfer when the only the receive fifo is known full, i.e. the I2C bus is known non-active. The workaround is based on the implementation in the linux-kernel. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Heiko Schocher <hs@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: u-boot@lists.denx.de
| * | i2c: i2c-cdns: Reorder timeout loop for interrupt waitingMoritz Fischer2017-01-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reorder the timeout loop such that we first check if the condition is already true, and then call udelay() so if the condition is already true, break early. Reviewed-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Heiko Schocher <hs@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: u-boot@lists.denx.de
| * | i2c: i2c-cdns: Detect unsupported sequences for rev 1.0Moritz Fischer2017-01-18-14/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revision 1.0 of this IP has a couple of issues, such as not supporting repeated start conditions for read transfers. So scan through the list of i2c messages for these conditions and report an error if they are attempted. This has been fixed for revision 1.4 of the IP, so only report the error when the IP can really not do it. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Heiko Schocher <hs@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: u-boot@lists.denx.de
| * | i2c: mux: Allow muxes to work as children of i2c bus without i2c-parentMoritz Fischer2017-01-18-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For mux check if the parent is already a device of UCLASS_I2C and if yes just use that. Otherwise see if someone specified an i2c-parent phandle. This mimics the behavior found in the Kernel, as it removes the requirement to explicitly specify a i2c-parent phandle. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Cc: Heiko Schocher <hs@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: u-boot@lists.denx.de
* | | Merge git://git.denx.de/u-boot-samsungTom Rini2017-01-18-134/+338
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| * | exynos: video: Enable stdout env var backward compatibility for LCDJavier Martinez Canillas2017-01-18-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit bb5930d5c97f ("exynos: video: Convert several boards to driver model for video") converted the Exynos Chromebooks machines to use DM for video, but this breaks backward compatibility with the stdout env var since now stdout is expected to be "vidconsole" instead of "lcd". This causes display to not work when updating u-boot on these boards if the old stdout env var is used. Since these are consumer devices, there's no easy way to have a serial console so users may be confused thinking that u-boot failed to boot, or in the best case will need to update the stdout env var blindly to make the display to work again. There's a CONFIG_VIDCONSOLE_AS_LCD config option to workaround this, so enable it in the Chromebooks' default configuration files to allow users to change their stdout env var before the workaround is removed. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | exynos: Enable XHCI on exynos5250 boardsSjoerd Simons2017-01-18-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Once upon a time u-boot didn't support building with two usb host controller types, these days it does. Enable XHCI in addition to the existing EHCI support so user can plug usb devices in all available ports regardless of the controller type. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | exynos5: Don't potentially undervoltage the CPUSjoerd Simons2017-01-18-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For snow when chainloading u-boot the CPU seems to be running at full speed. The lower CPU voltage seems to be ok for u-boot, but when booting linux (bringing up all cores) I'm seeing random crashes. Bump the voltage up to a level that's safe for all cpu frequencies. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | board: samsung: universal_c210: remove the codes relevant to soft_i2cJaehoon Chung2017-01-18-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removes the codes of soft_i2c. There is no usasge for universal_c210, also didn't define CONFIG_SOFT_I2C_GPIO_SCL. This code seems a dead code. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | i2c: Kconfig: Add SYS_I2C_S3C24X0 entryJaehoon Chung2017-01-18-0/+5
| | | | | | | | | | | | | | | | | | | | | Adding Kconfig for SYS_I2C_S3C24X0. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | i2c: s3c24x0: fix the compiler error for exynos4Jaehoon Chung2017-01-18-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_SYS_I2C_S3C24X0_SLAVE isn't defined, then complie error should be occurred. This patch is for preventing it. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | board: samsung: universal_210: use the driver model for max8998Jaehoon Chung2017-01-18-75/+94
| | | | | | | | | | | | | | | | | | | | | | | | Revmoe the "ifndef CONFIG_DM_I2C". Intead, use the driver model for max8998. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | configs: s5pc210_universal: enable the DM_PMIC and MAX8998Jaehoon Chung2017-01-18-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the CONFIG_DM_PMIC and CONFIG_DM_PMIC_MAX8998. s5pc210_universal board is using max8998 pmic. To use the i2c/pmic driver model, enable these configurations. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | ARM: dts: exnyos4210-universl_c210: add i2c_5 and pmic nodesJaehoon Chung2017-01-18-0/+164
| | | | | | | | | | | | | | | | | | | | | | | | Add the i2c_5 node and pmic as its child node. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | ARM: dts: exynos4: use the node's name for i2cJaehoon Chung2017-01-18-8/+19
| | | | | | | | | | | | | | | | | | | | | Use the node's name for i2c. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | board: samsung: goni: fix the pmic's name for gettingJaehoon Chung2017-01-18-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Getting from uclass, use the "max8998-pmic" as name. It also needs to change the dt-node's name as "max8998-pmic". Otherwise, it doesn't find the pmic device. Because it's only searching for 'max8998_pmic'. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | arm: samsung: goni: use the driver model for max8998Jaehoon Chung2017-01-05-31/+30
| | | | | | | | | | | | | | | | | | | | | | | | Remove the "ifndef CONFIG_DM_I2C". Instead, use the driver model for max8998. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2017-01-17-1056/+739
|\ \ \ | | | | | | | | | | | | | | | | | | | | - Enable eMMC driver for LD11/LD20 SoCs - Refactoring of SoC init code - Bug fix of pinctrl driver
| * | | pinctrl: uniphier: fix Ethernet (RMII) pin-mux setting for LD20Masahiro Yamada2017-01-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the pin-mux values for the MDC, MDIO, MDIO_INTL, PHYRSTL pins. Fixes: fc9da85c6059 ("pinctrl: uniphier: add Ethernet pin-mux settings") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | ARM: uniphier: move SBC and Support Card init code to U-Boot properMasahiro Yamada2017-01-18-27/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize SBC and Support Card in U-Boot proper instead of SPL. We may run different firmware (ex. ARM Trusted Firmware) before U-Boot, and basic SoC initialization may be done there. In that case, SPL may not be used. The motivation for preparing SBC and Support Card in SPL was to use LED for early debugging, but this is not mandatory to boot SoCs. With this commit, LED will be unavailable in SPL, but we can use a debug serial instead. So, this change will not be a big deal. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | ARM: uniphier: refactor spl_init_board()Masahiro Yamada2017-01-18-508/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge init-*.c into a single file using a table of callbacks because the initialization flow is almost common among SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | ARM: uniphier: refactor board_init()Masahiro Yamada2017-01-18-95/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The code here is cluttered due to the switch statement. Introduce a table of callbacks to clean up the initialization code across SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.1 at 2024-08-20 03:17:38 +0000