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* scsi: Change scsi_scan() to be able to return valueMichal Simek2016-12-02-6/+13
| | | | | | | | | | With DM_SCSI this function will return more than one return value to cover errors. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* scsi: Make private functions staticMichal Simek2016-12-02-6/+10
| | | | | | | | | | Several functions should be static because they are not exported to any other file. Warnings were reported by sparse C=1. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* scsi: Remove completely unused functionsMichal Simek2016-12-02-38/+0
| | | | | | | | | | These functions are not called for any location. This patch removes them scsi_trim_trail(), scsi_get_disk_count() and scsi_setup_read6(). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* scsi: Simplify scsi_read/scsi_write()Michal Simek2016-12-02-16/+11
| | | | | | | | | | There is no reason to directly point to static allocated array when we have proper block_dev pointer available via parameter in !CONFIG_BLK. For CONFIG_BLK this is read directly from uclass platdata. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* scsi: Move pccb buffer initalization directly to scsi_detect_devMichal Simek2016-12-02-6/+6
| | | | | | | | pccb is pointer to temporary buffer which is used only for sending command. Make it local as is done in scsi_read/scsi_write. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* scsi: Take lun from device block descriptionMichal Simek2016-12-02-6/+5
| | | | | | | | Prepare LUN(Logical unit number) directly in block description structure and reuse it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* scsi: Extract device detection algorithmMichal Simek2016-12-02-61/+82
| | | | | | | | The patch enables running detection algorithm on block device description structure. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* scsi: Extract block device initializationMichal Simek2016-12-02-20/+25
| | | | | | | Extract block device initialization to specific function. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* common: miiphyutil: Work and report phy address in hex in mdio cmdMichal Simek2016-12-02-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It is confusing that mdio commands work and report phy id as decimal value when mii is working with hex values. For example: ZynqMP> mdio list gem: 21 - TI DP83867 <--> ethernet@ff0e0000 ZynqMP> mdio read ethernet@ff0e0000 0 Reading from bus gem PHY at address 21: 0 - 0x1140 ZynqMP> mii dump 21 0 Incorrect PHY address. Range should be 0-31 ... ZynqMP> mii dump 15 0. (1140) -- PHY control register -- (8000:0000) 0.15 = 0 reset U-Boot normally takes hex values that's why this patch is changing mdio command to handle hex instead of changing mii command to handle decimal values. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* ARM: zynq: Enable SD1 and qspi for picozed boardSiva Durga Prasad Paladugu2016-12-02-0/+12
| | | | | | | Enable SD1 and qspi for picozed board. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq(mp): remove unneeded CONFIG_USB_MAX_CONTROLLER_COUNT definesMasahiro Yamada2016-12-02-2/+0
| | | | | | | | | | ARCH_ZYNQ(MP) selects DM_USB, where CONFIG_USB_MAX_CONTROLLER_COUNT is not used. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: List secondary software boot modesMichal Simek2016-12-02-0/+15
| | | | | | | | Using alternative bootmode field to support automatic secondary boot modes. It is purely software setting where SW modes are using free bootmode combinations. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Use DTS name for different psu_init_gpl* files in SPLMichal Simek2016-12-02-1/+1
| | | | | | | | | | | | | | | CONFIG_SYS_CONFIG_NAME is not proper config option for different low level init files because different board revisions requires different psu_init_gpl* files. Also at the end of moving drivers to DM all board specific configuration files should be removed. The same changes was done for Zynq. "ARM: zynq: Simplify zynq configuration" (sha1: ad5b5801264e573bfbf17a20b04c546985c5bfc1) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Force certain bootmode for SPLMichal Simek2016-12-02-1/+1
| | | | | | | | ZynqMP provides an option to overwrite bootmode setting which can change SPL behavior. For example: boot SPL via JTAG and then SPL loads images from SD. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-12-01-5/+62
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| * tools/kwbimage: add DEBUG optionChris Packham2016-12-01-1/+10
| | | | | | | | | | | | | | | | | | Offset 0x1 in the generated kwb image file is a set of flags, bit 0 enables debug output from the BootROM firmware. Allow a DEBUG option in the kwb configuration to request debug output from the BootROM firmware. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * tools/kwbimage: add BAUDRATE optionChris Packham2016-12-01-1/+44
| | | | | | | | | | | | | | | | | | | | | | | | Offset 0x18 in some Marvell datasheets this field is redacted as "reserved". This offset is actually a set of options and bits 2:0 allow the selection of the UART baudrate. Allow a BAUDRATE option to set the UART baudrate for any messages coming from the BootROM firmware. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: move SYS_MVEBU_PLL_CLOCK to KconfigChris Packham2016-12-01-3/+6
| | | | | | | | | | | | | | | | | | | | The main PLL frequency is 2GHz for Armada-XP and 1GHZ for Armada 375, 38x and 39x. [ Linux commit ae142bd9976532aa5232ab0b00e621690d8bfe6a ] Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mvebu: db-88f6820-amc: Enable FIT supportChris Packham2016-12-01-0/+2
| | | | | | | | | | Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | SPL: mmc: Make spl_mmc_load_image availableMarek Vasut2016-12-01-2/+5
| | | | | | | | | | | | | | | | | | | | Make the spl_mmc_load_image() available globally, so it can be invoked directly by SPL on extremely space-constrained systems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: Tinification of the mmc codeMarek Vasut2016-12-01-2/+83
| | | | | | | | | | | | | | | | | | | | | | | | Add new configuration option CONFIG_MMC_TINY which strips away all memory allocation within the MMC code and code for handling multiple cards. This allows extremely space-constrained SPL code use the MMC framework. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: Fix warning if debug() is not usedMarek Vasut2016-12-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If debug() is not used, then the whole content of debug(...) will be removed by the preprocessor, which will result in the following warning. This patch adds __maybe_unused annotation to fix this. drivers/mmc/mmc.c: In function ‘mmc_init’: drivers/mmc/mmc.c:1685:11: warning: variable ‘start’ set but not used [-Wunused-but-set-variable] unsigned start; Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: add bkops-enable commandTomas Melin2016-12-01-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | Add new command that provides possibility to enable the background operations handshake functionality (BKOPS_EN, EXT_CSD byte [163]) on eMMC devices. This is an optional feature of eMMCs, the setting is write-once. The command must be explicitly taken into use with CONFIG_CMD_BKOPS_ENABLE. Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
* | mmc: s5p_sdhci: fix to check proper pinmux idSeung-Woo Kim2016-12-01-1/+1
|/ | | | | | | At sdhci_get_config(), there was wrong condition to check pimux id, so this patch fixes to check proper pinmux id. Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
* ts4600: Disable CONFIG_DISPLAY_CPUINFOTom Rini2016-11-30-0/+1
| | | | | | | | | | | | Without this change we see: ../arch/arm/cpu/arm926ejs/mxs/mxs.c: In function ‘print_cpuinfo’: ../arch/arm/cpu/arm926ejs/mxs/mxs.c:181:23: warning: unused variable ‘data’ [-Wunused-variable] ../arch/arm/cpu/arm926ejs/mxs/mxs.c:180:6: warning: variable ‘cpurev’ set but not used [-Wunused-but-set-variable] So the easy solution is to disable CONFIG_DISPLAY_CPUINFO Reviewed-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-11-30-65/+584
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| * MIPS: Fix map_physmem for cached mappingsPaul Burton2016-11-30-1/+1
| | | | | | | | | | | | | | | | | | | | map_physmem should return a pointer that can be used by the CPU to access the given memory - on MIPS simply returning the physical address as it does prior to this patch doesn't achieve that. Instead return a pointer to the memory within (c)kseg0, which matches up consistently with the (c)kseg1 pointer that uncached mappings return via ioremap. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Use ram_top, not bi_memsize, in arch_lmb_reservePaul Burton2016-11-30-1/+1
| | | | | | | | | | | | | | | | | | When calculating the region to reserve for the stack in arch_lmb_reserve, make use of ram_top instead of adding bi_memsize to CONFIG_SYS_SDRAM_BASE. This avoids overflow if the system has enough memory to reach the end of the address space. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * mips: Let cache.h be included from assembly sourceMarek Vasut2016-11-30-0/+2
| | | | | | | | | | | | | | | | | | Add ifdef __ASSEMBLY__ around the function prototype to let cache.h be included from assembly code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
| * common/board_f: enable initr_trap for MIPSDaniel Schwierzeck2016-11-30-2/+2
| | | | | | | | | | | | | | | | Enable initr_trap hook also for MIPS to install and enable U-Boot's specific MIPS exception handlers. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * MIPS: add handling for generic and EJTAG exceptionsDaniel Schwierzeck2016-11-30-0/+344
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add exception handlers for generic and EJTAG exceptions. Most of the assembly code is imported from Linux kernel and adapted to U-Boot. The exception vector table will be reserved above the stack before U-Boot is relocated. The exception handlers will be installed and activated after relocation in the initr_traps hook function. Generic exceptions are handled by showing a CPU register dump similar to Linux kernel. For example: malta # md 1 00000001: Ooops: $ 0 : 00000000 00000000 00000009 00000004 $ 4 : 8ff7e108 00000000 0000003a 00000000 $ 8 : 00000008 00000001 8ff7cd18 00000004 $12 : 00000002 00000000 00000005 0000003a $16 : 00000004 00000040 00000001 00000001 $20 : 00000000 8fff53c0 00000008 00000004 $24 : ffffffff 8ffdea44 $28 : 90001650 8ff7cd00 00000004 8ffe6818 Hi : 00000000 Lo : 00000004 epc : 8ffe6848 (text bfc28848) ra : 8ffe6818 (text bfc28818) Status: 00000006 Cause : 00000410 (ExcCode 04) BadVA : 8ff9e928 PrId : 00019300 ### ERROR ### Please RESET the board ### EJTAG exceptions are checked for SDBBP and delegated to the SDBBP handler if necessary. Otherwise the debug mode will simply be exited. The SDBBP handler currently prints the contents of registers c0_depc and c0_debug. This could be extended in the future to handle semi-hosting according to the MIPS UHI specification. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Tested-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: reserve space for exception vectorsDaniel Schwierzeck2016-11-30-0/+20
| | | | | | | | | | | | | | | | | | | | | | In order to set own exception handlers, a table with the exception vectors must be built in DRAM and the CPU EBase register must be set to the base address of this table. Reserve the space above the stack and use gd->irq_sp as storage for the exception base address. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: add asm-offsets for struct pt_regsDaniel Schwierzeck2016-11-30-0/+66
| | | | | | | | | | | | | | Import asm-offsets.c from kernel to generate offset for struct pt_regs needed by exception handlers. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: add possibility to setup initial stack and global data in SRAMDaniel Schwierzeck2016-11-30-0/+18
| | | | | | | | | | | | | | | | | | | | This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which a SoC can select if it supports some kind of SRAM. Together with CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be set up in that SRAM. This can be used to provide a C environment also for lowlevel_init(). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: factor out code for initial stack and global dataDaniel Schwierzeck2016-11-30-26/+30
| | | | | | | | | | | | | | Move the code for setting up the initial stack and global data to a macro to be able to use it more than once. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: fix iand optimize setup of CP0 registersDaniel Schwierzeck2016-11-30-24/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exception. Extend and fix initialization of watch registers. Check if additional watch register sets are implemented and initialize them too. Initialize cp0 count as early as possible to get the most accurate boot timing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: fix ROM exception vectorsDaniel Schwierzeck2016-11-30-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI exception operation which can be read as unhandled exception by a hardware debugger if one is attached. If the debugger doesn't support UHI, the exception is read as unexpected breakpoint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: make inclusion of ROM exception vectors configurableDaniel Schwierzeck2016-11-30-3/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds a compile time option to include code for static exception vectors. Static exception vectors are only needed, when the U-Boot entry point is equal to the CPU reset exception vector address. For instance this is the case when U-Boot is used as ROM in Qemu or booted from parallel NOR flash. When U-Boot is booted from RAM (e.g. loaded there by SPL), the exception vectors need to be setup dynamically, which is done in follow-up commits. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | travis.yml: Split Freescale ARM job up moreTom Rini2016-11-30-2/+5
| | | | | | | | | | | | | | | | | | | | In order to avoid running into the time limit, split the 32bit and 64bit Freescale boards into separate jobs. We could either pass "freescale & armv8" to buildman or exclude all of the 32bit CPUs. While the former is shorter I fear the amount of possible escaping required would make things less readable. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-11-30-157/+2144
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| * imx6: clock: Enable External Memory Interface [EIM] clock (eim_slow_clock)Lukasz Majewski2016-11-30-0/+15
| | | | | | | | | | | | | | | | This patch extends the imx6 clock code to enable or disable the EIM slow clock, which in necessary when one wants to use EIM interface t o read/write from external memory (e.g. NOR). Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
| * mx6sx: Add initial support for Samtec VIN|ING 2000 boardChristoph Fritz2016-11-30-0/+834
| | | | | | | | | | | | | | | | This patch adds initial support for Samtec VIN|ING 2000 board. Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Acked-by: Marek Vasut <marex@denx.de>
| * imx7: SPI: add suport for SPI flash in mikroBUS slotAngus Ainslie2016-11-29-0/+30
| | | | | | | | | | | | | | | | | | | | Enable the escpi3 nets attached to the mikroBUS slot on the i.MX7 Sabre evalution board. Also enble the SPI flash commands to work with the "flash click" board. This is V2 of this patch with changes recommended by the maintainer CC: Jagan Teki <jteki@openedev.com>
| * arm: mx6: specify SPL paddingStefan Agner2016-11-29-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specify standard padding for payload to 68KB. This is derived from the maximum header size plus maximum SPL size. It matches the already defined offset for SD/eMMC devices (69KB) too. This allows to use the u-boot-with-spl.imx build target to generate a directly flashable image which can be flashed using: dd if=u-boot-with-spl.imx of=/dev/mmcblk0 bs=512 skip=2 While the patch has been created with SD/eMMC in mind, this also works with other boot media. The board file needs to configure the media specific (absolute) payload offset accordingly. Especially the IVT offset is boot media specific and can be retrieved from the reference manual (Table 8-25. Image Vector Table Offset and Initial Load Region Size). For NAND boot a define like this should do the job: #define CONFIG_SYS_NAND_U_BOOT_OFFS (SPL_PAD_TO + 0x400) Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * mx6sx: Add initial support for UDOO Neo BoardBreno Lima2016-11-29-0/+595
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UDOO Neo Board is a development board from Seco that has three models: - UDOO Neo Basic - UDOO Neo Basic Kick Starter - UDOO Neo Extended - UDOO Neo Full All versions are based on the i.MX6 SoloX processor. For more details about the UDOO Neo board, please refer to: http://www.udoo.org/udoo-neo/ This work is based on a previous commit of Francesco Montefoschi <francesco.monte@gmail.com>: https://github.com/fmntf/u-boot/commit/877b71184a5105e708024f232d36aed574961844 Only tested on the UDOO Neo Full board. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * colibri_vf: Read kernel and device tree from static UBI volumesSanchayan Maity2016-11-29-3/+3
| | | | | | | | | | | | | | | | Our update scripts write the kernel and device tree in seperate UBI volumes. This allows to use a lot less UBI/UBIFS support in U-Boot, which should lower the risk of hitting bugs in this area. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * ARM: ts4600: add basic board supportSebastien Bourdelin2016-11-29-0/+364
| | | | | | | | | | | | | | | | This commit adds basic support including: MMC, Serial console Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * board: ge: bx50v3: add the PMIC configuration supportKen Lin2016-11-29-0/+54
| | | | | | | | | | | | | | | | Change the PMIC bulk configuration from auto mode to sync mode to avoid voltage dropout issue seen in auto mode. Signed-off-by: Ken Lin <ken.lin@advantech.com.tw> Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
| * ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routinesEric Nelson2016-11-29-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR calibration routines are gated by conditionals for the i.MX6DQ SOCs, but with the use of the sysinfo parameter, these are usable on at least i.MX6SDL and i.MX6SL variants with DDR3. Also, since only the Novena board currently uses the dynamic DDR calibration routines, these routines waste space on other boards using SPL. Add a KConfig entry to allow boards to selectively include the DDR calibration routines. Signed-off-by: Eric Nelson <eric@nelint.com>
| * mx6: ddr: add routine to return DDR calibration dataEric Nelson2016-11-29-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | Add routine mmdc_read_calibration() to return the output of DDR calibration. This can be used for debugging or to aid in construction of static memory configuration. This routine will be used in a subsequent patch set adding a virtual "mx6memcal" board, but could also be useful when gathering statistics during an initial production run. Signed-off-by: Eric Nelson <eric@nelint.com>
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