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| * sparc: leon3: Updated serial driver to use CONFIG_CONS_INDEXFrancois Retief2015-12-03-0/+5
| | | | | | | | | | | | | | Updated the LEON3 serial driver to make use of the CONFIG_CONS_INDEX option to select which serial port the console will use. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: Serial baud rate register support multiple buses with different frequencyDaniel Hellstrom2015-12-03-4/+16
| | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * sparc: leon3: Clear GD_FLAG_SERIAL_READY flag on AMBA failureFrancois Retief2015-12-03-0/+1
| | | | | | | | | | | | | | | | Clear the GD_FLG_SERIAL_READY flag on AMBA P&P lookup failure so that the panic function can use DEBUG_UART driver. drivers/serial/serial.c set this flag before calling this function, preventing DEBUG_UART code from running. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: Added function that checks if IRQ is on or offDaniel Hellstrom2015-12-03-0/+10
| | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * sparc: Remove version_string variable from start.S fileFrancois Retief2015-12-03-21/+6
| | | | | | | | | | | | | | Remove the version_string variable from start.S file. A weak variable is also set in the cmd_version.c file. No need for architecture override. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: Move SYS_SPARC_NWINDOWS to KconfigFrancois Retief2015-12-03-15/+14
| | | | | | | | Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-12-04-273/+689
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| * | arm: imx6: novena: Enable extfs support in SPLMarek Vasut2015-12-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Simple patch to enable support for extfs filesystem in SPL, this is useful to those who want to avoid vfat like plague. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * | arm: imx6: novena, gw_ventana: Fix use of pfuze100 bit definitionsMarek Vasut2015-12-01-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following patch changed the PFUZE100 swbst register bit definitions and broke PMIC configuration on multiple boards, at least on the novena and gw_ventana. This patch fixes it. commit 8fa46350a4c7dca7710362f6c871098557b934ad Author: Peng Fan <Peng.Fan@freescale.com> Date: Fri Aug 7 16:43:45 2015 +0800 power: regulator: add pfuze100 support Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Vagrant Cascadian <vagrant@aikidev.net> Reviewed-by: Przemyslaw Marczak <p.marczak@samsung.com> Tested-by: Vagrant Cascadian <vagrant@aikidev.net> Reviewed-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Tim Harvey <tharvey@gateworks.com>
| * | ARM: mxs: fix VDDD brownout settingMichael Heimpold2015-12-01-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment, the desired brownout is at 1.0V. However, this setting cannot be realized by hardware since we have only 3 bits to represent the voltage difference from the target value. Target value is 1500 mV, brownout target is 1000 mV, voltage steps are 25 mV. Register content calculation: (1500 [mV] - 1000 [mV]) / 25 [mV] = 20 (decimal) = 0x14 Register takes only 3 bits, that is 0x4. But 0x4 * 25 [mV] = 100 [mV], that means that actual brownout level is 1500 [mV] - 100 [mV] = 1.4 V. Minimum possible BO level is 1500 [mV] - 0x7 * 25 [mV] = 1315 [mV]. So lets use this value as desired BO value (which is also the same as FSL bootlets use). Signed-off-by: Michael Heimpold <mhei@heimpold.de> Cc: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * | mx6: clock: Modify GPMI clock to support mx6sxYe.Li2015-11-25-0/+12
| | | | | | | | | | | | | | | | | | | | | On mx6sx, the CCM register bits for GPMI are different as other mx6 platforms. Modify the GPMI clock function to support mx6sx. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | video: ipu: simplify if else codePeng Fan2015-11-25-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify if/else code, since if channel equals to MEM_BG_SYNC or MEM_FG_SYNC, we have value 5 for 'dc_chan'. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | colibri_vf: Add board_usb_phy_mode functionSanchayan Maity2015-11-25-1/+32
| | | | | | | | | | | | | | | | | | | | | | | | Add board_usb_phy_mode function for detecting whether a port is being used as host or client using a GPIO. On Colibri Vybrid we provide GPIO 102 for this very same purpose. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * | cgtqmx6eval: Add DFU supportOtavio Salvador2015-11-25-0/+22
| | | | | | | | | | | | | | | | | | | | | Add MMC and SPI DFU support. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | iomux-v3: Take MX6D in consideration for imx_iomux_v3_setup_pad()Otavio Salvador2015-11-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | We should also take MX6D option in consideration when defining imx_iomux_v3_setup_pad(). Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | cgtqmx6eval: Add SPL supportOtavio Salvador2015-11-25-270/+565
| | | | | | | | | | | | | | | | | | | | | | | | | | | Congatec has several MX6 boards based on quad, dual, dual-lite and solo. Add SPL support so that all the variants can be supported Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | cgtqmx6eval: Add fastboot supportOtavio Salvador2015-11-25-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested basic fastboot commands, such as: On the U-boot prompt: => fastboot 0 On the host PC: $ fastboot getvar bootloader-version -i 0x0525 bootloader-version: U-Boot 2015.10-rc2-09654-g8f41d27 finished. total time: 0.000s $ fastboot reboot -i 0x0525 --> board reboots fine. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | cgtqmx6eval: Use SPI NOR to store the environmentOtavio Salvador2015-11-25-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | Congatec boards boot from SPI NOR, so it makes more sense to use SPI NOR to store the environment variables. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | cgtqmx6eval: Add SPI NOR flash supportOtavio Salvador2015-11-25-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SPI NOR support: => sf probe SF: Detected SST25VF032B with page size 256 Bytes, erase size 4 KiB, total 4 MiB Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | arm: mx6: Reduce SPL malloc pool sizeMarek Vasut2015-11-23-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using 50 MiB malloc pool in SPL is nonsense. Since the caches are not enabled in SPL, it takes 2 seconds to init the pool and has no obvious benefit. Reduce the size to 1 MiB. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Tested-by: Stefano Babic <sbabic@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com>
* | | Revert "LCD: Add an option to skip registration as an stdio output"Anatolij Gustschin2015-12-02-13/+0
| |/ |/| | | | | | | | | | | | | | | | | This reverts commit 05bfe1321024e2ae0039dc16f17d2165610fb4fd. As discussed on the list, we already have the needed functionality by defining CONFIG_SYS_CONSOLE_IS_IN_ENV, CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE and adding custom overwrite_console() in the board code. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | iocon: Disable FIT_VERBOSETom Rini2015-12-01-2/+1
| | | | | | | | | | | | In order to fit into image constraints again, remove this feature. Signed-off-by: Tom Rini <trini@konsulko.com>
* | rockchip: Explicitly set CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LENSjoerd Simons2015-12-01-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that u-boot relocates the malloc area in SPL to SDRAM, with the malloc area sitting below the SPL_STACK_R_ADDR the SPL_STACK_R_MALLOC_SIMPLE_LEN needs to be set explicitly for rockchip as its SPL_STACK_R_ADDR (512kb) is smaller then STACK_R_MALLOC_SIMPLE_LEN (1Mb). Using the same value as SYS_MALLOC_F_LEN (8kb) is enough to load u-boot from SD card. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
* | Revert "rockchip: Reconfigure the malloc based to point to system memory"Sjoerd Simons2015-12-01-7/+0
| | | | | | | | | | | | | | | | | | | | | | This patch was merged shortly before the v2015.10 as a minimal fix for booting on rockchip. Now that the patch series from Hans to do the relocation in generic code has been merged it can be dropped. This reverts commit b1f492ca9e0c090209824ff36456d4f131843190. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: move SYS_MALLOC_SIMPLE to mach-rockchip KconfigAriel D'Alessandro2015-12-01-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 1eb0c03c2198a7ec9de456b83dacdc4831b96cbf added SPL_SYS_MALLOC_SIMPLE Kconfig option and changed the way it is evaluated. Thus, the definitions of CONFIG_SYS_MALLOC_SIMPLE in rk3***_common.h board configs are now incorrect because CONFIG_SPL_BUILD is enabled so CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) will look for SPL_SYS_MALLOC_SIMPLE instead of SYS_MALLOC_SIMPLE. This commit fix this enabling SPL_SYS_MALLOC_SIMPLE with the new Kconfig option by default in rockchip-mach. Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: doc: show packet rk3036 uboot imagehuang lin2015-12-01-0/+11
| | | | | | | | | | | | | | | | | | | | show how to packet rk3036 uboot image and boot from SD Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Series-to: u-boot Series-version: 8 Series-cc: Lin Huang <hl@rock-chips.com>
* | rockchip: Add support for rk's second level loaderJeffy Chen2015-12-01-17/+14
| | | | | | | | | | | | | | | | | | | | The Rockchip boot ROM could load & run an initial spl loader, and continue to load a second level boot-loader(which stored right after the initial loader) when it returns. Modify idblock generation code to support it. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: Add max spl size & spl header configsJeffy Chen2015-12-01-8/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our chips may have different max spl size and spl header, so we need to add configs for that. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, Added $(if...) to tools/Makefile to fix widespread build breakage Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, - Add $(if...) to tools/Makefile to fix widespread build breakage
* | rockchip: Add basic support for evb-rk3036 boardhuang lin2015-12-01-1/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This add some basic files required to allow the board to dispaly serial message and can run command(mmc info etc) Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Moved board Kconfig fragment from previous patch into this one to fix build error: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - moved board Kconfig fragment from previous patch into this one
* | rockchip: rk3036: Add core Soc start-up codehuang lin2015-12-01-2/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
* | rockchip: add rk3036 sdram driverhuang lin2015-12-01-0/+1107
| | | | | | | | | | | | | | add rk3036 sdram driver so we can set up sdram in SPL Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: add early uart driverhuang lin2015-12-01-0/+108
| | | | | | | | | | | | | | | | add early uart driver so we can print debug message in SPL stage Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: mmc: get the fifo mode and fifo depth property from dtshuang lin2015-12-01-4/+18
| | | | | | | | | | | | | | | | rk3036 mmc do not have internal dma, so we use fifo mode when read and write data, we get the fifo mode and fifo depth property from dts, pass to dw_mmc driver. Signed-off-by: Lin Huang <hl@rock-chips.com>
* | rockchip: mmc: use non-removable property to distinguish emmc and sdcard ↵huang lin2015-12-01-2/+3
| | | | | | | | | | | | | | | | | | | | register emmc and sdcard have different register address, use non-removeable property to distinguish them. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | mmc: dw_mmc: support fifo mode in dwc mmc driverhuang lin2015-12-01-18/+72
| | | | | | | | | | | | | | | | some soc(rk3036 etc) use dw_mmc but do not have internal dma, so we implement fifo mode to read and write data. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | mmc: dw_mmc: move data transfer as a separate functionhuang lin2015-12-01-28/+37
| | | | | | | | | | | | | | | | the data transfer seem to long in the dwmci_send_cmd function, so move this block as a separate funciton. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3036: Add pinctrl driverhuang lin2015-12-01-0/+286
| | | | | | | | | | | | | | Add a driver which support pin multiplexing setup for rk3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3036: Add a simple syscon driverhuang lin2015-12-01-1/+22
| | | | | | | | | | | | | | Add a driver that provides access to system controllers Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3036: Add Soc reset driverhuang lin2015-12-01-0/+55
| | | | | | | | | | | | | | | | We can reset the Soc using some CRU (clock/reset unit) register. Add support for this. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3036: Add header files for GRFhuang lin2015-12-01-0/+493
| | | | | | | | | | | | | | GRF is the gereral register file. Add header files with register definitions. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3036: Add clock driverhuang lin2015-12-01-0/+583
| | | | | | | | | | | | | | | | Add a driver for setting up and modifying the various PLLs, peripheral clocks and mmc clocks on RK3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: Bring in RK3036 device tree file includes and bindingshuang lin2015-12-01-0/+613
| | | | | | | | | | | | | | | | | | Since rk3036 device tree file still in reviewing, bring it from https://patchwork.kernel.org/patch/7203371/ and add some aliases we need in uboot Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: serial driver support rk3036huang lin2015-12-01-0/+1
| | | | | | | | | | Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dm: core: Add SPL Kconfig for REGMAP and SYSCONhuang lin2015-12-01-2/+27
| | | | | | | | | | | | | | | | Add SPL Kconfig for REGMAP and SYSCON, so REGMAP and SYSCON can remove from SPL stage. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: add config decide whether to build common.chuang lin2015-12-01-1/+4
| | | | | | | | | | | | | | | | some rockchips soc will not use uclass in SPL stage, so define config to decide whether to build common.c Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rename board-spl.c to rk3288-board-spl.chuang lin2015-12-01-1/+1
| | | | | | | | | | | | | | | | since different rockchip soc need different spl file, so rename board-spl.c. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfighuang lin2015-12-01-3/+3
| | | | | | | | | | | | | | | | | | since different rockchip SOC have different size of SRAM, So the size SYS_MALLOC_F_LEN may different, so move this config to rk3288 own Kconfig Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: add timer driverhuang lin2015-12-01-20/+75
| | | | | | | | | | | | | | | | some rockchip soc will not include lib/timer.c in SPL stage, so implement timer driver for some soc can use us delay function in SPL. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: firefly: Save the environment on SD cardSjoerd Simons2015-12-01-1/+9
| | | | | | | | | | | | | | | | Save the environment on the SD card for Firefly in the empty space between the SPL and the u-boot image. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: Also load the initrd below 512MSjoerd Simons2015-12-01-0/+1
| | | | | | | | | | | | | | | | | | Similar to load an fdt, when loading an initrd about the 512Mb mark things seem to break. For now force loading below 512Mb until the reason why this fails has been determined/solved. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-07-16 09:33:40 +0000