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* misc: add "call" uclass opStephen Warren2016-08-12-0/+46
| | | | | | | | | | The call op requests that the callee pass a message to the underlying HW or device, wait for a response, and then pass back the response error code and message to the callee. It is useful for drivers that represent some kind of messaging or IPC channel to a remote device. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* power: pmic: act8846: add missing newline to debug statementsJohn Keeping2016-08-12-2/+2
| | | | | Signed-off-by: John Keeping <john@metanate.com> Acked-by: Simon Glass <sjg@chromium.org>
* power: regulator: act8846: fix reading valuesJohn Keeping2016-08-12-2/+2
| | | | | | | | | The voltage and control registers need to be looked up from the value in driver_data. Adjust the get_value and get_enable functions to match the corresponding set_* functions. Signed-off-by: John Keeping <john@metanate.com> Acked-by: Simon Glass <sjg@chromium.org>
* fdt: allow fdtdec_get_addr_size_*() to translate addressesStephen Warren2016-08-12-17/+36
| | | | | | | | | | | | | | | Some code may want to read reg values from DT, but from nodes that aren't associated with DM devices, so using dev_get_addr_index() isn't appropriate. In this case, fdtdec_get_addr_size_*() are the functions to use. However, "translation" (via the chain of ranges properties in parent nodes) may still be desirable. Add a function parameter to request that, and implement it. Update all call sites to default to the original behaviour. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Squashed in build fix from Stephen: Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt_support: fdt_translate_address() blob const correctnessStephen Warren2016-08-12-12/+14
| | | | | | | | | | | | The next patch will call fdt_translate_address() from somewhere with a "const void *blob" rather than a "void *blob", so fdt_translate_address() must accept a const pointer too. Constify the minimum number of function parameters to achieve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Squashed in build fix from Stephen: Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-08-11-176/+537
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| * ARM: uniphier: add PSCI support for UniPhier ARMv7 SoCsMasahiro Yamada2016-08-11-3/+275
| | | | | | | | | | | | Currently, only the CPU_ON function is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: add uniphier_cache_set_active_ways()Masahiro Yamada2016-08-11-1/+22
| | | | | | | | | | | | | | | | This outer cache allows to control active ways independently for each CPU, so this function will be useful to set up active ways for a specific CPU. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: add uniphier_cache_inv_way() to support way invalidationMasahiro Yamada2016-08-11-1/+10
| | | | | | | | | | | | This invalidates entries in specified ways of the outer cache. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: fix CONFIG_SYS_CACHELINE_SIZE when outer cache is onMasahiro Yamada2016-08-11-0/+4
| | | | | | | | | | | | | | The UniPhier outer cache (L2 cache on ARMv7 SoCs) has 128 byte line length and its tags are also managed per 128 byte line. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: move (and rename) CONFIG_UNIPHIER_L2CACHE_ON to KconfigMasahiro Yamada2016-08-11-4/+8
| | | | | | | | | | | | | | Move this option to Kconfig, renaming it into CONFIG_CACHE_UNIPHIER. The new option name makes sense enough, and the same as Linux has. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: move outer cache register macros to .c fileMasahiro Yamada2016-08-11-69/+55
| | | | | | | | | | | | | | Now, all of these macros are only used in cache-uniphier.c, so there is no need to export them in a header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: reuse uniphier_cache_disable() for lowlevel_initMasahiro Yamada2016-08-11-7/+3
| | | | | | | | | | | | | | The DRAM is available at this point, so setup the temporary stack and call the C function to reduce the code duplication a bit. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: export uniphier_cache_enable/disable functionsMasahiro Yamada2016-08-11-10/+26
| | | | | | | | | | | | | | | | The System Cache (outer cache) is used not only as L2 cache, but also as locked SRAM. The functions for turning on/off it is necessary whether the L2 cache is enabled or not. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: move lowlevel debug init code after page table switchMasahiro Yamada2016-08-11-4/+4
| | | | | | | | | | | | | | | | | | As the sLD3 Boot ROM has a complex page table, it is difficult to set up the debug UART with enabling it. It will be much easier to initialize the UART port after switching over to the straight-mapped page table. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: fix ROM boot mode for PH1-sLD3Masahiro Yamada2016-08-11-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4b50369fb535 ("ARM: uniphier: create early page table at run-time") broke the ROM boot mode for PH1-sLD3 SoC, because the run-time page table creation requires the outer cache register access but the page table in the sLD3 Boot ROM does not straight-map virtual/physical addresses. The idea here is to check the current page table to determine if it is a straight map table. If not, adjust the outer cache register base. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: refactor L2 zero-touching code in lowlevel_initMasahiro Yamada2016-08-11-26/+22
| | | | | | | | | | | | | | Here, the ldr pseudo-instruction falls into the ldr + data set. The register access by [r1, #offset] produces shorter code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: do not compile v7_outer_cache_disable if L2 is disabledMasahiro Yamada2016-08-11-1/+1
| | | | | | | | | | | | | | | | If CONFIG_UNIPHIER_L2CACHE_ON is undefined, the L2 cache is never enabled, so there is no need for v7_outer_cache_disable(). The weak stub avoids the compile error anyway. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: support prefetch and touch operations for outer cacheMasahiro Yamada2016-08-11-10/+57
| | | | | | | | | | | | | | | | | | | | The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as SRAM by locking ways. These functions will be used to transfer the trampoline code for SMP into the locked SRAM. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: refactor outer cache codeMasahiro Yamada2016-08-11-47/+52
| | | | | | | | | | | | | | | | | | Unify the range/all operation routines into the common function, uniphier_cache_maint_common(), and sync code with Linux a bit more. This reduces the code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-08-11-116/+885
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| * eth: asix88179: Add support for the driver modelAlban Bedel2016-08-09-0/+184
| | | | | | | | | | | | Adjust this driver to support driver model for Ethernet. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
| * eth: asix88179: Prepare supporting the driver modelAlban Bedel2016-08-09-28/+47
| | | | | | | | | | | | | | Change the prototype of a few functions to allow resuing the code for the driver model. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
| * eth: asix88179: Fix receiving on big endian systemAlban Bedel2016-08-07-1/+1
| | | | | | | | | | | | | | | | | | In asix_recv() the call to convert the endianess of the receive header was applied on the wrong variable. Instead of converting rx_hdr it converted pkt_hdr which is a pointer, and not yet initialiazed at this point. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
| * eth: asix88179: Add VID:DID for Cypress GX3 USB Ethernet AdapterAlban Bedel2016-08-07-0/+2
| | | | | | | | | | | | | | Added support for the Cypress GX3 SuperSpeed to Gigabit Ethernet Bridge Controller (VID_04b4/PID_3610). Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
| * arm: ls1021a: Enable CONFIG_DM_USB in defconfigsRajesh Bhagat2016-08-07-0/+4
| | | | | | | | | | | | | | Enables driver model flag CONFIG_DM_USB for LS1021A platform defconfigs. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * dm: ls1021a: dts: Update USB 3.0 node to support DM USBRajesh Bhagat2016-08-07-1/+1
| | | | | | | | | | | | Update USB 3.0 controller dts node in ls1021a.dtsi. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * usb: xhci: fsl: Add code to use CONFIG_DM_USBRajesh Bhagat2016-08-07-1/+82
| | | | | | | | | | | | Adds code to use driver model for USB XHCI FSL driver Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * usb: ehci: fsl: Add code to use CONFIG_DM_USBRajesh Bhagat2016-08-07-4/+127
| | | | | | | | | | | | Adds code to use driver model for USB EHCI FSL driver Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * drivers: usb: fsl: Make function for initialization to use in CONFIG_DM_USBRajesh Bhagat2016-08-07-27/+36
| | | | | | | | | | | | | | Moves code from ehci_hcd_init to new function ehci_fsl_init which can be re-used in CONFIG_DM_USB. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * usb: add (move) CONFIG_USB_HOST to KconfigMasahiro Yamada2016-08-07-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The meaning of CONFIG_USB in U-Boot is different from that in Linux. As you see in drivers/usb/Kconfig of Linux, CONFIG_USB enables the USB host controller support, while CONFIG_USB_SUPPORT is used to enable the whole of the USB sub-system. When I added CONFIG_USB into Kconfig by commit 6e7e9294d321 ("usb: add basic USB configs in Kconfig"), I planned to follow the Linux's convention, i.e. CONFIG_USB to enable/disable the USB host support. Then, commit 68f7c5db2d1e ("usb: Generic USB Kconfig option, that fits both host and gadget and comments") changed the logic of the CONFIG_USB to point to the whole of the USB sub-system. As a result, currently we do not have an option for USB host. This commit adds CONFIG_USB_HOST, which will be useful to compile in the USB host support code. CONFIG_USB_HOST is not referenced at all, but strangely some boards define it in board headers. I removed them because USB_HOST will be selected in Kconfig going forward. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * usb: add CONFIG_USB_UHCI_HCD in KconfigMasahiro Yamada2016-08-07-0/+17
| | | | | | | | | | | | | | | | | | | | There is no UHCI driver entry in Kconfig for now, but we have some UHCI drivers, for example, LEON. This is a placeholder in case we want to move them to Kconfig in the future. The help message was copied from Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * usb: add CONFIG_USB_OHCI_HCD in KconfigMasahiro Yamada2016-08-07-10/+26
| | | | | | | | | | | | | | | | | | | | | | Add this option as a common config for all OHCI controllers. Its help message was copied from Linux. Also, I moved it below EHCI to respect the order in Linux's Kconfig. Add CONFIG_USB_OHCI_HCD=y to axs103_defconfig, which is the only user of OHCI_GENERIC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * net: usb: r8152: Add DM supportStefan Roese2016-08-07-22/+221
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for driver model, so that CONFIG_DM_ETH can be defined and used with this driver. This patch also adds the read_rom_hwaddr() callback so that the ROM MAC address will be used to the DM part of this driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com> Cc: Ted Chen <tedchen@realtek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Joe Hershberger <joe.hershberger@ni.com>
| * dm: ehci-mx6: support driver modelPeng Fan2016-08-07-14/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support driver model for ehci mx6 driver. Consolidate code to be shared between DM and non-DM, such as introducing ehci_mx6_common_init. For simplicity, some old fasion code are keeped for DM usage, such as board_ehci_power and board_usb_phy_mode. And 'dr-mode', usbphy and vbus handling code for DM is not added now. These will be added in future patches. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Marek Vasut <marex@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Stefan Agner <stefan@agner.ch> Cc: Simon Glass <sjg@chromium.org>
* | Merge git://www.denx.de/git/u-boot-ppc4xxTom Rini2016-08-09-21/+45
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| * | ppc4xx: Fix platform supportDirk Eibach2016-08-09-21/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit "ecc3066 Fix board init code to respect the C runtime environment" broke platform support for ppc4xx. start.S prepares a stackframe that is later rendered unusable by appending the reserved space for global data. Instead the reserved space has to be put first. Then the stackframe can be pushed. I can only test the 405EP OCM case. At least all other ppc4xx boards still build. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* | | i2c: i2c-uclass-compat: avoid any BSS usageVignesh R2016-08-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As I2C can be used before DRAM initialization for reading EEPROM, avoid using static variables stored in BSS, since BSS is in DRAM, which may not have been initialised yet. Explicitly mark "static global" variables as belonging to the .data section. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Heiko Schocher<hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | efi_loader: disk: Sanitize exposed devicesAlexander Graf2016-08-08-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a target device is 0 bytes long, there's no point in exposing it to the user. Let's just skip them. Also, when an offset is passed into the efi disk creation, we should remove this offset from the total number of sectors we can handle. This patch fixes both things. Signed-off-by: Alexander Graf <agraf@suse.de>
* | | efi_loader: disk: Fix CONFIG_BLK breakageAlexander Graf2016-08-08-12/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using CONFIG_BLK, there were 2 issues: 1) The name we generate the device with has to match the name we set in efi_set_bootdev() 2) The device we pass into our block functions was wrong, we should not rediscover it but just use the already known pointer. This patch fixes both issues. Signed-off-by: Alexander Graf <agraf@suse.de>
* | | tiny-printf: Adjust to avoid using data sectionSimon Glass2016-08-08-44/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can pass all the variables down to the functions that need them, and then everything is on the stack. This is safer than using the data section. At least on firefly-rk3288, the code size is the same and the data size is 12 bytes smaller: before: 18865 2636 40 21541 5425 b/firefly-rk3288/spl/u-boot-spl after: 18865 2624 40 21529 5419 b/firefly-rk3288/spl/u-boot-spl Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de>
* | | configs: k2l_evm: add random eth address supportMugunthan V N2016-08-08-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is only one ethernet mac address in e-fuse, but there are multiple slaves in keystone net, so enable random mac address support. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | configs: k2e_evm: add random eth address supportMugunthan V N2016-08-08-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is only one ethernet mac address in e-fuse, but there are multiple slaves in keystone net, so enable random mac address support. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | configs: k2hk_evm: add random eth address supportMugunthan V N2016-08-08-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is only one ethernet mac address in e-fuse, but there are multiple slaves in keystone net, so enable random mac address support. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | drivers: net: keystone_net: add support for multi slave ethernetMugunthan V N2016-08-08-45/+177
| | | | | | | | | | | | | | | | | | | | | | | | | | | Keystone net can have multiple ethernet slaves, currently only slave 1 is supported by the driver. Register multiple slaves as individual ethernets to network framework. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | drivers: net: keystone_net: fix line termination with semi-colonMugunthan V N2016-08-08-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Each line should be terminated by semi-colon. It was not caught earlier as there is a proper statement. Fix it by changing the comma with semi-colon. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: dts: dra72-evm: Add mode-gpios entry for mac nodeVignesh R2016-08-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On DRA72 EVM, cpsw slave1 is muxed with VIN2A, hence switch to cpsw slave0 for ethernet. This is controlled by pcf gpio line. Add appropriate mode-gpios DT entry so that driver can select the required slave. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* | | net: cpsw: Add support to drive gpios for ethernet to be functionalVignesh R2016-08-08-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On DRA72 EVM, cpsw slaves may be muxed with other modules. This selection is controlled by a pcf gpio line. Add support for cpsw driver to acquire mode-gpios and select the appropriate slave using gpio APIs. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* | | ARM: dts: dra7xx: Add u-boot specific property for PCF8575 nodesVignesh R2016-08-08-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCF8575 does not have any registers hence, offset field needs to be ignored for i2c read/write. Therefore populate u-boot,i2c-offset-len with 0 in PCF8575 DT nodes. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: dra7xx_evm: Enable support for TI PCF8575Vignesh R2016-08-08-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On DRA7, pcf chip present at address 0x21 on i2c1, is used to switch between cpsw slave0 and slave1. Hence, enable PCF driver for the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-09-15 20:46:31 +0000