| Commit message (Collapse) | Author | Age | Lines |
|
|
|
|
|
|
| |
Warp uses eMMC connected to esdhc2 port, so fix
CONFIG_SYS_FSL_ESDHC_ADDR to reflect that.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
|
|
|
|
|
|
|
|
|
| |
Adjust CONFIG_SYS_DFU_DATA_BUF_SIZE in order to avoid the following error
when running the dfu command:
=> dfu 0 mmc 0
dfu_get_buf: Could not memalign 0x2000000 bytes
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
|
|
|
|
|
|
|
| |
If CONFIG_PCI_SCAN_SHOW enabled then lets print a message of no link was
detected.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
|
|
|
|
|
| |
This reverts commit a0117a5e416629932becf079589f5e1859eab90a.
Signed-off-by: Stefano Babic <sbabic@denx.de>
|
|
|
|
|
|
|
| |
max_freq in print_cpuinfo is used only with
imx6.
Signed-off-by: Stefano Babic <sbabic@denx.de>
|
|\ |
|
| |
| |
| |
| |
| |
| |
| | |
Move CONFIG_CMD_CACHE to mx6_common and standardise the way it's defined.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Tom Rini <trini at konsulko.com>
|
| |
| |
| |
| |
| |
| |
| | |
Move all standard mx6 MMC configs to mx6_common.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Tom Rini <trini at konsulko.com>
|
| |
| |
| |
| |
| |
| | |
Move all standard filesystem, partition and fdt options to mx6_common.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
|
| |
| |
| |
| |
| |
| |
| | |
Move generic miscellaneous options that are standard across most, if not all,
mx6 boards to central mx6_common define to ensure consistent features.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
|
| |
| |
| |
| |
| |
| |
| | |
Define common LOADADDR and BOOTDELAY to ensure a consistent experience
across mx6 boards
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
|
| |
| |
| |
| |
| |
| | |
Define CONFIG_MXC_GPIO and CONFIG_CMD_GPIO by default in mx6_common
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
|
| |
| |
| |
| |
| |
| |
| | |
Define the standard ATAG consfigs in mx6_common.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Tom Rini <trini at konsulko.com>
|
| |
| |
| |
| |
| |
| |
| |
| | |
All boards define CONFIG_MX6, CONFIG_DISPLAY_BOARDINFO, CONFIG_DISPLAY_CPUINFO
and CONFIG_SYS_GENERIC_BOARD so define them in mx6_common
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Tom Rini <trini at konsulko.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The linux/sizes.h, asm/arch/imx-regs.h, asm/imx-common/gpio.h,
config_cmd_default.h includes are used fairly universally across imx6 boards
so include them in mx6_common.h by default.
We define CONFIG_SYS_NO_FLASH before config_cmd_default.h so that we
don't have to undef CONFIG_CMD_FLASH / CONFIG_CMD_IMLS everywhere.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
|
| |
| |
| |
| |
| |
| |
| | |
Standardise mx6_common.h to the same as other mx6 boards
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Tom Rini <trini at konsulko.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
91199f4a5a21a7cf9dd9e7c05e295a042f8c2b7e broke mmc based Falcon mode.
The block_read function returns the number of blocks read thus the error
check needs to look for a return of 0 blocks read.
Cc: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
|
| |
| |
| |
| | |
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
| |
| |
| |
| | |
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
| |
| |
| |
| |
| |
| | |
We will use the same env size and redundancy used for NAND env for MMC.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The CPU temperature grade from OTP is now used to define the critical
threshold at which point we busyloop until we are below, however this
threshold is still too low.
Instead of 20C below the max CPU temperature, change it to 5C defined now
by TEMPERATURE_HOT_DETLA for clarity. Rename 'passive' to 'critical'
as that better defines our use case here. Additionally change the output
of the busyloop message to show the max CPU temperature as well as current.
Before:
CPU Temperature is 101 C, too hot to boot, waiting...
CPU Temperature is 101 C, too hot to boot, waiting...
After:
CPU Temperature (101C) too close to max (105C) waiting...
CPU Temperature (101C) too close to max (105C) waiting...
Cc: Stefan Roese <sr@denx.de>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Jon Nettleton <jon.nettleton@gmail.com>
Cc: Jason Liu <r64343@freescale.com>
Cc: Ye Li <b37916@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Peng Fan <b51431@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
add support for imx6dl based aristainetos2 board
U-Boot 2015.04-rc5-00066-g60f6ed4 (Apr 10 2015 - 08:46:27)
CPU: Freescale i.MX6DL rev1.1 at 792 MHz
Reset cause: WDOG
Board: aristaitenos2
Watchdog enabled
I2C: ready
DRAM: 1 GiB
NAND: 1024 MiB
MMC: FSL_SDHC: 0
SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB
Display: lg4573 (480x800)
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
=>
Signed-off-by: Heiko Schocher <hs@denx.de>
|
| |
| |
| |
| |
| |
| |
| | |
rework and unify i2c address names for different SoCs, which
use the mxc_i2c driver.
Signed-off-by: Heiko Schocher <hs@denx.de>
|
| |
| |
| |
| |
| |
| | |
add I2C4 modul for MX6DL based boards.
Signed-off-by: Heiko Schocher <hs@denx.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee
that socs' cache line size is 32 bytes.
If on chips whose cache line size is 64 bytes, error occurs:
"
NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0
ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0
"
Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to
CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
|
| |
| |
| |
| |
| |
| |
| |
| | |
The break after return is unreachable code, remove it.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| | |
pwm_id_to_reg() can return NULL, so add NULL testing to prevent NULL pointer
dereference.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
|
| |
| |
| |
| |
| |
| | |
Falcon mode entails the SPL booting the OS directly instead of U-Boot.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Currently we need to build one U-boot image for each of the wandboard
variants: quad, dual-lite and solo.
By switching to SPL we can support all these variants with a single binary,
which is very convenient.
Based on the work from Richard Hu.
Tested kernel booting on the three boards.
Signed-off-by: Richard Hu <hakahu@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Vagrant Cascadian <vagrant@aikidev.net>
Reviewed-by: Stefano Babic <sbabic@denx.de>
|
| |
| |
| |
| |
| |
| |
| | |
Replace the hard-coded values for min/max/passive with values derived from
the CPU temperature grade.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
When CONFIG_IMX6_THERMAL is defined print the CPU temperature grade info
along with the current temperature.
Before:
CPU: Temperature 42 C
After:
CPU: Automotive temperature grade (-40C to 125C) at 42C
CPU: Industrial temperature grade (-40C to 105C) at 42C
CPU: Extended Commercial temperature grade (-20C to 105C) at 42C
Cc: Stefan Roese <sr@denx.de>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Jon Nettleton <jon.nettleton@gmail.com>
Cc: Jason Liu <r64343@freescale.com>
Cc: Ye Li <b37916@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Peng Fan <b51431@freescale.com>
Tested-by: Nikolay Dimitrov <picmaster@mail.bg>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480
in the Fusemap Description Table in the reference manual. Return this value
as well as min/max temperature based on the value.
Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.
This has been tested with IMX6 Automative and Industrial parts.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Display the max CPU frequency as well as the current running CPU frequency
if the max CPU frequency is available and differs from the current CPU
frequency.
Before:
CPU: Freescale i.MX6Q rev1.2 at 792 MHz
After - using an 800MHz IMX6DL (running at its max)
CPU: Freescale i.MX6DL rev1.1 at 792 MHz
After - using a 1GHz IMX6Q (not running at its max):
CPU: Freescale i.MX6Q rev1.2 996 MHz (running at 792 MHz)
Cc: Stefan Roese <sr@denx.de>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Jon Nettleton <jon.nettleton@gmail.com>
Cc: Jason Liu <r64343@freescale.com>
Cc: Ye Li <b37916@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Peng Fan <b51431@freescale.com>
Tested-by: Nikolay Dimitrov <picmaster@mail.bg>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING
indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description
Table. Return this frequency so that it can be used elsewhere.
Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.
These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
| |
| |
| |
| | |
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support
to the MMDC however enabling it on the DDR3 got missed. Make sure we enable
it on the DDR3 as well.
Gateworks uses Micron memory as well as Winbond in MX6. We have found in
testing that we need to enable fast-exit for Winbond stability. Gateworks
boards are currently the only boards using the MX6 SPL and enabling
fast-exit mode.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Fix below warning
arch/arm/imx-common/cpu.c:29:14: warning: ‘get_reset_cause’ defined but
not used
static char *get_reset_cause(void)
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
|
| |
| |
| |
| |
| |
| | |
Change PUZE_100_SW1ABCONF to PFUZE100_SW1ABCONF
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Enable IOMUX_CONFIG_SION for all I2C pin mux settings, otherwise
we will get erros when doing i2c operations.
error log like the following:
"
wait_for_sr_state: failed sr=81 cr=a0 state=2020
i2c_init_transfer: failed for chip 0xb retry=1
"
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
|
| |
| |
| |
| | |
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
|
| |
| |
| |
| | |
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
|
| |
| |
| |
| | |
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The 'mx6-microsom' directory was only used for the previous mx6solo
hummingboard support, which has been removed in favour of the SPL
version.
Remove the remaining piece of the old mx6solo hummingboard support.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
|
| |
| |
| |
| |
| |
| |
| | |
We need to do any PMIC setup in the SPL if we are to bypass U-Boot for
falcon mode.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
| |
| |
| |
| |
| |
| | |
Use the SZ_1M and SZ_1K macros from linuz/sizes.h for improved readability
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
| |
| |
| |
| |
| |
| | |
Switch to MMC RAW support for SPL. We will place the uboot.img at 69KB.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The readenv() implementation of env_nand uses the mtd layer which is
unnecessary overhead in SPL when we already have a nand_spl_load_image()
function that doesn't need it. Using this instead eliminates the need
to provide a mtd_read for SPL env as well as reduces code (4KB savings in IMX6
SPL).
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Scott Wood <scottwood@freescale.com>
|
|\ \ |
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Due to licensing issues, the files ps7_init.c/h are not able to be
distributed with U-Boot source code. Recent Xilinx tools also
provide the GPL variants (ps7_init_gpl.c/h), compatible with U-Boot
license.
Prior to this commit, we had to copy ps7_init files into
board/xilinx/zynq/ before the compile.
To be more user-friendly, let's include ps7_init_gpl.c/h for
Zedboard, MicroZed, ZC702, ZC706.
These init code have been taken from the hwplatform_templates
directory of Xilinx SDK 2014.4.
You can still use customized ps7_init_gpl.c/h by enabling
CONFIG_ZYNQ_CUSTOM_INIT. The recommended directory for storing them
is now board/xilinx/zynq/custom_hw_platform, but board/xilinx/zynq
is still supported for backward compatibility. The latter emits
a warning message to prompt users to gradually switch to the new
directory.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Prior to this commit, ZC702 and ZC706 shared the same configuration
and were built as follows:
ZC702: make zynq_zc70x_defconfig && make
ZC706: make zynq_zc70x_defconfig && make DEVICE_TREE=zynq-zc706
This commit introduces separate configuration for them, which makes
the next commit much easier.
Going forward, the recommended build commands are:
ZC702: make zynq_zc702_defconfig && make
ZC706: make zynq_zc706_defconfig && make
Although the old work flow is still supported, CONFIG_TARGET_ZC70X
has been marked as deprecated. If used, the warning message is
shown to prompt users to switch to the new scheme.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|