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* ARM: tegra: enable PCIe controller on p2771-0000Stephen Warren2016-08-15-0/+75
| | | | | | | | | | | p2771-0000 has a couple of PCIe ports; one physically x4 desktop PCI connector (which may run at x2 electrically, depending on the board version and configuration) and a x1 connection to the M.2 slot (which may not be active, depending on the board version and configuration). This change enables those. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: enable SD card on p2771-0000Stephen Warren2016-08-15-0/+52
| | | | | | | | | | Now that clock and reset drivers exist for Tegra186, we can enable the SD card controller. Now that a BPMP I2C driver exists for Tegra186, we can communicate with the PMIC to enable power to the SD card. Hook up the DT content and board code required to make the SD card work. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: enable I2C buses for P2771-0000Bryan Wu2016-08-15-0/+38
| | | | | | | | | | Enable I2C devices in DT and enable building tegra_i2c.c driver. Signed-off-by: Bryan Wu <pengw@nvidia.com> (swarren, commit msg rework, fixed DT node sort order) Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* i2c: tegra: add standardized clk/reset API supportBryan Wu2016-08-15-4/+85
| | | | | | | | | | | | | clk/reset API was tested on T186 platform and previous chip like T210/T124 will still use the old APIs. Signed-off-by: Bryan Wu <pengw@nvidia.com> (swarren, simplified some ifdefs, removed indent level inside an ifdef) (swarren, added comment about the ifdefs) Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* pci: tegra: port to standard clock/reset/pwr domain APIsStephen Warren2016-08-15-5/+159
| | | | | | | | | | | | | Tegra186 supports the new standard clock, reset, and power domain APIs. Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so that it can operate with either set of APIs. On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming. Consequently, this logic is disabled too. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mmc: tegra: port to standard clock/reset APIsStephen Warren2016-08-15-10/+62
| | | | | | | | | | Tegra186 supports the new standard clock and reset APIs. Older Tegra SoCs still use custom APIs. Enhance the Tegra MMC driver so that it can operate with either set of APIs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* i2c: add Tegra186 BPMP driverStephen Warren2016-08-15-0/+140
| | | | | | | | | | | On Tegra186, some I2C controllers are directly controlled by the main CPU, whereas others are controlled by the BPMP, and can only be accessed by the main CPU via IPC requests to the BPMP. This driver covers the latter case. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* power domain: add Tegra186 driverStephen Warren2016-08-15-0/+100
| | | | | | | | | | In Tegra186, SoC power domains are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* reset: add Tegra186 reset driverStephen Warren2016-08-15-0/+91
| | | | | | | | | | | In Tegra186, on-SoC reset signals are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* clock: add Tegra186 clock driverStephen Warren2016-08-15-0/+120
| | | | | | | | | | | | In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. A tegra/ sub-directory is created to follow the existing pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* misc: add Tegra BPMP driverStephen Warren2016-08-15-0/+1863
| | | | | | | | | | | | | | | The Tegra BPMP (Boot and Power Management Processor) is a separate auxiliary CPU embedded into Tegra to perform power management work, and controls related features such as clocks, resets, power domains, PMIC I2C bus, etc. This driver provides the core low-level communication path by which feature-specific drivers (such as clock) can make requests to the BPMP. This driver is similar to an MFD driver in the Linux kernel. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2016-08-12-33/+100
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| * misc: add "call" uclass opStephen Warren2016-08-12-0/+46
| | | | | | | | | | | | | | | | | | | | The call op requests that the callee pass a message to the underlying HW or device, wait for a response, and then pass back the response error code and message to the callee. It is useful for drivers that represent some kind of messaging or IPC channel to a remote device. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
| * power: pmic: act8846: add missing newline to debug statementsJohn Keeping2016-08-12-2/+2
| | | | | | | | | | Signed-off-by: John Keeping <john@metanate.com> Acked-by: Simon Glass <sjg@chromium.org>
| * power: regulator: act8846: fix reading valuesJohn Keeping2016-08-12-2/+2
| | | | | | | | | | | | | | | | | | The voltage and control registers need to be looked up from the value in driver_data. Adjust the get_value and get_enable functions to match the corresponding set_* functions. Signed-off-by: John Keeping <john@metanate.com> Acked-by: Simon Glass <sjg@chromium.org>
| * fdt: allow fdtdec_get_addr_size_*() to translate addressesStephen Warren2016-08-12-17/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some code may want to read reg values from DT, but from nodes that aren't associated with DM devices, so using dev_get_addr_index() isn't appropriate. In this case, fdtdec_get_addr_size_*() are the functions to use. However, "translation" (via the chain of ranges properties in parent nodes) may still be desirable. Add a function parameter to request that, and implement it. Update all call sites to default to the original behaviour. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Squashed in build fix from Stephen: Signed-off-by: Simon Glass <sjg@chromium.org>
| * fdt_support: fdt_translate_address() blob const correctnessStephen Warren2016-08-12-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | The next patch will call fdt_translate_address() from somewhere with a "const void *blob" rather than a "void *blob", so fdt_translate_address() must accept a const pointer too. Constify the minimum number of function parameters to achieve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Squashed in build fix from Stephen: Signed-off-by: Simon Glass <sjg@chromium.org>
* | kconfig: use bool instead of boolean for type definition attributesMasahiro Yamada2016-08-12-22/+22
| | | | | | | | | | | | | | | | | | | | Linux stopped the use of keyword 'boolean' in Kconfig. Refer to commit 6341e62b212a2541efb0160c470e90bd226d5496 ("kconfig: use bool instead of boolean for type definition attributes") in Linux Kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | defconfig: am43xx_evm: enable eth driver modelMugunthan V N2016-08-12-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Enable eth driver model for am43xx_evm as cpsw supports driver model. This was already added with the commit bc705ea1cf12 but with commit 4c4e3b37750f to add fit support CONFIG_DM_ETH was missed. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | drivers: net: cpsw: always flush cache of size aligned to PKTALIGNLokesh Vutla2016-08-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | cpsw tries to flush dcache which is not in the range of PKTALIGN. Because of this the following warning comes while flushing: CACHE: Misaligned operation at range [dffecec0, dffed016] Fix it by flushing cache of size aligned to PKTALIGN. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | configs: dra7xx_evm: enable eth driver modelMugunthan V N2016-08-12-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Enable eth driver model for dra7xx_evm as cpsw supports driver model. This was already added with the commit 641b936fa5ba but with commit bd7245849f7c to add fit support CONFIG_DM_ETH was missed. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: dra7xx_evm: Enable regulator DM supportVignesh R2016-08-12-0/+6
| | | | | | | | | | | | | | | | Enable DM based regulator framework and also fixed regulator support as some IPs like mmc use regulators for there functioning. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: dts: dra7xx-evm: add evm_3v3_sd regulatorVignesh R2016-08-12-2/+22
| | | | | | | | | | | | | | | | | | | | Add a node for evm_3v3_sd using onboard PCF GPIO expander which feeds on to mmc vdd. Update mapping for vmmc-supply and vmmc_aux-supply. evm_3v3_sd supplies to SD card vdd, and ldo1 to sdcard i/o lines. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | common: image: Add support for post-processing of imagesAndreas Dannenberg2016-08-12-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit allows injecting a board/platform/device-specific post- processing function into the FIT image data loading process, which can include modifying the size and altering the starting source address of an image data artifact. This might be desired to do things like strip headers or footers attached to the images before they were packaged into the FIT, or to perform operations such as decryption or authentication. Introduce new configuration option CONFIG_FIT_IMAGE_POST_PROCESS to allow controlling this feature. If enabled, a platform-specific post- process function must be provided. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | drivers/sysreset: group sysreset driversMax Filippov2016-08-12-16/+35
| | | | | | | | | | | | | | | | Create drivers/sysreset and move sysreset-uclass and all sysreset drivers there. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | ARM: non-sec: flush code cacheline alignedStefan Agner2016-08-12-1/+3
| | | | | | | | | | | | | | | | | | | | Flush operations need to be cacheline aligned to take effect, make sure to flush always complete cachelines. This avoids messages such as: CACHE: Misaligned operation at range [00900000, 009004d9] Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
* | i2c: Drop redundant platform data setting in driversSimon Glass2016-08-12-6/+0
|/ | | | | | | | | The i2c uclass has a default setting for per_child_platdata_auto_alloc_size so drivers do not need to set it. Remove this from drivers to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-08-11-176/+537
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| * ARM: uniphier: add PSCI support for UniPhier ARMv7 SoCsMasahiro Yamada2016-08-11-3/+275
| | | | | | | | | | | | Currently, only the CPU_ON function is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: add uniphier_cache_set_active_ways()Masahiro Yamada2016-08-11-1/+22
| | | | | | | | | | | | | | | | This outer cache allows to control active ways independently for each CPU, so this function will be useful to set up active ways for a specific CPU. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: add uniphier_cache_inv_way() to support way invalidationMasahiro Yamada2016-08-11-1/+10
| | | | | | | | | | | | This invalidates entries in specified ways of the outer cache. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: fix CONFIG_SYS_CACHELINE_SIZE when outer cache is onMasahiro Yamada2016-08-11-0/+4
| | | | | | | | | | | | | | The UniPhier outer cache (L2 cache on ARMv7 SoCs) has 128 byte line length and its tags are also managed per 128 byte line. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: move (and rename) CONFIG_UNIPHIER_L2CACHE_ON to KconfigMasahiro Yamada2016-08-11-4/+8
| | | | | | | | | | | | | | Move this option to Kconfig, renaming it into CONFIG_CACHE_UNIPHIER. The new option name makes sense enough, and the same as Linux has. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: move outer cache register macros to .c fileMasahiro Yamada2016-08-11-69/+55
| | | | | | | | | | | | | | Now, all of these macros are only used in cache-uniphier.c, so there is no need to export them in a header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: reuse uniphier_cache_disable() for lowlevel_initMasahiro Yamada2016-08-11-7/+3
| | | | | | | | | | | | | | The DRAM is available at this point, so setup the temporary stack and call the C function to reduce the code duplication a bit. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: export uniphier_cache_enable/disable functionsMasahiro Yamada2016-08-11-10/+26
| | | | | | | | | | | | | | | | The System Cache (outer cache) is used not only as L2 cache, but also as locked SRAM. The functions for turning on/off it is necessary whether the L2 cache is enabled or not. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: move lowlevel debug init code after page table switchMasahiro Yamada2016-08-11-4/+4
| | | | | | | | | | | | | | | | | | As the sLD3 Boot ROM has a complex page table, it is difficult to set up the debug UART with enabling it. It will be much easier to initialize the UART port after switching over to the straight-mapped page table. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: fix ROM boot mode for PH1-sLD3Masahiro Yamada2016-08-11-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4b50369fb535 ("ARM: uniphier: create early page table at run-time") broke the ROM boot mode for PH1-sLD3 SoC, because the run-time page table creation requires the outer cache register access but the page table in the sLD3 Boot ROM does not straight-map virtual/physical addresses. The idea here is to check the current page table to determine if it is a straight map table. If not, adjust the outer cache register base. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: refactor L2 zero-touching code in lowlevel_initMasahiro Yamada2016-08-11-26/+22
| | | | | | | | | | | | | | Here, the ldr pseudo-instruction falls into the ldr + data set. The register access by [r1, #offset] produces shorter code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: do not compile v7_outer_cache_disable if L2 is disabledMasahiro Yamada2016-08-11-1/+1
| | | | | | | | | | | | | | | | If CONFIG_UNIPHIER_L2CACHE_ON is undefined, the L2 cache is never enabled, so there is no need for v7_outer_cache_disable(). The weak stub avoids the compile error anyway. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: support prefetch and touch operations for outer cacheMasahiro Yamada2016-08-11-10/+57
| | | | | | | | | | | | | | | | | | | | The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as SRAM by locking ways. These functions will be used to transfer the trampoline code for SMP into the locked SRAM. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: refactor outer cache codeMasahiro Yamada2016-08-11-47/+52
| | | | | | | | | | | | | | | | | | Unify the range/all operation routines into the common function, uniphier_cache_maint_common(), and sync code with Linux a bit more. This reduces the code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-08-11-116/+885
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| * eth: asix88179: Add support for the driver modelAlban Bedel2016-08-09-0/+184
| | | | | | | | | | | | Adjust this driver to support driver model for Ethernet. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
| * eth: asix88179: Prepare supporting the driver modelAlban Bedel2016-08-09-28/+47
| | | | | | | | | | | | | | Change the prototype of a few functions to allow resuing the code for the driver model. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
| * eth: asix88179: Fix receiving on big endian systemAlban Bedel2016-08-07-1/+1
| | | | | | | | | | | | | | | | | | In asix_recv() the call to convert the endianess of the receive header was applied on the wrong variable. Instead of converting rx_hdr it converted pkt_hdr which is a pointer, and not yet initialiazed at this point. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
| * eth: asix88179: Add VID:DID for Cypress GX3 USB Ethernet AdapterAlban Bedel2016-08-07-0/+2
| | | | | | | | | | | | | | Added support for the Cypress GX3 SuperSpeed to Gigabit Ethernet Bridge Controller (VID_04b4/PID_3610). Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
| * arm: ls1021a: Enable CONFIG_DM_USB in defconfigsRajesh Bhagat2016-08-07-0/+4
| | | | | | | | | | | | | | Enables driver model flag CONFIG_DM_USB for LS1021A platform defconfigs. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * dm: ls1021a: dts: Update USB 3.0 node to support DM USBRajesh Bhagat2016-08-07-1/+1
| | | | | | | | | | | | Update USB 3.0 controller dts node in ls1021a.dtsi. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * usb: xhci: fsl: Add code to use CONFIG_DM_USBRajesh Bhagat2016-08-07-1/+82
| | | | | | | | | | | | Adds code to use driver model for USB XHCI FSL driver Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
generated by cgit v1.1 at 2024-09-04 23:34:18 +0000