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| * | fsl_*_serdes.c: Modify memset call in serdes_initTom Rini2015-12-13-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GCC 5.x does not like sizeof(array_variable) and errors out. Change these calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) * SERDES_PRCTL_COUNT (the number of array elements). Cc: York Sun <yorksun@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | Enable console log from earlyconsole in Linux bootargsPratiyush Mohan Srivastava2015-12-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Remove 115200 from "earlycon" to avoid loss of initial log messages during linux kernel 4.1 bootup Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043ardb: Add support for >2GB memoryShaohui Xie2015-12-13-4/+22
| | | | | | | | | | | | | | | | | | | | | | | | This patch also expose the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | fsl/ddr: updated ddr errata-A008378 for arm and power SoCsShengzhou Liu2015-12-13-3/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | fsl/errata: move fsl_errata.h to common directoryShengzhou Liu2015-12-13-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix soc.h path in fsl_errata.h] Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102x: add get_svr and IS_SVR_REV helperShengzhou Liu2015-12-13-0/+13
| | | | | | | | | | | | | | | Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | freescale: fman: make sure phy-handle property is big endianShaohui Xie2015-12-13-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When creating phy-handle property, an unsigned int value is created by fdt_create_phandle, and memcpy is used to get the value, since DTS is big endian, the value cannot be used directly on little endian SoCs, it should be converted by cpu_to_fdt32. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/ls2080ardb: Update DDR settings for four chip-select caseYork Sun2015-12-13-4/+12
| | | | | | | | | | | | | | | | | | | | | When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm, and 2T timing is enabled. Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/ls2080aqds: Update DDR settings for four chip-select caseYork Sun2015-12-13-4/+12
| | | | | | | | | | | | | | | | | | | | | When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm, and 2T timing is enabled. Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/ddr/fsl: Update timing config for heavy loadYork Sun2015-12-13-2/+24
| | | | | | | | | | | | | | | | | | | | | In case four chip-selects are all active, the turnaround times need to increase to avoid overlapping under heavy load. Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/ddr/fsl: Update workaround for A008511 for vref rangeYork Sun2015-12-13-7/+15
| | | | | | | | | | | | | | | | | | | | | The workaround requires different setting for range 1 vs 2. Also adjust timeout value for waiting for controller to be idle. Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/ddr/fsl: Update MR5 RTT parkYork Sun2015-12-13-4/+15
| | | | | | | | | | | | | | | | | | For four chip-selects enabled case, RTT is parked on all of them. Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/ddr/fsl: Update DDR4 MR6 for Vref rangeYork Sun2015-12-13-0/+3
| | | | | | | | | | | | | | | | | | MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec. Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/ddr/fsl: Update DDR4 RTT valuesYork Sun2015-12-13-2/+244
| |/ | | | | | | | | | | | | DDR4 has different RTT value and code according to JEDEC spec. Update the macros and options . Signed-off-by: York Sun <yorksun@freescale.com>
* | armv7: omap-common: Rework SPL board_mmc_init()Tom Rini2015-12-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the changes in a1e56cf the way that we had board_mmc_init() structured for OMAP parts (so that we always report device 0) are no longer functional. For now, make the case of booting from the second device initialize both devices (we have no devices that only have the second device as MMC). A further rework and consolidation of the functions should be done at a later date. Tested on Beaglebone Black (SD and eMMC boot). Reported-by: Vagrant Cascadian <vagrant@debian.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | spl: mmc: use block device number, not hard-coded 0Eric Nelson2015-12-14-3/+5
| | | | | | | | | | | | | | | | | | | | | | In order to support boot from multiple devices through board_boot_order, it's necessary to use the block number of a device. The use of a hard-coded 0 for the device number also creates a need to re-order block devices for use in SPL like this: http://git.denx.de/?p=u-boot.git;a=blob;f=board/freescale/mx6slevk/mx6slevk.c;hb=HEAD#l195 Signed-off-by: Eric Nelson <eric@nelint.com>
* | part: fix "part list ... -bootable varname" to use hexStephen Warren2015-12-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately U-Boot assumes that almost all numbers are in hex, including partition numbers passed to e.g. "load". So, the command "part list mmc 0 -bootable devplist" should use hex when writing partition numbers into $devplist, so they'll be correctly interpreted. Change-Id: I9a70b19749643876baadb45efbc3decaef8bfee2 Fixes: 0798d6fd4191 ("part: Add support for list filtering on bootable partitions") Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
* | tools: env: include compiler.hPeter Robinson2015-12-13-0/+1
| | | | | | | | | | | | | | With gcc 5.2 and later we get a bunch of "error: unknown type name" for 'uint8_t', 'uint32_t' and friends. Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
* | m68k: add private libgccangelo@sysam.it2015-12-13-0/+176
| | | | | | | | | | | | Add private libgcc Signed-off-by: Angelo Dureghello <angelo@sysam.it>
* | common: cli_hush: Fix up simple typoNishanth Menon2015-12-12-2/+2
| | | | | | | | | | | | | | Correct the spelling for character.. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | siemens,am33x: remove ddr3 delay workaroundEgli, Samuel2015-12-12-5/+0
| | | | | | | | | | | | Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Heiko Schocher <hs@denx.de>
* | am33xx,ddr3: fix ddr3 sdram configurationEgli, Samuel2015-12-12-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the DDR3 initialization procedure in order to comply with DDR3 standard. A 500 us delay is specified between the DDR3 reset and clock enable signal. Until now, this delay was not respected. Some DDR3 chips don't bother but the bigger the RAM becomes the more likely it seems that this delay is needed. We observed that DRAM > 256 MB from the manufacturer Samsung have an issue when the specification is not respected. Changes: 1) Add a 1 ms wait for L3 timeout error trigger 2) Don't delay DDR3 initialization Bit 31 of emif_sdram_ref_ctrl shouldn't be set because his suppresses the initialization of DDR3 Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Reviewed-by: James Doublesin <doublesin@ti.com> Cc: Tom Rini <trini@konsulko.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Heiko Schocher <hs@denx.de>
* | VxWorks: fixup MAC address for VxWorksMiao Yan2015-12-12-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | VxWorks 7 kernels retrieve 'local-mac-addr' from dtb and use that for NIC MAC address. As a result, when booting the same kernel image on multiple boards, there will be address conflicts. So fixup MAC address when booting VxWorks 7 kernels Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | stm32: Convert serial driver to DMKamil Lulko2015-12-12-119/+136
|/ | | | | | Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-12-11-419/+465
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| * spi: xilinx: Add new compatible stringsMichal Simek2015-12-11-1/+2
| | | | | | | | | | | | | | | | | | Add xlnx,xps-spi-2.00.a/b which is compatible string listed in the Linux kernel. Remove origin one which has no real background. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * mailmap: Update Jagan Teki's name and email addressJagan Teki2015-12-11-1/+5
| | | | | | | | | | | | | | | | | | Used quite different name's and e-mail address, all of them mapped to standard name and e-mail address. Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: Rename sf_ops.c to spi-flash.cJagan Teki2015-12-11-4/+5
| | | | | | | | | | | | | | | | | | Since all spi-flash core operations are moved into sf_ops.c then it's better to renamed as spi-flash.c Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: Use static for file-scope functionsJagan Teki2015-12-11-5/+5
| | | | | | | | | | | | | | | | Used static for file-scope functions in sf_probe.c Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: sf_probe: Remove spi_slave pointer argumentJagan Teki2015-12-11-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since spi_slave is a spi pointer in spi_flash{} then assign spi_slave{} pointer to flash->spi and remove spi_slave pointer argument to - spi_flash_probe_slave - spi_flash_scan Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: ops: Fix missing break on spansion read_barJagan Teki2015-12-11-0/+1
| | | | | | | | | | | | | | | | For assigning read_bar commands in spansion case, break is missing this patch add that break. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: Remove unneeded SST_BP and SST_WPJagan Teki2015-12-11-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | SST parts added on sf_params.c supports both SST_WR which consits of both BP and WP and there is a spi controller ich which supports only BP so the relevent _write hook set based on "slave->op_mode_tx" hence there is no respective change required from flash side hance removed these. Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: Remove unneeded header includesJagan Teki2015-12-11-5/+0
| | | | | | | | | | | | | | | | Removed unneeded header includes in sf_ops and sf_probe Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: Flash power up read-only based on idcode0Jagan Teki2015-12-11-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Using macro's for flash power up read-only access code leads wrong behaviour hence use idcode0 for runtime detection, hence the flash which require this functionality gets detected at runtime. Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: Use simple name for register access functionsJagan Teki2015-12-11-26/+26
| | | | | | | | | | | | | | | | | | | | Most of the register access function are static, so used simple name to represent each. Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: Fix MakefileJagan Teki2015-12-11-5/+1
| | | | | | | | | | | | | | | | This patch removes unneeded ifdef and fixed accordingly. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: Use static for file-scope functionsJagan Teki2015-12-11-23/+6
| | | | | | | | | | | | | | | | | | Use static for file-scope functions and removed them from header files. Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: probe: Code cleanupJagan Teki2015-12-11-41/+39
| | | | | | | | | | | | | | | | | | | | | | | | - Move bar read code below the bar write hance both at once place, hence it easy for #ifdef macro only once and readable. - Move read_cmd_array at top Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: Move read_id code to sf_opsJagan Teki2015-12-11-19/+20
| | | | | | | | | | | | | | | | | | | | | | read_id code is related to spi_flash stuff hence moved to sf_ops. Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: Move spi_flash_scan code to sf_opsJagan Teki2015-12-11-342/+357
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intension is that sf_ops should deals all spi_flash related stuff and sf_probe (which should renamed future) should be an interface layer for spi_flash versus spi drivers. sf_ops => spi_flash interface sf_probe => interface layer vs spi_flash(sf_probe) to spi drivers Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * sf: spi_flash_validate_params => spi_flash_scanJagan Teki2015-12-11-71/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename spi_flash_validate_params to spi_flash_scan as this code not only deals with params setup but also configure all spi_flash attributes. And also moved all flash related code into spi_flash_scan for future functionality addition. Tested-by: Jagan Teki <jteki@openedev.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: Kconfig: Fix correct target name for ZynqMPMichal Simek2015-12-11-1/+1
| | | | | | | | | | | | | | | | ZynqMP is using different symbol. Use correct one. Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * spi: zynq_spi: Add cadence compatible stringMichal Simek2015-12-11-0/+1
| | | | | | | | | | | | | | Extend compatible list table for cdns,spi-r1p6 compatible string. Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * imx: mx7dsabresd: Add QSPI supportPeng Fan2015-12-11-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support qspi flashes for mx7dsabresd 1. introduce pin mux settings 2. enable qspi clock 3. introduce related macro definitions Default QSPI is not enabled, since we need hardware rework to use QSPI, see SPF-28590, page 9: " QSPI signals are muxed with EPDC_D[7:0] When using QSPI: de-populate R388-R391, R396-R399 populate R392-R395, R299, R300 " After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi flashes can be deteced and read/erase/write. Log info: " => sf probe SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB => sf read 0x80000000 0 0x4000000 device 0 whole chip SF: 67108864 bytes @ 0x0 Read: OK => sf erase 0 0x4000000 SF: 67108864 bytes @ 0x0 Erased: OK => sf write 0x80000000 0 0x4000000 device 0 whole chip SF: 67108864 bytes @ 0x0 Written: OK " Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Adrian Alonso <aalonso@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * spi: ti_qspi: Fix SPI_3WIRE checking using modeJagan Teki2015-12-11-1/+1
| | | | | | | | | | | | | | | | | | SPI_3WIRE is spi mode not spi flags, so this patch fixed the spi-3wire checking throgh mode instead of flags. Cc: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: Get spi-3wire from dtsJagan Teki2015-12-11-0/+2
| | | | | | | | | | | | | | | | | | spi-3wire is used when SI/SO signals shared so get the same from dts node and assign to mode on slave plat->mode. Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2015-12-11-12/+33
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| * | dm: serial: Minor coding style cleanup of some commentsStefan Roese2015-12-10-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix incorrect comment alignments. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Fix Kconfig text to mention SPL in SPL_OF_TRANSLATEStefan Roese2015-12-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a remark about SPL to this Kconfig option. Otherwise its identitcal to the non-SPL version, which is confusing. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Michal Simek <michal.simek@xilinx.com>
| * | buildman: README: add links for toolchains not available on kernel.orgThomas Chou2015-12-10-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add links for toolchains not available on kernel.org. The sh4 toolchains from kernel.org dose not work for some boards, so use the sh from Sourcery. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-07-15 18:10:22 +0000