summaryrefslogtreecommitdiff
Commit message (Expand)AuthorAgeLines
...
* | x86: broadwell: Add power-control supportSimon Glass2016-03-17-0/+220
* | x86: broadwell: Add reference code supportSimon Glass2016-03-17-0/+114
* | x86: broadwell: Add an LPC driverSimon Glass2016-03-17-0/+110
* | x86: broadwell: Add a northbridge driverSimon Glass2016-03-17-0/+60
* | x86: broadwell: Add a SATA driverSimon Glass2016-03-17-0/+270
* | x86: broadwell: Add a pinctrl driverSimon Glass2016-03-17-0/+590
* | x86: broadwell: Add a PCH driverSimon Glass2016-03-17-0/+839
* | x86: Add basic support for broadwellSimon Glass2016-03-17-0/+1246
* | x86: dts: Update the pinctrl binding a littleSimon Glass2016-03-17-10/+11
* | x86: Add support for running Intel reference codeSimon Glass2016-03-17-1/+36
* | x86: Drop all the old pin configuration codeSimon Glass2016-03-17-334/+0
* | x86: gpio: Allow the pinctrl driver to set up the pin configSimon Glass2016-03-17-175/+15
* | x86: Add an ICH6 pin configuration driverSimon Glass2016-03-17-0/+219
* | x86: link: Add pin configuration to the device treeSimon Glass2016-03-17-0/+155
* | x86: Update microcode for secondary CPUsSimon Glass2016-03-17-2/+12
* | x86: ivybridge: Show microcode version for each coreSimon Glass2016-03-17-1/+2
* | x86: Record the CPU details when starting each coreSimon Glass2016-03-17-1/+20
* | x86: Move common MRC Kconfig options to the common fileSimon Glass2016-03-17-26/+62
* | x86: Allow I/O functions to use pointersSimon Glass2016-03-17-2/+10
* | x86: Add macros to clear and set I/O bitsSimon Glass2016-03-17-0/+22
* | x86: ivybridge: Drop sandybridge_early_init()Simon Glass2016-03-17-2/+0
* | x86: Move Intel Management Engine code to a common placeSimon Glass2016-03-17-369/+418
* | x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass2016-03-17-5/+5
* | x86: Move common CPU code to its own placeSimon Glass2016-03-17-76/+162
* | x86: Move common LPC code to its own placeSimon Glass2016-03-17-85/+167
* | x86: Add the root-complex block to common intel registersSimon Glass2016-03-17-7/+9
* | x86: Create a common header for Intel register accessSimon Glass2016-03-17-6/+22
* | x86: Move microcode code to a common locationSimon Glass2016-03-17-4/+8
* | x86: Move cache-as-RAM code into a common locationSimon Glass2016-03-17-1/+8
* | x86: cpu: Add functions to return the family and steppingSimon Glass2016-03-17-0/+24
* | x86: Allow use of serial soon after relocationSimon Glass2016-03-17-1/+8
* | input: i8042: Make sure the keyboard is enabledSimon Glass2016-03-17-0/+5
* | syscon: Avoid returning a device on failureSimon Glass2016-03-17-0/+1
* | dm: timer: Correct timer init ordering after relocationSimon Glass2016-03-17-1/+3
* | x86: broadwell: Add a few microcode filesSimon Glass2016-03-17-0/+2272
* | x86: Add comments to the SIPI vectorSimon Glass2016-03-17-0/+2
* | x86: Tidy up mp_init to reduce duplicationSimon Glass2016-03-17-53/+26
* | x86: Correct duplicate POST valuesSimon Glass2016-03-17-2/+2
* | x86: Add a script to aid code conversion from corebootSimon Glass2016-03-17-0/+26
* | x86: gpio: Correct GPIO setup orderingSimon Glass2016-03-17-1/+8
* | x86: dts: link: Add board ID GPIOsSimon Glass2016-03-17-0/+2
* | x86: dts: link: Move SPD info into the memory controllerSimon Glass2016-03-17-111/+110
* | x86: link: Add required GPIO propertiesSimon Glass2016-03-17-3/+9
* | x86: Add some more common MSR indexesSimon Glass2016-03-17-20/+43
* | x86: cpu: Make the vendor table constSimon Glass2016-03-17-1/+1
* | malloc_simple: Add a little more debuggingSimon Glass2016-03-17-2/+5
* | pci: Correct a few comments and nitsSimon Glass2016-03-17-3/+4
* | pci: Add functions to update PCI configuration registersSimon Glass2016-03-17-0/+80
* | gpio: Use const where possibleSimon Glass2016-03-17-10/+10
* | gpio: Add a function to obtain a GPIO vector valueSimon Glass2016-03-17-0/+30
generated by cgit v1.1 at 2024-08-21 09:02:42 +0000