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* mtd: vf610_nfc: remove read on SEQINStefan Agner2015-05-24-6/+8
| | | | | | | | | | | Since we do not support sub-page writes anyway, reading the page back to the controller on SEQIN command is not required. Remove the page read on SEQIN. However, the column/page values relevant to the SEQIN command, hence set the column/row address on SEQIN command. Signed-off-by: Stefan Agner <stefan@agner.ch>
* mtd: vf610_nfc: remove caching of page in bufferStefan Agner2015-05-24-10/+1
| | | | | | | | | | To improve performance we remember the current page in the buffer and avoid reading it twice. This implicit page cache increases complexity while does not increase performance in real world cases. This patch removes that feature. Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Stefan Agner <stefan@agner.ch>
* tools: mxsboot: Calculate ECC strength dynamicallyJörg Krause2015-05-24-13/+22
| | | | | | | | Calculating the ECC strength dynamically to be aligned with the mxs NAND driver and the Linux Kernel. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks> Reviewed-by: Marek Vasut <marex@denx.de>
* mtd: nand: mxs: Replace magic number for bits per ECC level with macroJörg Krause2015-05-24-4/+6
| | | | | Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks> Reviewed-by: Marek Vasut <marex@denx.de>
* mtd:mxs:nand calculate ecc strength dynamicallyPeng Fan2015-05-24-18/+12
| | | | | | | | | | Calculate ecc strength according oobsize, but not hardcoded which is not aligned with kernel driver Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <b37916@freescale.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
* nand/elbc: Memory leak fixRaghav Dogra2015-05-22-0/+1
| | | | | | | | | Freeing allocated memory to priv before returning from the function Signed-off-by: Raghav Dogra <raghav@freescale.com> [scottwood: removed unnecessary cast] Signed-off-by: Scott Wood <scottwood@freescale.com>
* nand: fix buffer alignment in new verification featureStephen Warren2015-05-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | | On systems with caches enabled, NAND I/O may need to flush/invalidate the cache during read/write operations. For this to work correctly, all buffers must be cache-aligned. Fix nand_verify*() to allocate aligned buffers. This prevents cache alignment warnings from being spewed when using U-Boot to write an updated version of itself to flash on NVIDIA Tegra Seaboard (after perturbation of stack/data layout in current u-boot-dm/next branch). I have validatd (executed) nand_verify(), but I don't think I've executed nand_verify_page_oob(); testing of that would be useful. Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Heiko Schocher <hs@denx.de> Cc: Scott Wood <scottwood@freescale.com> Fixes: 59b5a2ad83df ("nand: Add verification functions") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Scott Wood <scottwood@freescale.com>
* Merge git://git.denx.de/u-boot-netTom Rini2015-05-20-659/+267
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| * net: Remove all calls to net_random_ethaddr()Joe Hershberger2015-05-20-294/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | Remove the calls to net_random_ethaddr() that some boards and some drivers are calling. This is now implemented inside of net/eth.c Enable the feature for all boards that previously enabled it. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-By: Michael Walle <michael@walle.cc> (for the lsxl board part) Series-changes: 2 -Fixed bfin build errors
| * net: Remove all references to CONFIG_ETHADDR and friendsJoe Hershberger2015-05-19-317/+13
| | | | | | | | | | | | | | | | | | | | We really don't want boards defining fixed MAC addresses in their config so we just remove the option to set it in a fixed way. If you must have a MAC address that was not provisioned, then use the random MAC address functionality. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * net: Implement random ethaddr fallback in eth.cJoe Hershberger2015-05-19-1/+24
| | | | | | | | | | | | | | | | | | Implement the random ethaddr fallback in eth.c so it is in a common place and not reimplemented in each board or driver that wants this behavior. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * net: phy: Add support for all targets which requires MANUAL_RELOCMichal Simek2015-05-19-0/+16
| | | | | | | | | | | | | | | | | | | | | | Targets with CONFIG_NEEDS_MANUAL_RELOC do not use REL/RELA relocation (mostly only GOT) where functions aray are not updated. This patch is fixing function pointers passed to phy_register function. This patch was tested on Microblaze architecture. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net/phy: refactor RTL8211F initializationShengzhou Liu2015-05-19-8/+25
| | | | | | | | | | | | | | | | | | | | RTL8211F needs to enalbe TXDLY for RGMII during phy initialization, so move it to rtl8211f_config for early initialization. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: Update hardware MAC address if it changes in envJoe Hershberger2015-05-19-47/+48
| | | | | | | | | | | | | | | | | | | | | | | | When the ethaddr changes in the env, the hardware should also be updated so that MAC filtering will work properly without resetting U-Boot. Also remove the manual calls to set the hwaddr that was included in a few drivers as a result of the framework not doing it. Reported-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Michal Simek <michal.simek@xilinx.com>
| * net/phy: Add support for realtek RTL8211FShengzhou Liu2015-05-19-0/+85
| | | | | | | | | | | | | | | | | | RTL8211F has different registers from RTL8211E. This patch adds support for RTL8211F PHY which can be found on Freescale's T1023 RDB board. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | README.scrapyard: add entries for dead board, T4240EMU and sc3Masahiro Yamada2015-05-20-3/+5
| | | | | | | | | | | | | | | | | | Follow-up commit 7fc63cca611b (mpc85xx/T4240EMU: Remove T4240EMU board), and commit 27e721564591 (ppc4xx: Remove sc3 board), filling the blank fields. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | sunxi: Cache line size definitionPaul Kocialkowski2015-05-19-0/+3
| | | | | | | | | | | | | | | | | | | | | | Sunxi platforms use ARM Cortex A8, A7 and A15 (unsupported yet) CPU cores, which all have 64 bytes cache line size. This is required to e.g. enable USB gadget. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: VBUS detection function fixup in g_dnl_board_usb_cable_connectedPaul Kocialkowski2015-05-19-1/+1
| | | | | | | | | | | | | | | | | | | | sunxi_usbc_vbus_detect was renamed to sunxi_usb_phy_vbus_detect but g_dnl_board_usb_cable_connected was still using the old name, breaking the build when USB gadget is enabled. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Add ga10h v1.1 defconfigHans de Goede2015-05-19-0/+30
| | | | | | | | | | | | | | | | | | | | The ga10h is an 10" tablet with an A33 or A23 soc, 1G RAM, 8G or 16G nand, sdio wifi, 2 micro usb ports, 1 otg and 1 host and 1 micro sd slot. This commit adds a defconfig for the v1.1 pcb with an a33 soc. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: video: Fix lvds panel support for sun6i+Hans de Goede2015-05-19-1/+32
| | | | | | | | | | | | | | | | | | We've never tested the lvds panel support on sun6i+ SoCs until now, and unsurprisingly the lvds code needed some fixes to work on my ga10h A33 tablet with lvds panel. This makes the panel on that tablet actually work. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Make DRAM_ODT_EN Kconfig setting a boolHans de Goede2015-05-19-25/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make DRAM_ODT_EN Kconfig setting a bool, add a separate DRAM_ODT_CORRECTION setting for A23 SoCs and use DRAM_ODT_EN Kconfig everywhere instead of only in dram_sun4i.c and hardcoding odt_en elsewhere. Note this commit makes no functional changes for existing boards, its purpose is to allow changing the odt_en value on future A33 boards. For sun4i/sun5i/sun7i boards which set DRAM_ODT_EN=y (which no defconfigs currently do) this patch turns on odt for both the DQ and the DQS lines, whereas previously it was possibly (but not desirable) to turn odt on only for one of them by setting the in DRAM_ODT_EN option to 1 or 2 instead of 3. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
* | sunxi: Fix dram initialization not working on some a33 devicesHans de Goede2015-05-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | When porting the allwinner dram init code to u-boot we missed some code setting an extra bit when doing auto dram config. This commits add this bit, fixing dram init not working on the ga10h 10" a33 tablet which I'm bringing up atm. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: add support for UART2 on A23/A33Laurent Itti2015-05-19-0/+7
| | | | | | | | | | | | | | | | | | | | Add support for UART2 (2-pin version but note that RTS/CTS pins are available pn that port for possible future use), can be selected in config by using CONFIG_CONS_INDEX=3 Signed-off-by: Laurent Itti <laurentitti@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | console: Fix pre-console flushing via cfb_console being very slowHans de Goede2015-05-19-19/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On my A10 OlinuxIno Lime I noticed a huge (5+ seconds) delay coming from console_init_r. This turns out to be caused by the preconsole buffer flushing to the cfb_console. The Lime only has a 16 bit memory bus and that is already heavy used to scan out the 1920x1080 framebuffer. The problem is that print_pre_console_buffer() was printing the buffer once character at a time and the cfb_console code then ends up doing a cache-flush for touched display lines for each character. This commit fixes this by first building a 0 terminated buffer and then printing it in one puts() call, avoiding unnecessary cache flushes. This changes the time for the flush from 5+ seconds to not noticable. The downside of this approach is that the pre-console buffer needs to fit on the stack, this is not that much to ask since we are talking about plain text here. This commit also adjusts the sunxi CONFIG_PRE_CON_BUF_SZ to actually fit on the stack. Sunxi currently is the only user of the pre-console code so no other boards need to be adjusted. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | sunxi: Set SYS_MALLOC_CLEAR_ON_INIT to nHans de Goede2015-05-19-0/+3
| | | | | | | | | | | | | | | | | | We don't need this on sunxi, as we always use calloc or memset when initialised memory is required. Clearing this shaves some time of our boot time. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Pass serial number through ATAGPaul Kocialkowski2015-05-19-0/+21
|/ | | | | | Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Merge git://git.denx.de/u-boot-samsungTom Rini2015-05-18-66/+84
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| * exynos: clock: clean up checkpatch issuesMinkyu Kang2015-05-18-28/+37
| | | | | | | | Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * gpio: s3c: Fix the GPIO driverMarek Vasut2015-05-06-33/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPIO driver didn't correctly compute the bank offset from the GPIO number and caused random writes into the GPIO block address space. Fix the driver so it actually does the writes correctly. While at it, make use of the clrsetbits_le32() mechanisms. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * i2c: s3c: Implant support for S3C2440Marek Vasut2015-05-06-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | This is a matter of simple additional ifdefery to cater for the different register layout of the S3C2440 chip. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | arc: gitignore: ignore ARC DTBsMasahiro Yamada2015-05-18-0/+1
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | MAINTAINERS, git-mailrc: Update Jagan's name and e-mailJagan Teki2015-05-16-2/+2
| | | | | | | | Signed-off-by: Jagan Teki <jteki@openedev.com>
* | imx: ventana: use stack relocationTim Harvey2015-05-15-3/+2
| | | | | | | | | | | | | | | | | | Certain features we desire require a larger stack than is available by using iRAM (most notably for us, env_mmc). Relocate the stack to DRAM so that we can use these features. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | imx: ventana: add GSC boot watchdog disable to SPLTim Harvey2015-05-15-0/+3
| | | | | | | | | | | | | | If the SPL is to be used for Falcon mode then we need to make sure the SPL disable the GSC boot watchdog. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx: ventana: add gpio setup to SPLTim Harvey2015-05-15-0/+3
| | | | | | | | | | | | | | If the SPL is to be used for Falcon mode then we need to make sure it configures basic GPIO (iomux, padconf, and default output levels). Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx: ventana: use common uart and i2c setup functions in SPLTim Harvey2015-05-15-47/+5
| | | | | | | | | | | | | | Now that uart and i2c setup functions have been moved to common.c we can use these and remove code duplication. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx: ventana: detect pmic using i2c probe instead of board modelTim Harvey2015-05-15-5/+9
| | | | | | | | | | | | | | | | Avoid requiring board-model and probe pmic by its i2c address. This is in preparation for being able to call pmic_setup() from SPL and not need board type. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx: ventana: move GSC boot watchdog disable function to gsc.cTim Harvey2015-05-15-22/+30
| | | | | | | | | | | | Move the code that disables the GSC boot watchdog into gsc.c Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx: ventana: split out common functions between SPL and ubootTim Harvey2015-05-15-864/+933
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move shared functions used by both SPL and U-Boot to common.c: - setup_iomux_uart() and uart pad config - gpio pad config In the process also moved the following to common.c in preparation for calling it from the SPL: - split i2c setup into a shared function - move pmic init to setup_pmic() function to call directly from power_init_board() - split gpio setup into early (iomux and default pin config) and late (output configuration based on env) Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx: ventana: default msata/pci mux to pci before PCI enumerationTim Harvey2015-05-15-3/+4
| | | | | | | | | | | | | | | | PCI enumeration occurs early, before we fully configure our GPIO's. Make sure we steer the MSATA/PCI mux to PCI in board_init to ensure PCI is selected before enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx: ventana: fix pcie reset for GW522xTim Harvey2015-05-15-4/+4
| | | | | | | | | | | | | | The re-assignment of pcie_rst gpio for GW522x needs to occur earlier, before the PCI subsystem calls the toggle funciton. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx: ventana: config: enable Thermal supportTim Harvey2015-05-15-0/+4
| | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx: ventana: enable DM_SERIALTim Harvey2015-05-15-0/+10
| | | | | | | | | | | | mxc_serial supports DM so lets use it. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx: ventana: register gpio's with gpio_requestTim Harvey2015-05-15-20/+57
| | | | | | | | | | | | | | Prior to using a gpio a call to gpio_request() should be called to register it with the gpio subsystem. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx: ventana: config: enable driver modelTim Harvey2015-05-15-0/+7
| | | | | | | | | | | | Enable U-Boot Driver Model (DM). Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx: ventana: config: enable gpio commandTim Harvey2015-05-15-0/+1
| | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx: ventana: display SPL boot deviceTim Harvey2015-05-15-0/+23
| | | | | | | | | | | | Display what device the SPL will fetch uboot.img from Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx: ventana: set dtype env var to boot mediaTim Harvey2015-05-15-4/+4
| | | | | | | | | | | | | | Bootscripts for some distro's such as Android can benefit from knowing what boot media its script was loaded from. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | arm: mx6: ddr3: Remove dead codeNikolay Dimitrov2015-05-15-22/+0
| | | | | | | | | | | | | | imx6 mmdc supports data rates up to 1066 MT/s, so remove the code handling higher data rates. Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
* | mx6: Set shared override bit in PL310 AUX_CTRL registerFabio Estevam2015-05-15-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having bit 22 cleared in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. This was inspired by a patch from Catalin Marinas [1] and also from recent discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring suggested that bootloaders should initialize the cache. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html [2] https://lkml.org/lkml/2015/2/20/199 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
generated by cgit v1.1 at 2024-08-22 10:40:50 +0000