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* arm: mvebu: Make ECC support configurable on Armada XPStefan Roese2016-01-14-0/+10
| | | | | | | | | | | Currently, ECC support is enabled for all Armada XP boards. So the DDR3 driver tries to configure the controller with ECC support, even on boards without ECC. This patch makes this ECC optional which now can be configured on a board-per-board basis. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc>
* arm: mvebu: Add support for MV78260Stefan Roese2016-01-14-5/+29
| | | | | | | | | | This patch adds support for the dual core Armada XP variant, the MV78260. It has some minor differences to the 4-core MV78460, e.g. only 12 serdes lanes. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc>
* arm: mvebu: Don't use 0 as board ID as its used for the custom boardsStefan Roese2016-01-14-1/+1
| | | | | | | | | Using board ID 0 is reserved for the non-Marvell "custom" boards. So move the board ID's to reflect this. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc>
* arm: mvebu: Simplify code in setup_usb_phys() a bitStefan Roese2016-01-14-5/+5
| | | | | | | | Use the clrbits() / setbits() functions instead of clrsetbits() when bit are only cleared or set. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Don't disable cache at startup on Armada XP at allStefan Roese2016-01-14-12/+13
| | | | | | | | | | This patch leaces the cache configuration untouched for the AXP in the setup done by the BootROM. Resulting in the cache still being enabled at the startup of U-Boot. This leads to a slightly faster boot to the U-Boot prompt (or Linux of course). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Remove SYS_MALLOC_CLEAR_ON_INIT from DB-MV784MP-GP AXP boardStefan Roese2016-01-14-0/+1
| | | | | | | | By removing CONFIG_SYS_MALLOC_CLEAR_ON_INIT, the bootup time is a bit faster. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Don't call arch_cpu_init() from SPL at allStefan Roese2016-01-14-21/+8
| | | | | | | | | | | | | | This patch removes the call to arch_cpu_init() in the SPL U-Boot version. As SPL does not need all the configuration done in this function. And also does not need the reconfiguration of the internal register address to 0xf1000000. This will be done by the main U-Boot later on. This also fixes a problem with the timer not beeing initialized on AXP, as needed for the mdelay in the setup_usb_phys(). This will now only be called once in main U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Add v7_outer_cache_disable function for AXP & A38xStefan Roese2016-01-14-0/+8
| | | | | | | | | | | | Add functionality to correctly disable the L2 cache on the Armada XP and 38x platforms. Without this, booting into Linux on ClearFog (A38x) results in a hangup without any output on the serial console at all. Even with earlyprintk enabled. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Enable L2 cache on Armada XPStefan Roese2016-01-14-9/+25
| | | | | | | | | | | | | | | | | | Until now, the L2 cache was never enabled again in U-Boot. To get even better performance (bootup time), lets enable the L2 cache in U-Boot. This code was taken from the Linux kernel. A performance gain was measured on the DB-MV784MP-GP board by testing with tftpboot and sata commands. This patch also cleans up the L2 cache related code. And makes sure that the L2 cache is only disabled once. Please note that A38x still runs with L2 cache disabled. And needs to be enabled for this SoC in a separate patch if needed or desired. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: db-mv784mp-gp: Enable cache commandStefan Roese2016-01-14-0/+1
| | | | | | | | Th cache command can be useful sometimes. So lets enable it on the AXP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: db-mv784mp-gp: Enable common file-system supportStefan Roese2016-01-14-0/+7
| | | | | | | | This patch adds the common FS options to the Marvell AXP eval board. This includes EXT2, EXT4, FAT and VFAT. And of course the generic FS commands. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: db-mv784mp-gp: Switch from IDE to SATA supportStefan Roese2016-01-14-27/+7
| | | | | | | | | | | Enable the newly introduced SATA driver for the Marvell AXP with DMA support instead of the PIO-only IDE driver. This increases the transfer speed. And is also more in-line with the Armada 38x ports, which also use a SATA driver (AHCI) and the "sata" U-Boot commands. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* sata: Add SATA driver with DMA support for Marvell Kirkwood and Armada XPTor Krill2016-01-14-0/+1046
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a new SATA driver for the Marvell Kirkwood and Armada 370 / XP SoC's. This driver supports the SATA controller of some Mavell SoC's. Here a (most likely incomplete) list of the supported SoC's: - Kirkwood - Armada 370 - Armada XP This driver implementation is an alternative to the already available driver via the "ide" commands interface (drivers/block/mvsata_ide.c). But this driver only supports PIO mode and as this new driver also supports transfer via DMA, its much faster. Please note, that the newer SoC's (e.g. Armada 38x) are not supported by this driver. As they have an AHCI compatible SATA controller integrated. The original version of this driver was sent by Tor Krill to the U-Boot list a few years ago. Here the link: http://lists.denx.de/pipermail/u-boot/2010-June/073147.html Changes by Stefan: - Coding-style cleanup - Support for Armada XP added - MBUS window setup added - D-cache flush and invalidation added - works with dcache enabled on Armada XP - Removed mdelay() from ata_wait_register() and add timer based timeout detection to speed up the transfer Signed-off-by: Tor Krill <tor@excito.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Tom Rini <trini@konsulko.com>
* arm: mvebu: Add SolidRun ClearFog Armada 38x initial supportStefan Roese2016-01-14-0/+929
| | | | | | | | | | | | | | | | | | | | This patch adds basic support for the SolidRun ClearFog Armada 38x based board to mainline U-Boot. Supported interfaces / devices are: - DDR3 - UART - MMC - Ethernet port 0 (connected to dedicated PHY) - I2C The included DT source was taken from Russell King's ftp server: http://www.home.arm.linux.org.uk/~rmk/clearfog/ With only minor modifications, like the addition of some aliases and the "u-boot,dm-pre-reloc" property. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Move some defines to common include fileStefan Roese2016-01-14-11/+6
| | | | | | | | | This patch moves some config options to the mvebu common include file. Making it easier to not forget these defines for new boards. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
* net: mvneta: Convert to driver modelStefan Roese2016-01-14-167/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update this driver to support driver model. As all MVEBU boards using this driver are converted with this patch, the non-driver-model code can be removed completely. This is also the reason why this patch is quite big and includes a) the driver change and b) the platform change. As its not git-bisect save otherwise. With this conversion, some parameters are now extracted from the DT instread of using the config header defines. The supported properties right now are: PHY-mode ("phy-mode") and PHY-address ("reg"). The base addresses for the ethernet controllers can be removed from the header files as well. Please note that this patch also removes the E1000 network driver from some MVEBU config headers. This is necessary, as with DM_ETH configured and the e1000 driver enabled, the PCI driver also needs to support DM. But the MVEBU PCI(e) driver still needs to get ported to DM. When this is done, the E1000 driver can be enabled again. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Simon Glass <sjg@chromium.org>
* arm: mvebu: armada-388-gp.dts: Add ethernet aliasesStefan Roese2016-01-14-0/+2
| | | | | | | | Adding these aliases enables the update of the MAC addresses from within U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Add armada-xp-maxbcm.dts for maxbcm boardStefan Roese2016-01-14-2/+252
| | | | | | | | | This is needed for the upcoming ethernet DM conversion of the maxbcm board. The configuration of the PHY is then extracted from the DT instead of using the defines from the config header. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Add SPI driver model supportStefan Roese2016-01-14-4/+23
| | | | | | | | | | | | This patch enables the DM support for the SPI driver and the SPI NOR flash chips. Some MVEBU boards boot from SPI NOR, so adding the aliases and enabling CONFIG_DM_SEQ_ALIAS is needed here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Simon Glass <sjg@chromium.org>
* spi: kirkwood_spi.c: Add driver model supportStefan Roese2016-01-14-63/+159
| | | | | | | | | | | | | This patch adds driver model support to the kirkwood SPI driver. Which is also used on the MVEBU SoC's, now being converted to DM. Non-DM support is still available for the "older" platforms using this driver, like kirkwood. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org>
* spi: kirkwood_spi.c: Prepare for driver model supportStefan Roese2016-01-14-13/+28
| | | | | | | | | | | This patch prepares the Kirkwood SPI driver, also used on the MVEBU board (Armada XP / 38x), for the conversion to driver model. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org>
* arm: mvebu: Add DM and OF_CONTROL support to SPLStefan Roese2016-01-14-77/+66
| | | | | | | | | | | | | | | | | | | | | | This patch adds full DM support to the SPL on MVEBU. Currently only serial is supported. Other drivers will follow. This patch also adds the necessary config values for the DEBUG UART to the MVEBU defconfig files. This came in handy while implementing this DM support. Additionally, the mvebu specific SPL linker script is removed and this common one is used instead: arch/arm/cpu/u-boot-spl.lds This common linker script already handles all special cases. No need to reinvent the wheel for MVEBU here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Simon Glass <sjg@chromium.org>
* arm: mvebu: ddr: Fix compilation warningStefan Roese2016-01-14-17/+0
| | | | | | | | | | | | | | | | | | gcc 5.1 generates this new warning (for Armada 38x platforms): drivers/ddr/marvell/a38x/ddr3_debug.c: In function 'hws_ddr3_tip_read_training_result': drivers/ddr/marvell/a38x/ddr3_debug.c:177:40: warning: 'sizeof' on array function parameter 'result' will return size of 'enum hws_result (*)[1]' [-Wsizeof-array-argument] memcpy(result, training_result, sizeof(result)); ^ drivers/ddr/marvell/a38x/ddr3_debug.c:171:31: note: declared here u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]) ^ Since this functions is not referenced anywhere, lets just remove it. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu/kirkwood: Use common timer functionsStefan Roese2016-01-14-124/+22
| | | | | | | | | | By using the common timer functions for mvebu/kirkwood we can get rid of quite a lot of code. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Simon Guinot <simon.guinot@sequanux.org> Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
* part_dos.c: Don't wrap to negative after 2G sectorsStefan Monnier2016-01-13-16/+21
| | | | | | | | In order to support large IDE disks we need to make certain types be lbaint_t now. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Stefan Monnier <monnier@iro.umontreal.ca>
* image: check "bootm_low" and "bootm_size" if "initrd_high" is missingMasahiro Yamada2016-01-13-2/+1
| | | | | | | | | | | | | | | To boot Linux, we should prevent Initramdisk and FDT from going too high. Currently, boot_relocate_fdt() checks "fdt_high" environment first, and then falls back to getenv_bootm_mapsize() + getenv_bootm_low() if "fdt_high" is missing. On the other hand, boot_ramdisk_high() only checks "initrd_high" to get the address limit for the Initramdisk. We also want to let this case fall back to getenv_bootm_mapsize() + getenv_bootm_low(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* dm: core: Add a new api to get indexed device addressMugunthan V N2016-01-13-4/+38
| | | | | | | | | Add new api to get device address based on index. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Jagan Teki <jteki@openedev.com> [Rebased on master] Signed-off-by: Jagan Teki <jteki@openedev.com>
* power: pmic.h: Drop include <spi.h>Jagan Teki2016-01-13-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | include/power/pmic.h never used any generic spi code from include/spi.h, but this has been added in below commit. "dm: pmic: add implementation of driver model pmic uclass" (sha1: 4d9057e82be11a862db411c4867e859fe0d4ca2a) Adding functionalities in include/spi.h will trigger a build issue as this been added used in include/power/pmic.h Build issue on trats2 with adding BIT macro on spi.h: ---------------------------------------------------- CC lib/asm-offsets.s In file included from include/power/pmic.h:15:0, from include/power/max77686_pmic.h:11, from include/configs/trats2.h:212, from include/config.h:5, from include/common.h:18, from lib/asm-offsets.c:15: include/spi.h: In function 'spi_w8r8': include/spi.h:327:2: warning: implicit declaration of function 'BIT' [-Wimplicit-function-declaration] Cc: Simon Glass <sjg@chromium.org> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
* defconfig: am437x_sk_evm: enable spi driver modelMugunthan V N2016-01-13-0/+3
| | | | | | | | | | enable spi driver model for am437x_sk_evm as ti_qspi supports driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* arm: dts: am4372: add qspi register maps for memory mapMugunthan V N2016-01-13-1/+4
| | | | | | | | Add qspi memory map address to device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
* am43xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for splMugunthan V N2016-01-13-0/+2
| | | | | | | | | Since OMAP's spl doesn't support DM currently, do not define DM_SPI and DM_SPI_FLASH for spl build. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* defconfig: dra74_evm: enable spi driver modelMugunthan V N2016-01-13-0/+2
| | | | | | | | | | enable spi driver model for dra74_evm as ti_qspi supports driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* defconfig: dra72_evm: enable spi driver modelMugunthan V N2016-01-13-0/+2
| | | | | | | | | | enable mmc driver model for dra72_evm as ti_qspi supports driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* arm: dts: dra72-evm: add spi-flash comaptible for flashMugunthan V N2016-01-13-1/+1
| | | | | | | | | In U-Boot most flashes uses "spi-flash" as compatible to bind the device to flash driver, so adding "spi-flash" compatible to m25p80 node. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* arm: dts: dra7-evm: add spi-flash comaptible for flashMugunthan V N2016-01-13-1/+1
| | | | | | | | | In U-Boot most flashes uses "spi-flash" as compatible to bind the device to flash driver, so adding "spi-flash" compatible to m25p80 node. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* arm: dts: am437x-gp-evm: add spi-flash comaptible for flashMugunthan V N2016-01-13-1/+1
| | | | | | | | | In U-Boot most flashes uses "spi-flash" as compatible to bind the device to flash driver, so adding "spi-flash" compatible to m25p80 node. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* arm: dts: dra7: add qspi register maps for memory map and control moduleMugunthan V N2016-01-13-2/+5
| | | | | | | | Add qspi memory map and control module register maps to device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
* drivers: spi: ti_qspi: convert driver to adopt device driver modelMugunthan V N2016-01-13-0/+187
| | | | | | | | | adopt ti_qspi driver to device driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* dts: dra7: add spi alias for qspiMugunthan V N2016-01-13-0/+1
| | | | | | | | | add spi alias for qspi so that spi probes the device and driver successfully. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
* dra7xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for splMugunthan V N2016-01-13-0/+5
| | | | | | | | Since OMAP's spl doesn't support DM currently, do not define DM_SPI and DM_SPI_FLASH for spl build. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: Add support for dual and quad modeMugunthan V N2016-01-13-1/+39
| | | | | | | | | | spi bus can support dual and quad wire data transfers for tx and rx. So defining dual and quad modes for both tx and rx. Also add support to parse bus width used for spi tx and rx transfers. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* drivers: spi: ti_qspi: prepare driver for DM conversionMugunthan V N2016-01-13-126/+153
| | | | | | | Prepare driver for DM conversion. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* drivers: spi:ti_qspi: change ti_qspi_slave to ti_qspi_priv for driver model ↵Mugunthan V N2016-01-13-60/+60
| | | | | | | | | | | | conversion Changing the ti_qspi_priv structure and its instance names from to priv for driver mode conversion. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* drivers: spi: ti_qspi: do not hard code chip select for memory map configurationMugunthan V N2016-01-13-2/+2
| | | | | | | | | | | | To enable memory map in dra7xx, specific chip select must be written to control module register. But this hard coded to chip select 1, fixing it by writing the specific chip select value to control module register. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: Add SPI_TX_DUAL modeJagan Teki2016-01-13-1/+2
| | | | | | | | | Added SPI_TX_DUAL mode flag. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* sf: Make IO modes at last in read modesJagan Teki2016-01-13-4/+4
| | | | | | | | | | | | SLOW, FAST, DUAL, DUAL_IO, QUAD, QUAD_IO changed order to SLOW, FAST, DUAL, QUAD, DUAL_IO, QUAD_IO Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: Minor cleanupJagan Teki2016-01-13-16/+16
| | | | | | | | | | | | | | - Add comments on mode_rx - Tab space's Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: Use BIT macroJagan Teki2016-01-13-19/+19
| | | | | | | | | | | | | Used BIT macro like 1 << nr as BIT(nr) where nr is 0...n Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: Fix bit assignment with flagsJagan Teki2016-01-13-3/+3
| | | | | | | | | | | | | Fixed bit assignment with flags members on spi_slave{} Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: Move flags macro's to spi_slave{} membersJagan Teki2016-01-13-8/+7
| | | | | | | | | | | | | | This patch moves flags macro's to respective member position on spi_slave{}, for better readabilty and finding the respective member macro's easily. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
generated by cgit v1.1 at 2024-09-18 23:59:28 +0000