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| | * rockchip: Add support for veyron-mickey (Chromebit)Simon Glass2016-11-25-1/+396
| | | | | | | | | | | | | | | | | | | | | | | | This adds support for the Asus Chromebit, and RK3288-based device designed to plug directly into an HDMI monitor. The device tree file comes from Linux v4.8. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * rockchip: video: Avoid using u8 in the HDMI driverSimon Glass2016-11-25-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | It makes not sense using u8 to hold a value on a 32-bit or 64-bit machine. It can only bloat the code by forcing the compiler to mask the value. Change it to uint. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * rockchip: veyron: Adjust ARM clock after relocationSimon Glass2016-11-25-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | Update board_init() to increase the ARM clock to the maximum speed on veyron boards. This makes quite a large difference in performance. With this change, speed goes from about 750 DMIPS to 2720 DMIPs. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * rockchip: clk: Support setting ACLKSimon Glass2016-11-25-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Add basic support for setting the ARM clock, since this allows us to run at maximum speed in U-Boot. Currently only a single speed is supported (1.8GHz). Signed-off-by: Simon Glass <sjg@chromium.org>
| | * rockchip: Move jerry SDRAM settings into its own .dts fileSimon Glass2016-11-25-8/+11
| | | | | | | | | | | | | | | | | | | | | The SDRAM settings are not common across all veyron models. Move the current settings into Jerry's file. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * rockchip: veyron: Add a note about the SDRAM voltageSimon Glass2016-11-25-0/+6
| | | | | | | | | | | | | | | | | | | | | Add a comment to indicate that we are not supporting the PWM regulator yet. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * rockchip: Rename jerry files to veyronSimon Glass2016-11-25-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present we have a single rk3288-based Chromebook: chromebook_jerry. But all such Chromebooks can use the same binary with only device-tree differences. The family name is 'veyron', so rename the files accordingly. Also update the device-tree filename since this currently differs from Linux. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * rockchip: Move jerry to use of-platdataSimon Glass2016-11-25-4/+4
| | | | | | | | | | | | | | | | | | | | | Adjust jerry to use of-platdata like other rk3288 boards. This reduces the SPL size enough that it boots again. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * rockchip: video: Check for device in useSimon Glass2016-11-25-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check whether a display device is in use before using it. Add a comment as to why two displays cannot currently be used at the same time. This allows us to remove the device-tree change that disables vopb on jerry. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * video: Track whether a display is in useSimon Glass2016-11-25-1/+27
| | | | | | | | | | | | | | | | | | | | | Mark a display as in use when display_enable() is called. This can avoid a display being used by multiple video-output devices. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * video: Use cache-alignment in video_sync()Simon Glass2016-11-25-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Sometimes the frame buffer is not a multiple of the cache line size. Adjust the cache-flushing code to avoid cache warnings/errors in this case. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * spi: Add a debug() on bind failureSimon Glass2016-11-25-1/+4
| | | | | | | | | | | | | | | | | | | | | This is an uncommon error but we may as well have a debug() message when it happens. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * rockchip: spi: Honour the deactivation delaySimon Glass2016-11-25-0/+8
| | | | | | | | | | | | | | | | | | | | | This is not currently implemented. Add support for this so that the Chrome OS EC can be used on jerry. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * rockchip: spi: Add support for of-platdataSimon Glass2016-11-25-1/+35
| | | | | | | | | | | | | | | | | | Allow this driver to be used with of-platdata on rk3288. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * spi: Add of-platdata support to SPI and SPI flashSimon Glass2016-11-25-2/+13
| | | | | | | | | | | | | | | | | | | | | Some boards may want to use these subsystems with of-platdata in SPL. Add support for this by avoiding any device tree access in this case. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * stdio: Correct numbering logic in stdio_probe_device()Simon Glass2016-11-25-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code assumes that the devices are ordered corresponding to their alias value. But (for example) video1 can come before video0 in the device tree. Correct this, by always looking for device 0 first. After that we can fall back to finding the first available device. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * stdio: Correct code style nitsSimon Glass2016-11-25-2/+2
| | | | | | | | | | | | | | | | | | Fix a few code style nits in stdio_get_by_name(). Signed-off-by: Simon Glass <sjg@chromium.org>
| | * rockchip: Allow jerry to use of-platdataSimon Glass2016-11-25-0/+2
| | | | | | | | | | | | | | | | | | | | | This board always boots from SPI, so update the code to support that with of-platdata. The boot source is not currently available with of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * rockchip: video: Correct VOP clock selectionSimon Glass2016-11-25-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | This code incorrectly uses the oscillator. It should use the clock selected in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 135aa95 (clk: convert API to match reset/mailbox style)
| | * rockchip: video: Correct HDMI data source selectionSimon Glass2016-11-25-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code currently always selects the second source. It only worked because both sources are set up. With the change to only init video devices that are present in the stdout environment variable, this fails. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * dts: arm: rk3036: add usb vbus nodeKever Yang2016-11-25-4/+33
| | | | | | | | | | | | | | | | | | | | | add fix regulator node for usb vbus power control. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * config: rk3036: enable fix regulatorKever Yang2016-11-25-0/+1
| | | | | | | | | | | | | | | | | | | | | usb host vbus power is using gpio fix regulator, enable it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * config: rk3036: enable configs for USB HOSTKever Yang2016-11-25-0/+10
| | | | | | | | | | | | | | | | | | | | | rk3036 using dwc2 usb controller, need enable relate configs for it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * config: evb-rk3399: enable PWM_ROCKCHIPKever Yang2016-11-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | PWM_ROCKCHIP need to enable for PWM regulator, this config is missing during rebase and new patch set in previous submission. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * evb-rk3399: deduced the dram node size when space reservedKever Yang2016-11-25-1/+1
| | | | | | | | | | | | | | | | | | | | | The size dram node need to be deduced by the same amount of reserved space. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * arm: rockchip: Fix typo in ROCKCHIP_RK3288 helpAndreas Färber2016-11-25-1/+1
| | | | | | | | | | | | | | | | | | | | | UART,s -> UARTs, to avoid this spreading via copy&paste. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
| | * arm: dts: Fix Rockchip sort orderAndreas Färber2016-11-25-1/+1
| | | | | | | | | | | | | | | | | | | | | Sort rk3036 before rk3288. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
| | * power: regulator: Add limits checking while setting currentKeerthy2016-11-25-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the specific set ops functions are directly called without any check for min/max current limits for a regulator. Check for them and proceed. Signed-off-by: Keerthy <j-keerthy@ti.com> Fixed checking of current limits: Signed-off-by: Simon Glass <sjg@chromium.org>
| | * power: regulator: Add limits checking while setting voltageKeerthy2016-11-25-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the specific set ops functions are directly called without any check for voltage limits for a regulator. Check for them and proceed. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Fixed checking of voltate limits: Signed-off-by: Simon Glass <sjg@chromium.org>
| | * power: regulator: Introduce regulator_set_value_force functionKeerthy2016-11-25-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case we want to force a particular value on a regulator irrespective of the min/max constraints for testing purposes one can call regulator_set_value_force function. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | Merge git://git.denx.de/u-boot-fdtTom Rini2016-11-25-1/+1
| |\ \
| | * | MAINTAINERS: Fix syntax and update filename for FDTAndreas Färber2016-11-25-1/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | Let get_maintainers.pl pick up the new cmd/fdt.c. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-11-25-145/+2025
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/Kconfig
| | * | image-fit: Fix compiling error caused by autoconf.hYork Sun2016-11-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ec6617c3 includes autoconf.h in image-fit.c, causing conflict for board odroid-xu3 which overwrites CONFIG_SYS_BOARD in header file. Move the include higher and use linux/kconfig.h instead of generated/autoconf.h. Signed-off-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com>
| | * | armv7: ls1021aiot: Fixing SPL compiling issuesYork Sun2016-11-23-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To align with SPL change 38fed8ab and 693d4c9f, add Kconfig option CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to defconfig, and remove CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS. Signed-off-by: York Sun <york.sun@nxp.com> CC: Feng Li <feng.li_2@nxp.com>
| | * | armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabledAlison Wang2016-11-22-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8: fsl-layerscape: SMP support for loading 32-bit OSAlison Wang2016-11-22-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Spin-table method is used for secondary cores to load 32-bit OS. The architecture information will be got through checking FIT image and saved in the os_arch element of spin-table, then the secondary cores will check os_arch and jump to 32-bit OS or 64-bit OS automatically. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8: Support loading 32-bit OS in AArch32 execution stateAlison Wang2016-11-22-71/+416
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | arm: exynos7420: remove custome low level init functionThomas Abraham2016-11-22-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the custom low-level initialization function and reuse the default low-level initialization function. But this requires the ARMV8_MULTIENTRY config option to be enabled for Exynos7420. On Exynos7420, the boot CPU belongs to the second cluster and so with ARMV8_MULTIENTRY config option enabled, the 'branch_if_master' macro fails to detect the CPU as boot CPU. As a temporary workaround the CPU_RELEASE_ADDR is set to point to '_main'. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Alison Wang <alison.wang@nxp.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8/fsl-lsch3: Update code to release secondary coresPriyanka Jain2016-11-22-5/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8: fsl-layerscape: Add NXP LS2088A SoC supportPriyanka Jain2016-11-22-15/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QorIQ LS2088A SoC is built on layerscape architecture. It is similar to LS2080A SoC with some differences like 1)Timer controller offset is different 2)It has A72 cores 3)It supports TZASC module Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8: fsl-layerscape : Check SVR for initializing TZASCPriyanka Jain2016-11-22-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2080 SoC and its personalities does not support TZASC But other new SoCs like LS2088A, LS1088A supports TZASC Hence, skip initializing TZASC for Ls2080A based on SVR Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8: fsl-layerscape: Update TZASC registers typePriyanka Jain2016-11-22-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES are 32-bit regsiters. So while doing register load-store operations, 32-bit intermediate register, w0 should be used. Update x0 register to w0 register type. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8: lsch3: Use SVR based timer base address detectionPriyanka Jain2016-11-22-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8: lsch3: Add generic get_svr() in assemblyPriyanka Jain2016-11-22-3/+14
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8/fsl-layerscape: Update CONFIG_LS2080A to CONFIG_FSL_LSCH3Shengzhou Liu2016-11-21-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update CONFIG_LS2080A to CONFIG_FSL_LSCH3 to make those workaround implementing of erratum reusable for more SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8: fsl-layerscape: Add README for deploying QSPI imageYuan Yao2016-11-21-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Yuan Yao <yao.yuan@nxp.com> [YS: Reviese commit subject] Reviewed-by: York Sun <york.sun@nxp.com>
| | * | arm: ls1021a: improve the core frequency to 1.2GHZYuan Yao2016-11-21-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Change core clock to 1.2GHz in the configurations for SD and NAND boot. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8: ls2080aqds: fix SGMII repeater settingsShaohui Xie2016-11-21-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current value to check whether the PHY was configured has dependency on MC, it expects MC to start PCS AN, this is not true during boot up, so it should be changed to remove the dependency. The PHY's register space should be restore to default after accessing extended space. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | fsl: serdes: fix a deadloop issue for P4080Hou Zhiqiang2016-11-21-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This deadloop is introduced by commit: 71fe222 fsl: serdes: ensure accessing the initialized maps of serdes protocol deadloop detail: cpu_init_r => fsl_serdes_init => p4080_erratum_serdes_a005 => is_serdes_configured => fsl_serdes_init Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-07-15 21:36:59 +0000