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* test/fs: Check ext4 behaviour if dirent is first entry in directory blockStefan Brüns2016-09-23-0/+10
| | | | | | | | | | This is a regression test for a crash happening if the first dirent in the block matches. Code tried to access a predecessor entry which does not exist. The crash happened for any block, but "." is always the first entry in the first directory block and thus easy to check for. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
* test/fs: strip noise from filesystem code prior to checking resultsStefan Brüns2016-09-23-11/+15
| | | | | | | | ext4 and fat code emit some diagnostic messages during command execution. These additional lines force a match window size which strictly is not necessary. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
* test/fs: remove use of undefined WRITE_FILE variableStefan Brüns2016-09-23-6/+4
| | | | | | | The write file is created from $SMALL_FILE by appending ".w" on all other occurences in the code. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
* test/fs: Restructure file path specification to allow some flexibilityStefan Brüns2016-09-23-36/+22
| | | | | | | | Instead of providing the full path, specify directory and filename separately. This allows to specify intermediate directories, required for some additional tests. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
* cmd/fat: Do not crash on write when <bytes> is not specifiedStefan Brüns2016-09-23-2/+2
| | | | | | | | argc is checked, but is off by one. In case <bytes> is not specified, create an empty file, which is identical to the ext4write behaviour. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* fs/fat: Correct description of determine_fatent functionStefan Brüns2016-09-23-1/+3
| | | | | | | Current description does not match the function behaviour. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com>
* fs/fat: Do not write unmodified fat entries to diskStefan Brüns2016-09-23-12/+21
| | | | | | | | | | | | The code caches 6 sectors of the FAT. On FAT traversal, the old contents needs to be flushed to disk, but only if any FAT entries had been modified. Explicitly flag the buffer on modification. Currently, creating a new file traverses the whole FAT up to the first free cluster and rewrites the on-disk blocks. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* fs/fat: Remove two statements without effectStefan Brüns2016-09-23-4/+1
| | | | | | | | | | fatlength is a local variable which is no more used after the assignment. s_name is not used in the function, save the strncpy. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-09-22-26/+1391
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| * clk: rk3288: add PWM clock get rateKever Yang2016-09-22-0/+2
| | | | | | | | | | | | | | This patch add clk_get_rate for PWM device. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * clk: rk3399: add pmucru controller supportKever Yang2016-09-22-4/+173
| | | | | | | | | | | | | | | | pmucru is a module like cru which is a clock controller manage some PLL and module clocks. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rk3399: add a empty "sys_proto.h" header fileKever Yang2016-09-22-0/+10
| | | | | | | | | | | | | | | | driver/usb/dwc3/gadget.c need a "sys_proto.h" header file, add a empty one to make compile success. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: skip lowlevel_init processXu Ziyuan2016-09-22-8/+1
| | | | | | | | | | | | | | | | lowlevel_init() is never needed for rk3288, so drop it. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * board: evb-rk3399: enable usb 2.0 host vbus power on board_initKever Yang2016-09-22-1/+14
| | | | | | | | | | | | | | | | rk3399 using one gpio control signal for two usb 2.0 host port, it's better to enable the power in board file instead of in usb driver. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * config: evb-rk3399: enable fixed regulatorKever Yang2016-09-22-0/+2
| | | | | | | | | | | | | | This patch enable fixed regulator driver for rk3399 evb. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dts: rk3399-evb: add regulator-fixed for usb host vbusKever Yang2016-09-22-0/+6
| | | | | | | | | | | | | | | | rk3399 evb using one gpio to enable 5V output for both USB 2.0 host port, let's use fixed regulator for them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dts: rk3399: add dwc3_typec node for rk3399MengDongyang2016-09-22-0/+53
| | | | | | | | | | | | | | | | | | rk3399 has two dwc3 controller for type-C port, add the dts node and enable them. Signed-off-by: MengDongyang <daniel.meng@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * config: rk3399: add usb related configsMengDongyang2016-09-22-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch to enable configs for usb module - xhci - ehci - usb storage - usb net Signed-off-by: MengDongyang <daniel.meng@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Squashed in patch to move to Kconfig: https://patchwork.ozlabs.org/patch/672543/ Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * usb: host: add Kconfig for USB_XHCI_ROCKCHIPKever Yang2016-09-22-0/+7
| | | | | | | | | | | | | | Add a Kconfig for Rockchip xhci controller. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Marek Vasut <marex@denx.de>
| * rockchip: select DM_USB for rockchip SoCMengDongyang2016-09-22-0/+1
| | | | | | | | | | | | | | | | Select DM_USB to compatible with USB DM driver model. Signed-off-by: MengDongyang <daniel.meng@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * usb: xhci-rockchip: add rockchip dwc3 controller driverMengDongyang2016-09-22-0/+226
| | | | | | | | | | | | | | | | | | | | | | | | This patch add support for rockchip dwc3 controller, which corresponding to the two type-C port on rk3399 evb. Only support usb2.0 currently for we have not enable the usb3.0 phy driver and PD(fusb302) driver. Signed-off-by: MengDongyang <daniel.meng@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * rk3288: add arch_cpu_init for rk3288Kever Yang2016-09-22-0/+20
| | | | | | | | | | | | | | | | We do some SoC level one time setting initialization in arch_cpu_init. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rk_pwm: remove grf setting code from driverKever Yang2016-09-22-11/+0
| | | | | | | | | | | | | | | | | | We consider the grf setting for pwm controller select as the system operation instead of driver operation, move it to soc init, let's remove it from pwm driver first. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rk_pwm: use clock framework API to get module clockKever Yang2016-09-22-3/+14
| | | | | | | | | | | | | | | | | | This patch use clock API instead of hardcode for get pwm clock. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fix printf() to debug() nit: Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: use dummy byte only enable OF_PLATDATAXu Ziyuan2016-09-22-0/+4
| | | | | | | | | | | | | | | | | | Add a condition to determine the rk3288_sdram_channel size. This patch fixes read sdram_channel property failed from DT on rk3288 boards, which not enable OF_PLATDATA. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
| * dts: rk3399: add pinctrl for sdmmcKever Yang2016-09-22-0/+37
| | | | | | | | | | | | | | | | This patch add pinctrl for sdcard which may not be initialized before uboot. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rk3399: enable the pwm2/3 pinctrl in board initKever Yang2016-09-22-1/+30
| | | | | | | | | | | | | | | | | | There is no interrupt line for each PWM which used by pinctrl to get the periph_id, so it's not able to enable the default pinctrl setting by pinctrl framework, let's enable it at board_init(). Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * config: evb-rk3399: enable pinctrl driverKever Yang2016-09-22-0/+2
| | | | | | | | | | | | | | | | This patch enable rk3399 pinctrl driver and gpio driver which is sub-node of pinctrl. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * pinctrl: add driver for rk3399Kever Yang2016-09-22-0/+770
| | | | | | | | | | | | | | This patch add pinctrl driver for rk3399. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rk3399: syscon: add support for pmugrfKever Yang2016-09-22-0/+2
| | | | | | | | | | | | | | | | pmugrf is a module like grf which contain some of the iomux registers and other registers. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | ns16650: Make sure we have CONFIG_CLK set before using infrastructureTom Rini2016-09-22-15/+17
| | | | | | | | | | | | | | We cannot call on the CONFIG_CLK based clk_get_rate function unless CONFIG_CLK is set. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-09-22-285/+469
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| * | ARM: dts: uniphier: sync clock/reset controller nodes with LinuxMasahiro Yamada2016-09-23-181/+301
| | | | | | | | | | | | | | | | | | Sync device trees with Linux for easier DT life. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | clk: uniphier: allow to have clock node under syscon nodeMasahiro Yamada2016-09-23-9/+9
| | | | | | | | | | | | | | | | | | | | | To sync the DT binding with Linux, the register base must be taken from the parent syscon node. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | clk: uniphier: move U_BOOT_DRIVER entry to core codeMasahiro Yamada2016-09-23-75/+74
| | | | | | | | | | | | | | | | | | | | | | | | Move U_BOOT_DRIVER() entry from the data file (clk-uniphier-mio.c) to the core support file (clk-uniphier-core.c) because I do not want to repeat the driver boilerplate when I add more clock data. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | clk: uniphier: constify clock data arrays/structuresMasahiro Yamada2016-09-23-9/+9
| | | | | | | | | | | | | | | | | | Clarify these clock data are constant. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: add PLL init code for LD11 SoCMasahiro Yamada2016-09-23-7/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set the Cortex-A53 clock to the maximum frequency since it is running at 500MHz (SPLL/4) on startup Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: move CONFIG_SPL_* to defconfig or selectMasahiro Yamada2016-09-23-15/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As I repeated in the ML, I am unhappy with config entries with bare defaults. Kick them out of arch/arm/mach-uniphier/Kconfig. Currently, CONFIG_SPL_SERIAL_SUPPORT is not user-configurable (build fails without it), but it should be fixed later anyway, so I am moving CONFIG_SPL_SERIAL_SUPPORT to defconfigs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2016-09-22-208/+188
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| * | | configs: fsl: Move SPI/SPI-FLASH configs to defconfigJagan Teki2016-09-22-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved FSL_QSPI/SPI/SPI-FLASH configs from include/configs into respective used defconfigs. - CONFIG_FSL_QSPI - CONFIG_SPI_FLASH - CONFIG_SPI_FLASH_BAR - CONFIG_SPI_FLASH_STMICRO Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * | | spi: Kconfig: Move FSL_QSPI entry to non-dm placeJagan Teki2016-09-22-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since FSL_QSPI driver still supporting non-dm code better to move the Kconfig from DM undefined place. Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * | | sf: Move flags macro's to spi_flash_params{} membersJagan Teki2016-09-22-13/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves flags macro's to respective member position on spi_flash_params{}, for better readabilty and finding the respective member macro's easily. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * | | sf: Add CONFIG_SPI_FLASH_USE_4K_SECTORS in spi_flashJagan Teki2016-09-22-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CONFIG_SPI_FLASH_USE_4K_SECTORS in spi_flash code from header file. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * | | sf: Remove SECT_32KJagan Teki2016-09-22-16/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SECT_32K never used anywhere in the code. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * | | spi: Remove SPI_RX_FASTJagan Teki2016-09-22-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removed SPI_RX_FAST since default read for spi slaves are always 1-wire fast read. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * | | spi: Use mode for rx mode flagsJagan Teki2016-09-22-28/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make rx mode flags as generic to spi, earlier mode_rx is maintained separately because of some flash specific code. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * | | sf: Remove e_rd_cmd from param tableJagan Teki2016-09-22-117/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | e_rd_cmd is maintained separately for fastest read command code, since the read commands are computed normally this e_rd_cmd is not required in spi_flash_params table. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * | | sf: Simplify fastest read cmd codeJagan Teki2016-09-22-18/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fastest read command code look for fastest read command taking inputs from spi->mode_rx and flags from param table and controller mode_rx is always been a priority. Since mode_rx is always set from controller side this optimized code doesn't require much and this code required exctra overhead like 1) Maintain e_rx_cmd in param table 2) Maintain mode_rx in spi_slave {} Hence removed this code, and look for read command from normal spi->mode from spi_slave{} and params->flags Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * | | spi: ti_qspi: Remove unnecessary udelay for AM437xVignesh R2016-09-22-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This udelay() was added as an HACK and is no longer required. All read/write/erase operations work fine even without this delay. Hence, remove the udelay() call. Tested read/write/erase operation on AM437x SK. Also tested QSPI Boot. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | | spi: ti_qspi: use 128 bit transfer mode when writing to flashVignesh R2016-09-22-6/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TI QSPI has four 32 bit data registers which can be used to transfer 16 bytes of data at once. The register group QSPI_SPI_DATA_REG_3, QSPI_SPI_DATA_REG_2, QSPI_SPI_DATA_REG_1 and QSPI_SPI_DATA_REG is treated as a single 128-bit word for shifting data in and out. The bit at QSPI_SPI_DATA_REG_3[31] position is the first bit to be shifted out in case of 128 bit transfer mode. Therefore the first byte to be written to flash should be at QSPI_SPI_DATA_REG_3[31-25] position. Instead of writing 1 byte at a time when interacting with SPI NOR flash, make use of all the four registers so that 16 bytes can be transferred in one go. With this patch, the flash write speed increases from ~250KBs/ to ~650KB/s on DRA74 EVM. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
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