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* input: Allow repeat filtering to be disabledSimon Glass2015-11-19-2/+26
| | | | | | | | | | | | | Generally the input library handles processing of a list of scanned keys. Repeated keys need to be generated based on a timer in this case, since all that is provided is a list of keys current depressed. Keyboards which do their own scanning will resend codes when they want to inject a repeating key. Provide a function which tells the input library to accept repeating keys and not to try to second-guess the caller. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* input: Add a function to add a keycode to the existing setSimon Glass2015-11-19-4/+62
| | | | | | | | | | | | | | | | | | | | | | Most keyboards can be scanned to produce a list of the keycodes which are depressed. With the i8042 keyboard this scanning is done internally and only the processed results are returned. In this case, when a key is pressed, a 'make' code is sent. When the key is released a 'break' code is sent. This means that the driver needs to keep track of which keys are pressed. It also means that any protocol error can lead to stuck keys. In order to support this type of keyboard, add a function when can be used to provide a single keycode and either add it to the list of what is pressed or remove it from the list. Then the normal input_send_keycodes() function can be used to actually do the decoding work. Add debugging to display the ASCII characters written to the input queue also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* input: Add a few more keyboard keycodesSimon Glass2015-11-19-3/+3
| | | | | | | The slash and * are missing from the keycode tables. Add these so that these keypad keys can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
* input: Correct keycode for Ctrl-YSimon Glass2015-11-19-1/+1
| | | | | | This code is currently incorrect, perhaps due to a typo. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* i8042: Adjust keyboard init to assume successSimon Glass2015-11-19-10/+9
| | | | | | | | | Modify i8042_kbd_init() so that the normal pass is sucessful init and failure exits early. This will make the code easier to extend and is easier to read. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* i8042: Adjust kbd_reset() to collect all failuresSimon Glass2015-11-19-5/+8
| | | | | | | Rather than lots of 'return' statements, use goto to a single return. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* i8042: Use functions to handle register accessSimon Glass2015-11-19-31/+44
| | | | | | | | | | | | | At present the register access in kbd_reset() is quite primitive. This makes it hard to follow. Create functions to read and write data, both to a single register, and via the command/data approach. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-on: Intel Crown Bay and QEMU Tested-by: Bin Meng <bmeng.cn@gmail.com>
* video: Drop unused console functionsSimon Glass2015-11-19-87/+9
| | | | | | | | | | | | | | | | | | CONFIG_CONSOLE_CURSOR, CONFIG_SYS_CONSOLE_BLINK_COUNT and CONFIG_CONSOLE_TIME are not used by any board. The implementation is not great and stands in the way of a refactor of i8042. Drop these for now. They can be re-introduced quite easily later, perhaps with driver-model real-time-clock (RTC) support. When reintroducing, it might be useful to make a few changes: - Blink time would be more useful than blink count - The confusing #ifdefs should be avoided - The time functions should support driver model - It would be best keyed off console_tstc() or some similar idle loop rather than a particular input driver (i8042 in this case) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: cros_ec: Convert cros_ec keyboard driver to driver modelSimon Glass2015-11-19-95/+62
| | | | | | | | Adjust the cros_ec keyboard driver to support driver model. Make this the default for all Exynos boards so that those that use a keyboard will build correctly with this driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: tegra: Convert keyboard driver to driver modelSimon Glass2015-11-19-134/+112
| | | | | | | | Adjust the tegra keyboard driver to support driver model, using the new uclass. Make this the default for all Tegra boards so that those that use a keyboard will build correctly with this driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: stdio: Plumb in the new keyboard uclassSimon Glass2015-11-19-1/+30
| | | | | | | | | | | When driver model is used for keyboards we must scan the available keyboards and register them with stdio. Add code to do this. At some point (once LCD/video is converted) we should be able to convert stdio to driver model and avoid these dual data structures. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cros_ec: Use udevice instead of cros_ec_dev for keyboard functionsSimon Glass2015-11-19-9/+13
| | | | | | | In preparation for converting the cros_ec keyboard driver to driver model, adjust the cros_ec functions it will use to use a normal struct udevice. Signed-off-by: Simon Glass <sjg@chromium.org>
* input: Add the keycode translation tables separatelySimon Glass2015-11-19-9/+30
| | | | | | | | | Require the caller to add the keycode translation tables separately so that it can select which ones to use. In a later patch we will add the option to add German tables. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* input: Return -ENOSPC when there is not spaceSimon Glass2015-11-19-1/+2
| | | | | | | Return a useful error instead of -1 when something goes wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* input: Add a device pointer to the input configSimon Glass2015-11-19-0/+1
| | | | | | | | | | | | The read_keys() method in input is passed a struct input_config. Add a device pointer there so that we can find out the device that is referred to with driver model. Once all drivers are converted we can update the input structure to use driver model instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: input: Create a keyboard uclassSimon Glass2015-11-19-6/+181
| | | | | | | | | Add a uclass for keyboard input, mirroring the existing stdio methods. This is enabled by a new CONFIG_DM_KEYBOARD option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: usb: Add support for USB keyboards with driver modelSimon Glass2015-11-19-8/+57
| | | | | | | | Switch USB keyboards over to use driver model instead of scanning with the horrible usb_get_dev_index() function. This involves creating a new uclass for keyboards, although so far there is no API. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Turn on CONFIG_DEBUG_UART_NS16550 in defconfigsAriel D'Alessandro2015-11-19-0/+2
| | | | | | | | | | No UART driver was specified in defconfig, thus DEBUG_UART_ALTERA_JTAGUART was incorrectly selected by default since commit 220e8021af96741bd7149ca9895e1f0c8a38d0bb added a new Altera UART driver. Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-11-19-121/+25
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| * sf: Correct flash->flags for SST flashBin Meng2015-11-18-4/+5
| | | | | | | | | | | | | | | | flash->flags for SST flash should be updated for both DM and non-DM flash drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * spi: sf_ops: Check the return value from spi_flash_cmd_read_status()Fabio Estevam2015-11-18-2/+8
| | | | | | | | | | | | | | | | | | | | | | We should check the return value from spi_flash_cmd_read_status() and propagate it in the case of error. This fixes a defect caught by Coverity. Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * sf: Add lock ops for SST SPI NOR flashFabio Estevam2015-11-18-3/+5
| | | | | | | | | | | | | | | | | | | | SST SPI NOR flash has the same locking programming bits as ST Micro - added support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> [Minor change on commit message] Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * sf: Remove eeprom_m95xxx test driverJagan Teki2015-11-18-112/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The relevent boards which used this driver got zapped in previous release and the driver is never used in the code and also it doesn't use/do any spi-flash operations. Commit details for relevent removed boards: "ARM: at91: remove non-generic boards" (sha1: f6b42c140387589ded24749781ce565571092eac) Cc: Tom Rini <trini@konsulko.com> Cc: Albin Tonnerre <albin.tonnerre@free-electrons.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * ARM: am43xx: Enable QUAD read and EDMA support for ti_qspiVignesh R2015-11-17-0/+5
| | | | | | | | | | | | | | | | | | Enable TI_EDMA3 and QUAD read support for ti_qspi on am43xx, this increases read performance to 4 MB/s. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * spi: ti_qspi: Add dummy readl for bus syncVignesh R2015-11-17-0/+2
| | | | | | | | | | | | | | | | | | | | | | Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure bus sync. Without this device's CS is not deactivated reliably leading to failure to enumerate flash or failure to set quad enable bit on Macronix flash present on am437x-sk and am437x-idk evms. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-11-19-39/+638
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| * | common: mii: Do not allow to exceed max phy limitMichal Simek2015-11-19-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Phy can have addresses 0-31. Check this boundary to ensure that user can't call commands on phy address 32 and more. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | zynq: sdhci: Define max clock by macroMichal Simek2015-11-19-1/+6
| | | | | | | | | | | | | | | | | | | | | zc1571 with silicon can operate on 200MHz maximum frequency. Setup this frequency by default and fix setting for ep108. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | net: zynq: Fix MDC setting for zynqMichal Simek2015-11-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on spec: "MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations)" Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47 which is above of 2.5MHz. Using 48 divider will give us correct setting according spec (111/48=2.31). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: zynq: Remove unused MDCCLKDIV2 macroMichal Simek2015-11-19-1/+0
| | | | | | | | | | | | | | | | | | | | | Driver cleanup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: zynq: Fix mdc clock division setting for 100Mbit/sMichal Simek2015-11-19-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using set and clear macro is incorrect because it is not overwritting origin mdc clock division setup. For example origin setup is 8(0b001) and new setup is 64(0b100) which means 0b101 is setup which is 96 divider. Using writel to rewrite all setting like for 1000Mbit/s case. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: zynq: Wait till packet is sentMichal Simek2015-11-19-1/+32
| | | | | | | | | | | | | | | | | | Wait till BD is processed to ensure that packet was sent successfully. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | net: zynq: Disable secondary queuesEdgar E. Iglesias2015-11-19-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zynq has no priority queues. ZynqMP has one priority queue and this change is required to get ethernet working. This patch was not needed on ep108 for uknown reason even it should be used. Tested on Zynq and ZynqMP. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | net: zynq: Add dummy packet to fix packet duplication issueMichal Simek2015-11-19-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Target is duplicating packets. IP prefetches another BD and process it when the first one is sent. Adding one dummy BD to the chain fix the problem with packet duplication. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: zynq: Do not report TX underrunMichal Simek2015-11-19-2/+0
| | | | | | | | | | | | | | | Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: zynq: Setup BD when structures are filledMichal Simek2015-11-19-3/+3
| | | | | | | | | | | | | | | | | | | | | Fix incorrect sequence in BD handling. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: zynq: Allocate BD_SPACE in connection to RX_BUFMichal Simek2015-11-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | BD_SEPRN_SPACE should not have hard coded value and it will be calculated based on the number of buffer descriptors that we would like to use. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: zynq: Fix clearing statisticMichal Simek2015-11-19-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | Previous loop was completely bogus. Iterration should go just over statistic counters. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: zynq: Extend register description with offsetsMichal Simek2015-11-19-15/+15
| | | | | | | | | | | | | | | | | | | | | Extend comments with register offset to help with debuggging. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: zynq: Add support for different PHY interface typesMichal Simek2015-11-19-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MII is setup by default for all cases. The most of boards are using RGMII but PHY drivers are not doing any specific setting that's why MII setting was working fine. With TI DP83867 is necessary to setup paramaters based on interface type. Use one setting per board for it which is something what will be removed when driver is moved to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: zynq: Add debug message to phyread/phywriteMichal Simek2015-11-19-1/+12
| | | | | | | | | | | | | | | | | | | | | Add debug messages to phyread/write to help with PHY debug. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | ARM: zynq: Add target for building bootable SPL image for ZynqNathan Rossi2015-11-19-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a build target to generate 'boot.bin' which includes SPL. This is used by the platforms BootROM to load SPL directly. This change also conditionally changes what the 'boot.bin' target generates depending on the SoC. Leaving the behaviour unchanged for the AT91 targets. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Cc: Tom Rini <trini@konsulko.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | tools: zynqimage: Add Xilinx Zynq boot header generation to mkimageNathan Rossi2015-11-19-1/+261
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As with other platforms vendors love to create their own boot header formats. Xilinx is no different and for the Zynq platform/SoC there exists the "boot.bin" which is read by the platforms bootrom. This format is described to a useful extent within the Xilinx Zynq TRM. This implementation adds support for the 'zynqimage' to mkimage. The implementation only considers the most common boot header which is un-encrypted and packed directly after the boot header itself (no XIP, etc.). However this implementation does take into consideration the other fields of the header for image dumping use cases (vector table and register initialization). Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM64: zynqmp: Enable TI phy by defaultMichal Simek2015-11-19-0/+1
| | | | | | | | | | | | | | | | | | Enable TI phy for Xilinx ZynqMP platform. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | net: phy: Add support for Texas Instruments DP83867Edgar E. Iglesias2015-11-19-0/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | Code is taken from Linux kernel driver (v4.2). Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | ARM: zynq: Choose boot image based on OF_SEPARATE macroMichal Simek2015-11-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | OF_CONTROL is enabled by default for all Zynq boards. The difference between two boot images is done by OF_SEPARATE or OF_EMBED macros. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | zynqmp: mp: Add support for booting R5 from any addressMichal Simek2015-11-19-3/+35
| | | | | | | | | | | | | | | | | | | | | Put jump trampoline to TCM at 0 and setup R5 reset address to 0. Jump trampoline ensures that jump to the right location. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-11-19-43/+73
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| * | | dm: sf: Add support for all targets which requires MANUAL_RELOCMichal Simek2015-11-19-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is follow up patch based on "dm: Add support for all targets which requires MANUAL_RELOC" (sha1: 484fdf5ba058b07be5ca82763aa2b72063540ef3) to update function pointers for DM. Using post_bind is not ideal but it is one on current option what can be used. Variable reloc_done has to be used do not call relocation after every bind. Maybe new core functions should be introduced for this case. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | dm: core: Add missing entries for manual relocationMichal Simek2015-11-19-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patches: "dm: core: Add a post_bind method for parents" (sha1: 0118ce79577f9b0881f99a6e4f8a79cd5014cb87) "dm: core: Add a uclass pre_probe() method for devices" (sha1: 02c07b3741f1b825934b1a6eb8f23530532dc426) "dm: core: Allow the uclass to set up a device's child after binding" (sha1: 081f2fcbd9a95ba10677065359791f8fea3f8c58) "dm: core: Allow uclass to set up a device's child before it is probed" (sha1: 83c7e434c9dd3ca81f8b763e23c1881b973bcf2f) Adds new entries to struct driver and struct uclass_driver without extending code for manual relocation. This patch fixes it for all architectures which requires MANUAL_RELOC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-09-18 17:52:01 +0000