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* rockchip: Explicitly set CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LENSjoerd Simons2015-12-01-0/+2
| | | | | | | | | | | | | | Now that u-boot relocates the malloc area in SPL to SDRAM, with the malloc area sitting below the SPL_STACK_R_ADDR the SPL_STACK_R_MALLOC_SIMPLE_LEN needs to be set explicitly for rockchip as its SPL_STACK_R_ADDR (512kb) is smaller then STACK_R_MALLOC_SIMPLE_LEN (1Mb). Using the same value as SYS_MALLOC_F_LEN (8kb) is enough to load u-boot from SD card. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
* Revert "rockchip: Reconfigure the malloc based to point to system memory"Sjoerd Simons2015-12-01-7/+0
| | | | | | | | | | | This patch was merged shortly before the v2015.10 as a minimal fix for booting on rockchip. Now that the patch series from Hans to do the relocation in generic code has been merged it can be dropped. This reverts commit b1f492ca9e0c090209824ff36456d4f131843190. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: move SYS_MALLOC_SIMPLE to mach-rockchip KconfigAriel D'Alessandro2015-12-01-8/+3
| | | | | | | | | | | | | | | | | Commit 1eb0c03c2198a7ec9de456b83dacdc4831b96cbf added SPL_SYS_MALLOC_SIMPLE Kconfig option and changed the way it is evaluated. Thus, the definitions of CONFIG_SYS_MALLOC_SIMPLE in rk3***_common.h board configs are now incorrect because CONFIG_SPL_BUILD is enabled so CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) will look for SPL_SYS_MALLOC_SIMPLE instead of SYS_MALLOC_SIMPLE. This commit fix this enabling SPL_SYS_MALLOC_SIMPLE with the new Kconfig option by default in rockchip-mach. Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: doc: show packet rk3036 uboot imagehuang lin2015-12-01-0/+11
| | | | | | | | | | show how to packet rk3036 uboot image and boot from SD Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Series-to: u-boot Series-version: 8 Series-cc: Lin Huang <hl@rock-chips.com>
* rockchip: Add support for rk's second level loaderJeffy Chen2015-12-01-17/+14
| | | | | | | | | | The Rockchip boot ROM could load & run an initial spl loader, and continue to load a second level boot-loader(which stored right after the initial loader) when it returns. Modify idblock generation code to support it. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Add max spl size & spl header configsJeffy Chen2015-12-01-8/+40
| | | | | | | | | | | | | | | Our chips may have different max spl size and spl header, so we need to add configs for that. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, Added $(if...) to tools/Makefile to fix widespread build breakage Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, - Add $(if...) to tools/Makefile to fix widespread build breakage
* rockchip: Add basic support for evb-rk3036 boardhuang lin2015-12-01-1/+171
| | | | | | | | | | | | | | This add some basic files required to allow the board to dispaly serial message and can run command(mmc info etc) Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Moved board Kconfig fragment from previous patch into this one to fix build error: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - moved board Kconfig fragment from previous patch into this one
* rockchip: rk3036: Add core Soc start-up codehuang lin2015-12-01-2/+207
| | | | | | | | | | | | | | | | rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
* rockchip: add rk3036 sdram driverhuang lin2015-12-01-0/+1107
| | | | | | | add rk3036 sdram driver so we can set up sdram in SPL Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: add early uart driverhuang lin2015-12-01-0/+108
| | | | | | | | add early uart driver so we can print debug message in SPL stage Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: mmc: get the fifo mode and fifo depth property from dtshuang lin2015-12-01-4/+18
| | | | | | | | rk3036 mmc do not have internal dma, so we use fifo mode when read and write data, we get the fifo mode and fifo depth property from dts, pass to dw_mmc driver. Signed-off-by: Lin Huang <hl@rock-chips.com>
* rockchip: mmc: use non-removable property to distinguish emmc and sdcard ↵huang lin2015-12-01-2/+3
| | | | | | | | | | register emmc and sdcard have different register address, use non-removeable property to distinguish them. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* mmc: dw_mmc: support fifo mode in dwc mmc driverhuang lin2015-12-01-18/+72
| | | | | | | | some soc(rk3036 etc) use dw_mmc but do not have internal dma, so we implement fifo mode to read and write data. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* mmc: dw_mmc: move data transfer as a separate functionhuang lin2015-12-01-28/+37
| | | | | | | | the data transfer seem to long in the dwmci_send_cmd function, so move this block as a separate funciton. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: Add pinctrl driverhuang lin2015-12-01-0/+286
| | | | | | | Add a driver which support pin multiplexing setup for rk3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: Add a simple syscon driverhuang lin2015-12-01-1/+22
| | | | | | | Add a driver that provides access to system controllers Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: Add Soc reset driverhuang lin2015-12-01-0/+55
| | | | | | | | We can reset the Soc using some CRU (clock/reset unit) register. Add support for this. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: Add header files for GRFhuang lin2015-12-01-0/+493
| | | | | | | GRF is the gereral register file. Add header files with register definitions. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: Add clock driverhuang lin2015-12-01-0/+583
| | | | | | | | Add a driver for setting up and modifying the various PLLs, peripheral clocks and mmc clocks on RK3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Bring in RK3036 device tree file includes and bindingshuang lin2015-12-01-0/+613
| | | | | | | | | Since rk3036 device tree file still in reviewing, bring it from https://patchwork.kernel.org/patch/7203371/ and add some aliases we need in uboot Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: serial driver support rk3036huang lin2015-12-01-0/+1
| | | | | Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: core: Add SPL Kconfig for REGMAP and SYSCONhuang lin2015-12-01-2/+27
| | | | | | | | Add SPL Kconfig for REGMAP and SYSCON, so REGMAP and SYSCON can remove from SPL stage. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: add config decide whether to build common.chuang lin2015-12-01-1/+4
| | | | | | | | some rockchips soc will not use uclass in SPL stage, so define config to decide whether to build common.c Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rename board-spl.c to rk3288-board-spl.chuang lin2015-12-01-1/+1
| | | | | | | | since different rockchip soc need different spl file, so rename board-spl.c. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfighuang lin2015-12-01-3/+3
| | | | | | | | | since different rockchip SOC have different size of SRAM, So the size SYS_MALLOC_F_LEN may different, so move this config to rk3288 own Kconfig Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: add timer driverhuang lin2015-12-01-20/+75
| | | | | | | | some rockchip soc will not include lib/timer.c in SPL stage, so implement timer driver for some soc can use us delay function in SPL. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: firefly: Save the environment on SD cardSjoerd Simons2015-12-01-1/+9
| | | | | | | | Save the environment on the SD card for Firefly in the empty space between the SPL and the u-boot image. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Also load the initrd below 512MSjoerd Simons2015-12-01-0/+1
| | | | | | | | | Similar to load an fdt, when loading an initrd about the 512Mb mark things seem to break. For now force loading below 512Mb until the reason why this fails has been determined/solved. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Disable PCI compatibility functions by defaultSimon Glass2015-12-01-5/+42
| | | | | | | | | We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Convert 'pci' command to driver modelSimon Glass2015-12-01-6/+128
| | | | | | | | | Adjust this command to use the correct PCI functions, instead of the compatibility layer. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Move PCI header output code into its own functionSimon Glass2015-12-01-6/+11
| | | | | | | | We want to share this code with the driver model version, so put it in a separate function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Use a separate 'dev' variable for the PCI deviceSimon Glass2015-12-01-5/+8
| | | | | | | | | In the 'pci' command, add a separate variable to hold the PCI device. When this code is converted to driver model, this variable will be used to hold a struct udevice instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Use common functions to read/write configSimon Glass2015-12-01-43/+31
| | | | | | | | | | Currently we use switch() and access PCI configuration via several functions, one for each data size. Adjust the code to use generic functions, where the data size is a parameter. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Tidy up function comments in cmd_pci.cSimon Glass2015-12-01-45/+39
| | | | | | | The function comments use an old style and some are incorrect. Update them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Reorder functions in cmd_pci.cSimon Glass2015-12-01-110/+106
| | | | | | | | Before converting this to driver model, reorder the code to avoid forward function declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Move common auto-config functions to a common fileSimon Glass2015-12-01-117/+129
| | | | | | | | Some functions will be used by driver model and legacy PCI code. To avoid duplication, put these in a separate, shared file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Rename pci_auto.c to pci_auto_old.cSimon Glass2015-12-01-1/+1
| | | | | | | | This file should not be used with driver model as it has lots of legacy/ compatibility functions. Rename it to make this clear. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a comment about how to find struct pci_controllerSimon Glass2015-12-01-0/+2
| | | | | | | | With driver mode, struct pci_controller is stored as uclass-private data. Add a comment to that effect. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Refactor the pciinfo() functionSimon Glass2015-12-01-89/+148
| | | | | | | | | | This function uses macros to output data. It seems better to use a table of registers rather than macro-based code generation. It also reduces the code/data size by 2KB on ARM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Use a separate variable for the bus numberSimon Glass2015-12-01-3/+3
| | | | | | | | At present in do_pci(), bdf can either mean a bus number or a PCI bus number. Use separate variables instead to reduce confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Use a common return in command processingSimon Glass2015-12-01-6/+13
| | | | | | | Adjust the commands to return from the same place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: tegra: pci: Convert tegra boards to driver model for PCISimon Glass2015-12-01-330/+160
| | | | | | | | | Adjust the Tegra PCI driver to support driver model and move all boards over at the same time. This can make use of some generic driver model code, such as the range-decoding logic. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Add a function to find the regions for a PCI busSimon Glass2015-12-01-0/+42
| | | | | | | | | This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Add a function to get the controller for a busSimon Glass2015-12-01-0/+16
| | | | | | | | | A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Add functions to emulate 8- and 16-bit accessSimon Glass2015-12-01-0/+70
| | | | | | | | | Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Support decoding ranges with duplicate entriesSimon Glass2015-12-01-3/+10
| | | | | | | | | | | | | | | | | | At present we add a new resource entry for every range entry. But some range entries refer to configuration regions. To make this work, avoid adding two regions of the same type. The later ranges will overwrite the earlier (configuration) ones. There does not seem to be a way to distinguish the configuration ranges other than by ordering (as per the device tree binding). We could perhaps instead just store one region of each type in a simple array. Once we are sure that we don't need to support multiple regions, we could change this. It would be easier to do it when all drivers are converted to use driver model for PCI. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Set up the SDRAM mapping correctlySimon Glass2015-12-01-6/+9
| | | | | | | | | | SDRAM doesn't always start at 0. Adjust the region mapping so that it works on platforms where SDRAM is somewhere else. This needs testing on other platforms. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Avoid a driver model build error with CONFIG_CMD_PCI_ENUMSimon Glass2015-12-01-6/+4
| | | | | | | | | | | | | This is not supported with driver model, so print a message instead of generating a build error. Rescanning PCI is not yet implemented. This function will be implemented later once some additional PCI driver model improvements are merged. It was confirmed on the mailing list that no one on the tegra side will miss this feature, so it is disabled for tegra. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: tegra: pci: Move CONFIG_PCI_TEGRA to KconfigSimon Glass2015-12-01-6/+28
| | | | | | | Move this option to Kconfig and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: refactor common Kconfig optionsStephen Warren2015-12-01-18/+20
| | | | | | | | | | | This makes it easier to select common options in a single place, rather than having to add them separately for different SoCs or architectures. The lists of select statements are now also sorted for easy searching. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
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