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* x86: tsc: Move tsc_timer.c to drivers/timerBin Meng2015-12-01-3/+8
| | | | | | | | To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: tsc: Remove legacy timer codesBin Meng2015-12-01-82/+0
| | | | | | | | | | | Now that we have converted all x86 boards to use driver model timer, remove these legacy timer codes in the tsc driver. Note this also removes the TSC_CALIBRATION_BYPASS Kconfig option, as it is not needed with driver model. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Convert to use driver model timerBin Meng2015-12-01-39/+42
| | | | | | | Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: timer: Avoid using timer before it is readySimon Glass2015-12-01-1/+9
| | | | | | | | | | | | | | At present bootstage will try to read the timer very early after relocation. When driver model is used to provide the timer, we cannot read it until driver model is ready. Correct this by adding a separate stage for the post-relocation bootstage init. This fixes booting on chromebook_link. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* x86: tsc: Add driver model timer supportBin Meng2015-12-01-0/+65
| | | | | | | This adds driver model timer support to x86 tsc timer driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: tsc: Use notrace from <linux/compiler.h>Bin Meng2015-12-01-3/+3
| | | | | | | | Replace __attribute__((no_instrument_function)) with notrace from <linux/compiler.h>. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Remove MIN_PORT80_KCLOCKS_DELAYBin Meng2015-12-01-20/+0
| | | | | | | | | | This is not referenced anywhere. Remove it, as well as tsc_base_kclocks and tsc_prev in the global data. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Fix 'Reomve' typo: Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: timer: Support 64-bit counterBin Meng2015-12-01-12/+32
| | | | | | | | | | | | There are timers with a 64-bit counter value but current timer uclass driver assumes a 32-bit one. Modify timer_get_count() to ask timer driver to always return a 64-bit counter value, and provide an inline helper function timer_conv_64() to handle the 32-bit/64-bit conversion automatically. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* timer: sandbox: Use device tree to pass the clock frequencyBin Meng2015-12-01-4/+1
| | | | | | | | We should use device tree to pass the clock frequency of the timer instead of hardcoded in the driver codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* timer: altera: Remove the codes to get clock frequencyBin Meng2015-12-01-6/+0
| | | | | | | | | Since we have timer uclass to get clock frequency for us, remove the custom version in the altera timer driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
* dm: timer: Implement pre_probe()Bin Meng2015-12-01-0/+13
| | | | | | | | | | Every timer device needs to have a valid clock frequency and it can be specified in the device tree. Use pre_probe() to get this in the timer uclass driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
* dm: timer: Fix several nitsBin Meng2015-12-01-13/+14
| | | | | | | | This changes 'Timer' to 'timer' at several places. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-11-30-63/+1171
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| * arm: at91/spl: atmel_sfr: move saic redirect to separate fileWenyou Yang2015-11-30-15/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | To make saic redirect code sharing with other SoCs, move the saic redirect code from SAMA5D4 particular file, mach-at91/armv7/sama5d4_devices.c to a separate file, mach-at91/atmel_sfr.c Move ATMEL_SFR_AICREDIR_KEY definition to sama5d4.h, because each SoC has its own value. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: at91/spl: matrix: use matrix slave id macrosWenyou Yang2015-11-30-9/+34
| | | | | | | | | | | | | | | | To make matrix initialization code sharing with others, use the matrix slave id macros, instead of hard-coding. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: at91/spl: matrix: remove security peripheral select codeWenyou Yang2015-11-30-9/+0
| | | | | | | | | | | | | | | | | | Remove the security peripheral select code, keep the default value in these registers, that is, the peripheral address space is configured as "Secured" access, it is suitable for SPL. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: at91/spl: matrix: remove matrix write protection codeWenyou Yang2015-11-30-8/+0
| | | | | | | | | | | | | | | | | | On processor reset, the matrix write protection is disabled, so no need to disable/enable write protection when writing the matrix registers. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: at91/spl: matrix: move matrix init to separate fileWenyou Yang2015-11-30-43/+52
| | | | | | | | | | | | | | | | | | | | To make the matrix initialization code sharing with other SoCs, move it from SAMA5D4 particular file, mach-at91/armv7/sama5d4_devices.c to a separate file, mach-at91/matrix.c Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: atmel: Add SAMA5D2 Xplained boardWenyou Yang2015-11-30-6/+731
| | | | | | | | | | | | | | | | | | | | | | | | The board supports following features: - Boot media support: SD card/e.MMC/SPI flash, - Support LCD display (optional, disabled by default), - Support ethernet, - Support USB mass storage. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> [fix checkpatch warnings] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * gpio: atmel: Add the PIO4 driver supportWenyou Yang2015-11-30-0/+356
| | | | | | | | | | | | | | The PIO4 is introduced from SAMA5D2, as a new version for Atmel PIO controller. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-11-30-556/+5021
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| * | armv8: fsl-layerscape: Fix early MMU table for nand bootYork Sun2015-11-30-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The early MMU table doesn't enable all addresses. Unused addresses are marked as invalid, as introduced by commit 9979922. An entry was missing for NAND flash space, causing nand boot failure. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com>
| * | armv8: ls2080a: Define CONFIG_ENV_OVERWRITE to overwrite serial and ethaddrAlison Wang2015-11-30-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | As the environment variables "serial#" and "ethaddr" need to be overwriten by the users, CONFIG_ENV_OVERWRITE is defined to disable the write protection. Anybody can change or delete these parameters. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | net: phy: added aquantia PHY AQR405 supportShaohui Xie2015-11-30-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | The phy can share driver with other aquantia PHYs, so we only add PHY ID. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8: ls2085a: Add workaround of errata A009635Prabhakar Kushwaha2015-11-30-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | board/ls2080qds: Fix typo in README for QSGMII riser cardPrabhakar Kushwaha2015-11-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DPMACx to PHY mapping for SGMII is mentioned as QSGMII. So fix typo in README for QSGMII rise card. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Change from ls2085aqds to ls2080aqds] Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Update fdt_high and initrd_high for LS1021AQDS boardAlison Wang2015-11-30-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As 3G/1G user/kernel memory split is used on LS1021A, the Linux kernel fails to access the device tree blob on boot. The reason is that u-boot relocates the device tree blob into high memory when booting the kernel and the kernel is unable to access the blob. To avoid this issue, fdt_high is set to the value of 0xffffffff. The device tree blob will not get relocated and is still in low memory to make it accessible to the kernel. For the same reason, initrd_high is set to the value of 0xffffffff too. This patch is to update fdt_high and initrd_high for LS1021AQDS board. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8: fsl-layerscape: Fix "cpu release" commandYork Sun2015-11-30-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | When one core is released, other cores may not have valid entry address. Those cores are trapped by "wfe" and wait for further instruction. When their address is set, they need to be kicked off by "sev". Signed-off-by: York Sun <yorksun@freescale.com>
| * | drivers/ddr/fsl: Fix typo in BIST test for DDR4York Sun2015-11-30-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | BIST test code has a typo, resulting the binding registers not maintained as expected. This typo results BIST runs twice on the covered memory. Signed-off-by: York Sun <yorksun@freescale.com> Reported-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| * | armv8/layerscape: Update MMU table with execute-never bitsAlison Wang2015-11-30-31/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com>
| * | drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3York Sun2015-11-30-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | Freescale LSCH3 platforms use two DDR controlers interleaving mode out of reset. It can be configured to disable one controller. To support this operation, the driver needs to detect and skip the disabled controller. Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043ardb: add USB supportGong Qianyu2015-11-30-4/+40
| | | | | | | | | | | | | | | | | | | | | Add support for the third USB controller for LS1043A. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043ardb: add DSPI supportGong Qianyu2015-11-30-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | Use the U-Boot Driver Model. Just enable Freescale DSPI driver and set DSPI related parameters in dts file. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043aqds: dts: add dtb supportGong Qianyu2015-11-30-1/+128
| | | | | | | | | | | | | | | | | | | | | Reuse the dts files from ls1043a linux kernel. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043aqds: add LS1043AQDS board supportShaohui Xie2015-11-30-0/+1649
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043AQDS Specification: ------------------------- Memory subsystem: * 2GByte DDR4 DIMM * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two RGMII ports * XFI 10G port * SGMII * QSGMII with 4x 1G ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> [York Sun: Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043ardb: dts: add dtb supportGong Qianyu2015-11-30-0/+247
| | | | | | | | | | | | | | | | | | | | | | | | Reuse dts files from ls1043a linux kernel. Some parts in dts files may not be needed by U-Boot. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/fsl-layerscape: Remove reference to gdataGong Qianyu2015-11-30-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The global_data pointer (gd) has been set earlier in crt0_64.S. So there's no need to assign it again. Remove gdata since it is going away in U-Boot. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | pci/layerscape: add support for LS1043A PCIe LUT register accessMingkai Hu2015-11-30-7/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8: ls2085a: Add support of LS2085A SoCPrabhakar Kushwaha2015-11-30-20/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's LS2085A is a another personality of LS2080A SoC with support of AIOP and DP-DDR. This Patch adds support of LS2085A Personality. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Updated MAINTAINERS files Dropped #ifdef in cpu.h Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha2015-11-30-190/+244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver: net: ldpaa: Fix Rx buffer alignmentPrabhakar Kushwaha2015-11-30-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MC 0.7.1.2 enforces limitation i.e.: "Packets may be corrupted in several combinations of buffer size and frame offsets. Workaround: Use buffers that are of size that is a multiple of 256, and frame offset that is a multiple of 256" Updating the DPNI Eth driver to comply with the restriction. Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver: net: ldpaa: Add debug informationPrabhakar Kushwaha2015-11-30-0/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add following debug information in the driver - Get various DPNI counter values - Get link status of DPNI objects - Get information of both ends of connection (DPMAC - DPNI) Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver: net: ldpaa: Use DPMAC as net devicePrabhakar Kushwaha2015-11-30-45/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per current implementation of DPAA2 ethernet driver DPNI is used as net device. DPNI is tangible objects can be multiple connected to same physical lane. Use DPMAC as net device where it represents physical lane. Below modification done in driver - Use global DPNI object - Connect DPMAC to DPNI - Create and destroy DPMAC Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver: net: fsl-mc: Create DPAA2 object at run-timePrabhakar Kushwaha2015-11-30-41/+468
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's DPAA2 ethernet driver depends upon the static DPL for the DPRC, DPNI, DPBP, DPIO objects. Instead of static objects, Create DPNI, DPBP, DPIO objects at run-time. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver: net: fsl-mc: Add DPAA2 commands to manage MCPrabhakar Kushwaha2015-11-30-223/+251
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Management complex Firmware, DPL and DPC are depolyed during u-boot boot sequence. Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop and apply DPL from u-boot command prompt. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver: net: fsl-mc: Increase MC command timeoutPrabhakar Kushwaha2015-11-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | dpni_create API take takes more time as comapred to existing supported APIs of MC Flib. So increase MC command timeout. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver: ldpaa: Add api to return linked PHY ID of DPMACPrabhakar Kushwaha2015-11-30-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DPMAC represents physical line on the board. This physical line eventually asscociate with on-board PHY. So Add an api to return linked PHY ID of DPMAC object. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8: ls2085aqds: Print function name during SerDes errorPrabhakar Kushwaha2015-11-30-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | Print function name along with SerDes Protocol during SerDes Protocol not supported error. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver: net: fsl-mc: Add APIs for DPMAC objects in FLIBPrabhakar Kushwaha2015-11-30-1/+692
| | | | | | | | | | | | | | | | | | | | | | | | | | | DPMAC object of Management complex controls Physical MAC and MDIO controller. It provides APIs for MDIO and link state updates. It also provides APIs for PHY/link configuration. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver: net: fsl-mc: Add create, destroy APIs in flibsPrabhakar Kushwaha2015-11-30-0/+548
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current Management Complex Flibs does not support APIs for adding and destroying the objects. Add APIs to create and destroy objects for DPBP, DPIO, DPNI and DPRC. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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