summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* secure_boot: enable chain of trust for PowerPC platformsAneesh Bansal2016-01-27-0/+21
| | | | | | | | | | | | | | | Chain of Trust is enabled for PowerPC platforms for Secure Boot. CONFIG_BOARD_LATE_INIT is defined. In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* secure_boot: enable chain of trust for ARM platformsAneesh Bansal2016-01-27-0/+34
| | | | | | | | | | | | | | Chain of Trust is enabled for ARM platforms (LS1021 and LS1043). In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* secure_boot: create function to determine boot modeAneesh Bansal2016-01-27-0/+61
| | | | | | | | | A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* secure_boot: split the secure boot functionality in two partsAneesh Bansal2016-01-27-55/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). Thus the current Secure Boot functionlity has been split into two parts: CONFIG_CHAIN_OF_TRUST This will have the following functionality as part of U-Boot: 1. Enable commands like esbc_validate, esbc_halt 2. Change the environment settings based on bootmode, determined at run time: - If bootmode is non-secure, no change - If bootmode is secure, set the following: - bootdelay = 0 (Don't give boot prompt) - bootcmd = Validate and execute the bootscript. CONFIG_SECURE_BOOT This is defined only for creating a different compile time target for secure boot. Traditionally, both these functionalities were defined under CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement for a separate Secure Boot target for ARM based SoC's. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be determine at run time. Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot environemnt must not be picked from flash/external memory. This cannot be done based on bootmode at run time in current U-Boot architecture. Once this dependency is resolved, no separate SECURE_BOOT target will be required for ARM based SoC's. Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining CONFIG_ENV_IS_NOWHERE Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* secure_boot: include/configs: move definition of CONFIG_CMD_BLOBAneesh Bansal2016-01-27-71/+2
| | | | | | | | | | CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was earlier defined in all config files. The definition has been moved to a common file which is included by all configs. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* secure_boot: include/configs: make secure boot header file uniformAneesh Bansal2016-01-27-16/+57
| | | | | | | | | | | | | | The file fsl_secure_boot.h must be included in config file for Secure Boot. This is not required to be protected by any macro. CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be turned on. The above was missing in some config files and all files have been made uniform in this respect. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* drivers: net: fsl_mc: Compare pointer value qbman_swp_mc_startPratiyush Mohan Srivastava2016-01-25-1/+3
| | | | | | | | | | Current code compares the return pointer of function qbman_cena_write_start with NULL. Instead the value of the return pointer should be compared. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080a: Increase MC's DDR size to 512 MBPratiyush Mohan Srivastava2016-01-25-1/+1
| | | | | | | | | Freescale's management complex (MC) uses System DDR for internal usage. Increase used System DDR size from 256MB to 512 MB. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2040a: Add support of LS2040A SoCPratiyush Mohan Srivastava2016-01-25-0/+2
| | | | | | | | | Freescale's LS2040A is a another personality of LS2080A SoC without AIOP support consisting of 4 armv8 cores. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: Enable all 8 DPMAC ports in LS2080A PersonalityPratiyush Mohan Srivastava2016-01-25-5/+0
| | | | | | | | | | LS2080A has support for 8 DPMAC ports out of which only 5 ports can be used at a time. Enabling all 8 DPMAC ports of LS2080A personality. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* SECURE BOOT: support for validation of dynamic imageAneesh Bansal2016-01-25-18/+32
| | | | | | | | | | | | | | | | | Some images to be validated are relocated to a dynamic address at run time. So, these addresses cannot be known befor hand while signing the images and creating the header offline. So, support is required to pass the image address to the validate function as an argument. If an address is provided to the function, the address field in Header is not read and is treated as a reserved field. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* SECURE BOOT: separate function created for signatureAneesh Bansal2016-01-25-44/+54
| | | | | | | | | | | The code for image hash calculation, hash calculation from RSA signature and comparison of hashes has been mobed to a separate function. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* SECURE BOOT: separate functions for reading keysAneesh Bansal2016-01-25-73/+96
| | | | | | | | | | | | | Separate functions are created for reading and checking the sanity of Public keys: - read_validate_single_key - read_validate_ie_tbl - read_validate_srk_table Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* SECURE BOOT: change prototype of fsl_secboot_validate functionAneesh Bansal2016-01-25-15/+25
| | | | | | | | | | | | | | The prototype and defination of function fsl_secboot_validate has been changed to support calling this function from another function within u-boot. Only two aruments needed: 1) header address - Mandatory 2) SHA256 string - optional Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllersEd Swarthout2016-01-25-0/+1
| | | | | | | | Following commit 61bd2f75, exclude unused DDR controller from calculating RAM size for SPL boot. Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: fixes lsch2 serdes registers defineShaohui Xie2016-01-25-20/+47
| | | | | | | Fixes lsch2 SerDes registers define according to LS1043A RM Rev D. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: ls1021a: Adjust sata register default valuesTang Yuantian2016-01-25-5/+5
| | | | | | | | Updated the default sata register values to enhance the performance and stability. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* driver/ddr/fsl: Add workaround for A009663Shengzhou Liu2016-01-25-0/+20
| | | | | | | | | | | | Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-lsch3: fixup SYSCLK frequency in device treePrabhakar Kushwaha2016-01-25-0/+3
| | | | | | | | | | | | SYSCLK frequency is dependent on on-board switch settings. It may vary as per requirement. boot-loader is aware of board switch configurations. So Fixup Linux device tree from boot-loader. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043aqds: enable qixis_reset command to boot from NAND/SDGong Qianyu2016-01-25-0/+4
| | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043aqds: fix qixis_reset command issueGong Qianyu2016-01-25-1/+1
| | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* freescale/qixis: Add support for booting from SD/QSPIGong Qianyu2016-01-25-0/+36
| | | | | | | | | | | | | | | | 1.Use "qixis_reset sd" to boot from SD 2.Use "qixis_reset sd_qspi" to boot from SD with QSPI support 3.Use "qixis_reset qspi" to boot from QSPI flash On some SoCs such as LS1021A and LS1043A, IFC and QSPI could be pin-multiplexed. So the switches are different between SD boot with IFC support and SD boot with QSPI support. The default booting from SD is with IFC support. Once QSPI is enabled(IFC disabled), only use I2C to access QIXIS. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043aqds: Add support for >2GB memoryShaohui Xie2016-01-25-4/+27
| | | | | | | This patch also exposes the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl/ddr: Add workaround for ERRATUM_A009942Shengzhou Liu2016-01-25-0/+19
| | | | | | | | | | | | During the receive data training, the DDRC may complete on a non-optimal setting that could lead to data corruption or initialization failure. Workaround: before setting MEM_EN, set DEBUG_29 register with specific value for different data rates. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge git://git.denx.de/u-boot-fdtTom Rini2016-01-22-1/+1
|\
| * devicetree: use wildcard to clean arch subdirThomas Chou2016-01-22-1/+1
| | | | | | | | | | | | | | | | Use wildcard to clean arch subdirectories, as it is cleaner than listing all the arch which builds dtb. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | rockchip: Update the READMESimon Glass2016-01-21-20/+20
| | | | | | | | | | | | | | | | | | | | GPIO, I2C, LCD and HDMI are now implemented. We have more than one PMIC. There is an implementation to run the CPU at full speed although it does not seem to make much difference. Update the README to cover recent developments. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Add support for Raxda Rock 2Simon Glass2016-01-21-6/+133
| | | | | | | | | | | | | | | | | | | | | | | | This board includes an RK3288 SoC on a SOM. It can be mounted on a base-board which provides a wide range of peripherals. So far this is verified to boot to a prompt from a microSD card. The serial console works as well as HDMI. Thanks to Tom Cubie for sending me a board. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: rock2: dts: Make changes for U-BootSimon Glass2016-01-21-0/+21
| | | | | | | | | | | | Add the required pre-relocation tags and SDRAM init information for U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: rock2: Bring in device tree files from LinuxSimon Glass2016-01-21-0/+458
| | | | | | | | | | | | | | Bring in the current device tree files for rock2 from linux/next commit 719d6c1. Hopefully this is the latest one. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: dts: Sync up SPDIF node with LinuxSimon Glass2016-01-21-0/+21
| | | | | | | | | | | | | | This has been added and we have references to it in the rock2 board. Add this node. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: firefly-rk3288: Enable HDMI outputSimon Glass2016-01-21-1/+15
| | | | | | | | | | | | Enable HDMI output and a console on firefly. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: jerry: Enable EDP and HDMI video outputSimon Glass2016-01-21-2/+18
| | | | | | | | | | | | | | | | | | | | | | Enable these devices using the VOPL video output device. We explicitly disable VOPB in the device tree to avoid it taking over. Since this device has an LCD display this comes up by default. If the display fails for some reason then it will attempt to use HDMI. It is possible to force it to fail (and thus fall back to HDMI) by puting 'return -EPERM' at the top of rk_edp_probe(). For now there is no easy way to select between the two. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: jerry: Add support for timing SPI flash speedSimon Glass2016-01-21-0/+3
| | | | | | | | | | | | | | Add the 'time' and 'sf test' commands so that we can test SPI flash performance. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: spl: Support full-speed CPU in SPLSimon Glass2016-01-21-0/+124
| | | | | | | | | | | | | | | | Add a feature which speeds up the CPU to full speed in SPL to minimise boot time. This is only supported for certain boards (at present only jerry). Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3288: pinctrl: Fix HDMI pinctrlSimon Glass2016-01-21-0/+2
| | | | | | | | | | | | | | Since the device tree does not specify the EDID pinctrl option for HDMI we must set it manually. Fix the driver to handle this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3288: clock: Fix various minor errorsSimon Glass2016-01-21-8/+13
| | | | | | | | | | | | Fix a number of small errors which were found in reviewing the clock code. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: jerry: Fix the SDRAM timingSimon Glass2016-01-21-1/+1
| | | | | | | | | | | | | | There is a minor error in the SDRAM timing. It does not seem to affect anything so far. Fix it just in case. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: spl: Drop MMC support code when not neededSimon Glass2016-01-21-2/+4
| | | | | | | | | | | | When the board does not use MMC SPL this code is a waste of space. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Tidy up the register-access macrosSimon Glass2016-01-21-3/+4
| | | | | | | | | | | | | | | | | | These work reasonable well, but there are a few errors: - Brackets should be used to avoid unexpected side-effects - When setting bits, the corresponding upper 16 bits should be set also Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: sdram: Use syscon_get_first_range() where possibleSimon Glass2016-01-21-14/+3
| | | | | | | | | | | | | | This is a shortcut to obtaining a register address. Use it where possible, to simplify the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: sdram: Tidy up a few commentsSimon Glass2016-01-21-2/+2
| | | | | | | | | | | | Fix spaces in two comments in this file. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: config: Enable the 'gpio' commandSimon Glass2016-01-21-0/+1
| | | | | | | | | | | | | | Now that we have a pretty good GPIO driver, enable the 'gpio' command on all rockchip boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Add a script to parse datasheetsSimon Glass2016-01-21-0/+224
| | | | | | | | | | | | | | | | This script has proved useful for parsing datasheets and creating register shift/mask values for use in header files. Include it in case it is useful for others. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Add a simple 'clock' commandSimon Glass2016-01-21-0/+24
| | | | | | | | | | | | Add a command that displays the PLLs and their current rate. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: Don't skip low-level initSimon Glass2016-01-21-1/+8
| | | | | | | | | | | | | | At present the low-level init is skipped on rockchip. Among other things this means that the instruction cache is left disabled. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: video: Add a video-output driverSimon Glass2016-01-21-1/+696
| | | | | | | | | | | | | | | | Some rockchip SoCs include video output (VOP). Add a driver to support this. It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and eDP are supported. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: video: Add a display driver for rockchip eDPSimon Glass2016-01-21-1/+1722
| | | | | | | | | | | | | | Some Rockchip SoCs support embedded DisplayPort output. Add a display driver for this so that these displays can be used on supported boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: video: Add a display driver for rockchip HDMISimon Glass2016-01-21-0/+1408
| | | | | | | | | | | | | | | | | | | | | | | | Some Rockchip SoCs support HDMI output. Add a display driver for this so that these displays can be used on supported boards. Unfortunately this driver is not fully functional. It cannot reliably read EDID information over HDMI. This seems to be due to the clocks being incorrect - the I2C bus speed appears to be up to 100x slower than the clock settings indicate. The root cause may be in the clock logic. Signed-off-by: Simon Glass <sjg@chromium.org>
* | rockchip: clk: Add support for clocks needed by the displaysSimon Glass2016-01-21-4/+170
| | | | | | | | | | | | | | The displays need to use NPLL and also select some new peripheral clocks. Add support for these to the clock driver. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-28 05:22:40 +0000