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* ARM64: zynqmp: Select SYS_CONFIG_NAME via KconfigMichal Simek2016-04-04-9/+7
| | | | | | | | | This option enable adding new platform suport just by adding defconfig and DTS file which will target generic configuration for SoC. Make no sense to extend Kconfig just create a pointer between DTS and configuration file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Enable FAT write and EXT4 write for USB tooMichal Simek2016-04-04-0/+3
| | | | | | Enabling writing files to FAT and EXT4 for USB. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Decrease boot delaySoren Brinkmann2016-04-04-1/+1
| | | | | | | Synchronize it with zynq platform. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: axi_emac: Report phy-node error message permanentlyMichal Simek2016-04-04-1/+1
| | | | | | Do not use debug() when printing error message. Use printf instead. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Remove !OF_CONTROL code for timer and interruptMichal Simek2016-04-04-45/+1
| | | | | | OF_CONTROL is enabled by default that's why this is dead code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Read information about timer/interrupts from DTMichal Simek2016-04-04-1/+63
| | | | | | | Read information about timer and interrupts from DT. This is the first small step to move timer and intc to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: Fix default ps7_init_gpl.c/h for ZYBOMichal Simek2016-04-04-244/+1342
| | | | | | | | | There is incorrect setting for USB which didn't work with origin ps7_init_gpl.X files. Use default setting for Digilent Zybo projects with HDMI in PL. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: zybo: Enabling reading MAC address from EEPROMMichal Simek2016-04-04-0/+3
| | | | | | | Zybo has on board I2C EEPROM which contains preprogrammed MAC address. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: gem: Allow to set the MAC from an EEPROMJoe Hershberger2016-04-04-0/+33
| | | | | | | | | | Provide board specific option how to read MAC address from ROM. Do it in generic way to be reusable by differnet boards. If this is not enough board specific functions can be created. Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: Enable option to overwrite default variablesMichal Simek2016-04-04-0/+2
| | | | | | Enable overwriting variables out of main config file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: xilinx_axi: Clear Isolate bit if found during phy setupSiva Durga Prasad Paladugu2016-04-04-1/+19
| | | | | | | | | | In SGMII cases the isolate bit might set after DMA and ethernet resets and hence check and clear during setup_phy if it was set. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: xilinx_axi: Use interface type instead of zeroSiva Durga Prasad Paladugu2016-04-04-1/+1
| | | | | | | | | Pass appropriate interface type to phy_connect instead of zero. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq-common: Enable phy driver for Xilinx PCS/PMA coreSiva Durga Prasad Paladugu2016-04-04-0/+1
| | | | | | | Add support of Xilinx PCS/PMA core phy for Zynq Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: Add support for SGMII interfaceSiva Durga Prasad Paladugu2016-04-04-7/+19
| | | | | | | | Add support of SGMII interface for zynq GEM. Read xlnx,emio property from DT. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* phy: Add phy driver support for xilinx PCS/PMA coreSiva Durga Prasad Paladugu2016-04-04-0/+149
| | | | | | | | Add phy driver support for xilinx PCS/PMA core Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: phy: Realtek RTL8211B/C PHY ID fixKarsten Merker2016-04-02-1/+2
| | | | | | | | | | | | | | | | | | | | | | | The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field. The lowest four bits of the PHY ID encode the chip revision (B+C/D/E/F) of the RTL8211 and the code originally applied a mask of 0xfffff0 to the PHY ID, so that matching the PHY ID to the appropriate driver code was only done on the chip type (RTL8211), but not on a specific revision. After introduction of support for the RTL8211E, which needed another startup function than the older chip revisions, commit 42205047674d7fc9e0aa747273fbc7dcfbac3183 changed the mask to 0xffffff to make the chip revision relevant for the match, but didn't provide the now-relevant lower bits of the uid field for the RTL8211B/C. Fix this by setting the full PHY ID in the RTL8211B_driver uid field. Fixes: 42205047674d ("net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected") Signed-off-by: Karsten Merker <merker@debian.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* MAINTAINERS: Update Scott Wood's email addressScott Wood2016-04-01-1/+1
| | | | | | | Freescale is now NXP. I still work there, but I won't be using their mail system for U-Boot development. Signed-off-by: Scott Wood <oss@buserror.net>
* sata: use block layer for sata commandEric Nelson2016-04-01-2/+4
| | | | | | | | Call blk_dread, blk_dwrite, blk_derase to ensure that the block cache is used if enabled and to remove build breakage when CONFIG_BLK is enabled. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* mmc: use block layer in mmc commandEric Nelson2016-04-01-3/+4
| | | | | | | | Call blk_dread, blk_dwrite, blk_derase to ensure that the block cache is used if enabled and to remove build breakage when CONFIG_BLK is enabled. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* drivers: block: add block device cacheEric Nelson2016-04-01-2/+402
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a block device cache to speed up repeated reads of block devices by various filesystems. This small amount of cache can dramatically speed up filesystem operations by skipping repeated reads of common areas of a block device (typically directory structures). This has shown to have some benefit on FAT filesystem operations of loading a kernel and RAM disk, but more dramatic benefits on ext4 filesystems when the kernel and/or RAM disk are spread across multiple extent header structures as described in commit fc0fc50. The cache is implemented through a minimal list (block_cache) maintained in most-recently-used order and count of the current number of entries (cache_count). It uses a maximum block count setting to prevent copies of large block reads and an upper bound on the number of cached areas. The maximum number of entries in the cache defaults to 32 and the maximum number of blocks per cache entry has a default of 2, which has shown to produce the best results on testing of ext4 and FAT filesystems. The 'blkcache' command (enabled through CONFIG_CMD_BLOCK_CACHE) allows changing these values and can be used to tune for a particular filesystem layout. Signed-off-by: Eric Nelson <eric@nelint.com>
* Add myself as Snapdragon and SPMI maintainerMateusz Kulikowski2016-04-01-0/+14
| | | | | | | | - Update MAINTAINERS - Update git-mailrc Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* board: Add Qualcomm Dragonboard 410C supportMateusz Kulikowski2016-04-01-0/+729
| | | | | | | | | | | | | | | | | | | | | | This commit add support for 96Boards Dragonboard410C. It is board based on APQ8016 Qualcomm SoC, complying with 96boards specification. Features (present out of the box): - 4x Cortex A53 (ARMv8) - 2x USB Host port - 1x USB Device port - 4x LEDs - 1x HDMI connector - 1x uSD connector - 3x buttons (Power, Vol+, Vol-/Reset) - WIFI, Bluetooth with integrated antenna - 8GiB eMMC U-Boot boots chained with fastboot in 64-bit mode. For detailed build instructions see readme.txt in board directory. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Tested-by: Simon Glass <sjg@chromium.org>
* arm: Add support for Qualcomm Snapdragon familyMateusz Kulikowski2016-04-01-0/+383
| | | | | | | | | | | First supported chip is APQ8016 (that is compatible with MSM8916). Drivers in SoC code: - Reset controller (PSHOLD) - Clock controller (very simple clock configuration for MMC and UART) Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* gpio: Add support for Qualcomm PM8916 gpiosMateusz Kulikowski2016-04-01-0/+361
| | | | | | | | | | | This driver supports GPIOs present on PM8916 PMIC. There are 2 device drivers inside: - GPIO driver (4 "generic" GPIOs) - Keypad driver that presents itself as GPIO with 2 inputs (power and reset) Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* pmic: Add support for Qualcomm PM8916 PMICMateusz Kulikowski2016-04-01-0/+131
| | | | | | | | This PMIC is connected on SPMI bus so needs SPMI support enabled. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* drivers: spmi: Add support for Qualcomm SPMI bus driverMateusz Kulikowski2016-04-01-1/+222
| | | | | | | | Support SPMI arbiter on Qualcomm Snapdragon devices. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* spmi: Add sandbox test driverMateusz Kulikowski2016-04-01-0/+356
| | | | | | | | This patch adds emulated spmi bus controller with part of pm8916 pmic on it to sandbox and tests validating SPMI uclass. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: Add SPMI bus uclassMateusz Kulikowski2016-04-01-0/+115
| | | | | | | | | | | | Qualcom processors use proprietary bus to talk with PMIC devices - SPMI (System Power Management Interface). On wiring level it is similar to I2C, but on protocol level, it's multi-master and has simple autodetection capabilities. This commit adds simple uclass that provides bus read/write interface. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* ehci: Add support for Qualcomm EHCIMateusz Kulikowski2016-04-01-0/+200
| | | | | | | | | | This driver is able to reconfigure OTG controller into HOST mode. Board can add board-specific initialization as board_prepare_usb(). It requires USB_ULPI_VIEWPORT enabled in board configuration. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* ehci-ci.h: drop generic USBCMD fieldsMateusz Kulikowski2016-04-01-6/+2
| | | | | | | | Use definitions from ehci.h instead. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* usb: ehci-ci: Add missing registers.Mateusz Kulikowski2016-04-01-1/+5
| | | | | | | | | | | | | | Some registers of usb_ehci were marked as reserved. This may be true for some variants of Chipidea USB core, but they have meaning on other devices. The following registers were added: sbusstatus/sbusmode: AHB-related registers genconfig*: Auxiluary IP core configuration registers. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* usb: Rename ehci-fsl.h to ehci-ci.hMateusz Kulikowski2016-04-01-20/+20
| | | | | | | | | | | | | Most of ehci-fsl header describe USB controller designed by Chipidea and used by various SoC vendors. This patch renames it to a generic header: ehci-ci.h Contents of file are not changed (so it contains several references to freescale SoCs). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* eth: asix88179: Print packet length properlyMateusz Kulikowski2016-04-01-1/+1
| | | | | | | | | Debug printf used '%u' to print size_t variable. This caused warnings on 64-bit machines. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* usb: ulpi: Fix compile warning in read/write on 64-bit machines.Mateusz Kulikowski2016-04-01-2/+5
| | | | | | | | | | | | | | | | | | | ulpi_read and ulpi_write are used to read/write registers via ULPI bus. Code generates compilation warnings on 64-bit machines where pointer is cast to u32. This patch drops all but last 8 bits of register address. It is possible, because addresses on ULPI bus are 6- or 8-bit. It is not possible (according to ULPI 1.1 spec) to have more than 8-bit addressing. This patch should not cause regressions as all calls to ulpi_read/write use either structure pointer (@ address 0) or integer offsets cast to pointer - addresses requested are way below 8-bit range. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* usb: ulpi: Fix viewport_addr typeMateusz Kulikowski2016-04-01-1/+1
| | | | | | | | | | | viewport_addr is address of memory mapped ULPI viewport. It is used only as argument to readl/writel later causing compile warnings on 64-bit devices. This fix changes its type to match pointer size. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* Migrate CONFIG_ULPI* to KconfigMateusz Kulikowski2016-04-01-10/+24
| | | | | | | | | | | | | Move CONFIG_USB_ULPI* from headers to defconfigs for boards that use it. Also - add CONFIG_USB where necesarry - all boards use it, but some are not defining it explicitly. Affected boards: colibri_t20, harmony, mcx, mt_ventoux, twister, zynq_(picozed, zc702, zc706, zed, zybo) Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* usb: ulpi: Add Kconfig options for ULPIMateusz Kulikowski2016-04-01-0/+35
| | | | | | | | | | | The following options can be now enabled via defconfig: - CONFIG_USB_ULPI - CONFIG_USB_ULPI_VIEWPORT - CONFIG_USB_ULPI_VIEWPORT_OMAP Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
* ehci-hcd: Add init_after_resetMateusz Kulikowski2016-04-01-0/+7
| | | | | | | | | | | | Some host controllers need addidional initialization after ehci_reset() In non-dm implementation it is possible to use CONFIG_EHCI_HCD_INIT_AFTER_RESET. This patch adds similar option to ehci drivers using dm. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* mmc: Add support for Qualcomm SDHCI controllerMateusz Kulikowski2016-04-01-0/+215
| | | | | | | | | | | Add support for SD/eMMC controller present on some Qualcomm Snapdragon devices. This controller implements SDHCI 2.0 interface but requires vendor-specific initialization. Driver works in PIO mode as ADMA is not supported by U-Boot (yet). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* gpio: Add support for Qualcomm gpio controllerMateusz Kulikowski2016-04-01-0/+170
| | | | | | | | | | Add support for gpio controllers on Qualcomm Snapdragon devices. This devices are usually called Top Level Mode Multiplexing in Qualcomm documentation. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* serial: Add support for Qualcomm serial portMateusz Kulikowski2016-04-01-0/+232
| | | | | | | | | This driver works in "new" Data Mover UART mode, so will be compatible with modern Qualcomm chips only. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* board: ti: DRA7: Add DP83867 TI phy for rev cDan Murphy2016-04-01-0/+7
| | | | | | | | | | | Enable the TI DP83867 Giga bit phy on the dra7 rev c board. The rx and tx internal delays are need for this board so the usage of RGMII_ID is required. Signed-off-by: Dan Murphy <dmurphy@ti.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* efi_loader: Always allocate the highest available addressAlexander Graf2016-04-01-0/+29
| | | | | | | | | | | | Some EFI applications (grub2) expect that an allocation always returns the highest available memory address for the given size. Without this, we may run into situations where the initrd gets allocated at a lower address than the kernel. This patch fixes booting in such situations for me. Signed-off-by: Alexander Graf <agraf@suse.de>
* sniper: Change vendor name from lge to lg, matching devicetree vendor prefixPaul Kocialkowski2016-04-01-3/+3
| | | | | | | This moves the sniper board from the lge to lg, in order to match the devicetree vendor prefix already defined in the kernel. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* kc1: Proper reboot mode and boot reason validationPaul Kocialkowski2016-04-01-13/+10
| | | | | | | | | | | | | | | With the previous implementation, rebooting without registering a recognized reboot mode would end up with U-Boot checking for a valid power-on reason, which might result in the device turning off (e.g. with no USB cable attached and no buttons pressed). Since this approach is not viable (breaks reboot in most cases), the validity of the reboot reason is checked (in turn, by checking that a warm reset happened, as there is no magic) to detect a reboot and the 'o' char is recognized to indicate that power-off is required. Still, that might be overridden by the detection of usual power-on reasons, on purpose. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* sniper: Proper reboot mode and boot reason validationPaul Kocialkowski2016-04-01-10/+23
| | | | | | | | | | | | | | | | | | With the previous implementation, rebooting without registering a recognized reboot mode (despite registering the magic) would end up with U-Boot checking for a valid power-on reason, which might result in the device turning off (e.g. with no USB cable attached and no buttons pressed). This was designed to catch reboots that are actually intended to be power-off, something that old Android kernels do, instead of properly turning the device off using the TWL4030. However, since this approach is not viable (breaks reboot in most cases), the validity of the reboot mode magic is checked to detect a reboot and the 'o' char is recognized to indicate that power-off is required. Still, that might be overridden by the detection of usual power-on reasons, on purpose. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* kc1: Add some sysboot and devicetree-related environment variablesPaul Kocialkowski2016-04-01-0/+2
| | | | | | This adds some environment variables for sysboot and devicetree. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* kc1: Select libfdt to allow running devicetree-based kernelsPaul Kocialkowski2016-04-01-0/+1
| | | | | | Selecting CONFIG_OF_LIBFDT allows running recent mainline kernels. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* kc1: Include explicit serial baudrate on bootargsPaul Kocialkowski2016-04-01-1/+1
| | | | | | This makes the baudrate for the kernel command line explicit. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* sniper: Include explicit serial baudrate on bootargsPaul Kocialkowski2016-04-01-1/+1
| | | | | | This makes the baudrate for the kernel command line explicit. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
generated by cgit v1.1 at 2024-11-28 02:04:54 +0000