summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeLines
* sata: use block layer for sata commandEric Nelson2016-04-01-2/+4
| | | | | | | | Call blk_dread, blk_dwrite, blk_derase to ensure that the block cache is used if enabled and to remove build breakage when CONFIG_BLK is enabled. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* mmc: use block layer in mmc commandEric Nelson2016-04-01-3/+4
| | | | | | | | Call blk_dread, blk_dwrite, blk_derase to ensure that the block cache is used if enabled and to remove build breakage when CONFIG_BLK is enabled. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* drivers: block: add block device cacheEric Nelson2016-04-01-2/+402
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a block device cache to speed up repeated reads of block devices by various filesystems. This small amount of cache can dramatically speed up filesystem operations by skipping repeated reads of common areas of a block device (typically directory structures). This has shown to have some benefit on FAT filesystem operations of loading a kernel and RAM disk, but more dramatic benefits on ext4 filesystems when the kernel and/or RAM disk are spread across multiple extent header structures as described in commit fc0fc50. The cache is implemented through a minimal list (block_cache) maintained in most-recently-used order and count of the current number of entries (cache_count). It uses a maximum block count setting to prevent copies of large block reads and an upper bound on the number of cached areas. The maximum number of entries in the cache defaults to 32 and the maximum number of blocks per cache entry has a default of 2, which has shown to produce the best results on testing of ext4 and FAT filesystems. The 'blkcache' command (enabled through CONFIG_CMD_BLOCK_CACHE) allows changing these values and can be used to tune for a particular filesystem layout. Signed-off-by: Eric Nelson <eric@nelint.com>
* Add myself as Snapdragon and SPMI maintainerMateusz Kulikowski2016-04-01-0/+14
| | | | | | | | - Update MAINTAINERS - Update git-mailrc Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* board: Add Qualcomm Dragonboard 410C supportMateusz Kulikowski2016-04-01-0/+729
| | | | | | | | | | | | | | | | | | | | | | This commit add support for 96Boards Dragonboard410C. It is board based on APQ8016 Qualcomm SoC, complying with 96boards specification. Features (present out of the box): - 4x Cortex A53 (ARMv8) - 2x USB Host port - 1x USB Device port - 4x LEDs - 1x HDMI connector - 1x uSD connector - 3x buttons (Power, Vol+, Vol-/Reset) - WIFI, Bluetooth with integrated antenna - 8GiB eMMC U-Boot boots chained with fastboot in 64-bit mode. For detailed build instructions see readme.txt in board directory. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Tested-by: Simon Glass <sjg@chromium.org>
* arm: Add support for Qualcomm Snapdragon familyMateusz Kulikowski2016-04-01-0/+383
| | | | | | | | | | | First supported chip is APQ8016 (that is compatible with MSM8916). Drivers in SoC code: - Reset controller (PSHOLD) - Clock controller (very simple clock configuration for MMC and UART) Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* gpio: Add support for Qualcomm PM8916 gpiosMateusz Kulikowski2016-04-01-0/+361
| | | | | | | | | | | This driver supports GPIOs present on PM8916 PMIC. There are 2 device drivers inside: - GPIO driver (4 "generic" GPIOs) - Keypad driver that presents itself as GPIO with 2 inputs (power and reset) Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* pmic: Add support for Qualcomm PM8916 PMICMateusz Kulikowski2016-04-01-0/+131
| | | | | | | | This PMIC is connected on SPMI bus so needs SPMI support enabled. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* drivers: spmi: Add support for Qualcomm SPMI bus driverMateusz Kulikowski2016-04-01-1/+222
| | | | | | | | Support SPMI arbiter on Qualcomm Snapdragon devices. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* spmi: Add sandbox test driverMateusz Kulikowski2016-04-01-0/+356
| | | | | | | | This patch adds emulated spmi bus controller with part of pm8916 pmic on it to sandbox and tests validating SPMI uclass. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: Add SPMI bus uclassMateusz Kulikowski2016-04-01-0/+115
| | | | | | | | | | | | Qualcom processors use proprietary bus to talk with PMIC devices - SPMI (System Power Management Interface). On wiring level it is similar to I2C, but on protocol level, it's multi-master and has simple autodetection capabilities. This commit adds simple uclass that provides bus read/write interface. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* ehci: Add support for Qualcomm EHCIMateusz Kulikowski2016-04-01-0/+200
| | | | | | | | | | This driver is able to reconfigure OTG controller into HOST mode. Board can add board-specific initialization as board_prepare_usb(). It requires USB_ULPI_VIEWPORT enabled in board configuration. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* ehci-ci.h: drop generic USBCMD fieldsMateusz Kulikowski2016-04-01-6/+2
| | | | | | | | Use definitions from ehci.h instead. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* usb: ehci-ci: Add missing registers.Mateusz Kulikowski2016-04-01-1/+5
| | | | | | | | | | | | | | Some registers of usb_ehci were marked as reserved. This may be true for some variants of Chipidea USB core, but they have meaning on other devices. The following registers were added: sbusstatus/sbusmode: AHB-related registers genconfig*: Auxiluary IP core configuration registers. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* usb: Rename ehci-fsl.h to ehci-ci.hMateusz Kulikowski2016-04-01-20/+20
| | | | | | | | | | | | | Most of ehci-fsl header describe USB controller designed by Chipidea and used by various SoC vendors. This patch renames it to a generic header: ehci-ci.h Contents of file are not changed (so it contains several references to freescale SoCs). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* eth: asix88179: Print packet length properlyMateusz Kulikowski2016-04-01-1/+1
| | | | | | | | | Debug printf used '%u' to print size_t variable. This caused warnings on 64-bit machines. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* usb: ulpi: Fix compile warning in read/write on 64-bit machines.Mateusz Kulikowski2016-04-01-2/+5
| | | | | | | | | | | | | | | | | | | ulpi_read and ulpi_write are used to read/write registers via ULPI bus. Code generates compilation warnings on 64-bit machines where pointer is cast to u32. This patch drops all but last 8 bits of register address. It is possible, because addresses on ULPI bus are 6- or 8-bit. It is not possible (according to ULPI 1.1 spec) to have more than 8-bit addressing. This patch should not cause regressions as all calls to ulpi_read/write use either structure pointer (@ address 0) or integer offsets cast to pointer - addresses requested are way below 8-bit range. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* usb: ulpi: Fix viewport_addr typeMateusz Kulikowski2016-04-01-1/+1
| | | | | | | | | | | viewport_addr is address of memory mapped ULPI viewport. It is used only as argument to readl/writel later causing compile warnings on 64-bit devices. This fix changes its type to match pointer size. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* Migrate CONFIG_ULPI* to KconfigMateusz Kulikowski2016-04-01-10/+24
| | | | | | | | | | | | | Move CONFIG_USB_ULPI* from headers to defconfigs for boards that use it. Also - add CONFIG_USB where necesarry - all boards use it, but some are not defining it explicitly. Affected boards: colibri_t20, harmony, mcx, mt_ventoux, twister, zynq_(picozed, zc702, zc706, zed, zybo) Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* usb: ulpi: Add Kconfig options for ULPIMateusz Kulikowski2016-04-01-0/+35
| | | | | | | | | | | The following options can be now enabled via defconfig: - CONFIG_USB_ULPI - CONFIG_USB_ULPI_VIEWPORT - CONFIG_USB_ULPI_VIEWPORT_OMAP Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
* ehci-hcd: Add init_after_resetMateusz Kulikowski2016-04-01-0/+7
| | | | | | | | | | | | Some host controllers need addidional initialization after ehci_reset() In non-dm implementation it is possible to use CONFIG_EHCI_HCD_INIT_AFTER_RESET. This patch adds similar option to ehci drivers using dm. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* mmc: Add support for Qualcomm SDHCI controllerMateusz Kulikowski2016-04-01-0/+215
| | | | | | | | | | | Add support for SD/eMMC controller present on some Qualcomm Snapdragon devices. This controller implements SDHCI 2.0 interface but requires vendor-specific initialization. Driver works in PIO mode as ADMA is not supported by U-Boot (yet). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* gpio: Add support for Qualcomm gpio controllerMateusz Kulikowski2016-04-01-0/+170
| | | | | | | | | | Add support for gpio controllers on Qualcomm Snapdragon devices. This devices are usually called Top Level Mode Multiplexing in Qualcomm documentation. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* serial: Add support for Qualcomm serial portMateusz Kulikowski2016-04-01-0/+232
| | | | | | | | | This driver works in "new" Data Mover UART mode, so will be compatible with modern Qualcomm chips only. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* board: ti: DRA7: Add DP83867 TI phy for rev cDan Murphy2016-04-01-0/+7
| | | | | | | | | | | Enable the TI DP83867 Giga bit phy on the dra7 rev c board. The rx and tx internal delays are need for this board so the usage of RGMII_ID is required. Signed-off-by: Dan Murphy <dmurphy@ti.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* efi_loader: Always allocate the highest available addressAlexander Graf2016-04-01-0/+29
| | | | | | | | | | | | Some EFI applications (grub2) expect that an allocation always returns the highest available memory address for the given size. Without this, we may run into situations where the initrd gets allocated at a lower address than the kernel. This patch fixes booting in such situations for me. Signed-off-by: Alexander Graf <agraf@suse.de>
* sniper: Change vendor name from lge to lg, matching devicetree vendor prefixPaul Kocialkowski2016-04-01-3/+3
| | | | | | | This moves the sniper board from the lge to lg, in order to match the devicetree vendor prefix already defined in the kernel. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* kc1: Proper reboot mode and boot reason validationPaul Kocialkowski2016-04-01-13/+10
| | | | | | | | | | | | | | | With the previous implementation, rebooting without registering a recognized reboot mode would end up with U-Boot checking for a valid power-on reason, which might result in the device turning off (e.g. with no USB cable attached and no buttons pressed). Since this approach is not viable (breaks reboot in most cases), the validity of the reboot reason is checked (in turn, by checking that a warm reset happened, as there is no magic) to detect a reboot and the 'o' char is recognized to indicate that power-off is required. Still, that might be overridden by the detection of usual power-on reasons, on purpose. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* sniper: Proper reboot mode and boot reason validationPaul Kocialkowski2016-04-01-10/+23
| | | | | | | | | | | | | | | | | | With the previous implementation, rebooting without registering a recognized reboot mode (despite registering the magic) would end up with U-Boot checking for a valid power-on reason, which might result in the device turning off (e.g. with no USB cable attached and no buttons pressed). This was designed to catch reboots that are actually intended to be power-off, something that old Android kernels do, instead of properly turning the device off using the TWL4030. However, since this approach is not viable (breaks reboot in most cases), the validity of the reboot mode magic is checked to detect a reboot and the 'o' char is recognized to indicate that power-off is required. Still, that might be overridden by the detection of usual power-on reasons, on purpose. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* kc1: Add some sysboot and devicetree-related environment variablesPaul Kocialkowski2016-04-01-0/+2
| | | | | | This adds some environment variables for sysboot and devicetree. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* kc1: Select libfdt to allow running devicetree-based kernelsPaul Kocialkowski2016-04-01-0/+1
| | | | | | Selecting CONFIG_OF_LIBFDT allows running recent mainline kernels. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* kc1: Include explicit serial baudrate on bootargsPaul Kocialkowski2016-04-01-1/+1
| | | | | | This makes the baudrate for the kernel command line explicit. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* sniper: Include explicit serial baudrate on bootargsPaul Kocialkowski2016-04-01-1/+1
| | | | | | This makes the baudrate for the kernel command line explicit. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* arm64: booti: add missing unmap_sysmem()Masahiro Yamada2016-04-01-0/+5
| | | | | | | | | | | Make sure to call unmap_sysmem() for address allocated by map_sysmem() before leaving the function; however this patch gives no impact on the behavior because map_sysmem()/unmap_sysmem() does nothing except on Sandbox. Sandbox never runs this code because "booti" is a command for booting ARM64 kernel image. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* configs: ti_armv7_keystone2: make SYS_TEXT_BASE configurable at build timeVitaly Andrianov2016-04-01-0/+2
| | | | | | | | | | | U-boot for general purpose KS2 devices is loaded to the beginning of the internal memory (0x0c000000). Secure devices uses this memory and CONFIG_SYS_TEXT_BASE has to be different for those devices. This commit make this configurable at build time by giving CONFIG_SYS_TEXT_BASE as a command line definition to make command. Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
* arm: spl: Align default board_init_f comment with codeAndreas Dannenberg2016-04-01-1/+1
| | | | | | | | The default board_init_f() implementation performs a call to board_init_r() as the last step of the sequence. Fix the comment for this function to reflect the actual execution flow. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
* post: Remove references to scrapped "netta" board.Robert P. J. Day2016-04-01-67/+1
| | | | | | | | | | | Given that README.scrapyard shows scrapping of netta boards: netta2 powerpc mpc8xx c51c1c9a 2014-07-07 netta powerpc mpc8xx c51c1c9a 2014-07-07 delete netta example from POST tests. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* common: env_sf: Add exclamation markPeng Fan2016-04-01-1/+1
| | | | | | | | | | | | | Add exclamation mark to the errmsg, when error and set_default_env. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Mario Schuknecht <mario.schuknecht@dresearch-fe.de> Cc: Vignesh R <vigneshr@ti.com> Cc: Jagan Teki <jteki@openedev.com> Cc: Ravi Babu <ravibabu@ti.com> Cc: York Sun <york.sun@nxp.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* jffs2: Fix set but not used warningTom Rini2016-04-01-1/+2
| | | | | | | We only use 'ofs' in jffs2_sum_scan_sumnode when debugging as it's part of a dbg_summary call. Mark this as __maybe_unused. Signed-off-by: Tom Rini <trini@konsulko.com>
* lib/physmem.c: Switch to __weak for arch_phys_memsetTom Rini2016-04-01-4/+2
| | | | | | | We normally use __weak rather than calling it out directly as an alias. Update this function to the normal method. Signed-off-by: Tom Rini <trini@konsulko.com>
* post: Delete unnecessary bitmask of POST_MANUAL from POST_ALWAYSRobert P. J. Day2016-04-01-4/+4
| | | | | | | | | | | | | Since POST_ALWAYS is defined as: #define POST_ALWAYS (POST_NORMAL | \ POST_SLOWTEST | \ POST_MANUAL | \ POST_POWERON ) there is no need to redundantly bitmask it with POST_MANUAL. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* post: Remove reference to deleted "lwmon" board from MakefileRobert P. J. Day2016-04-01-1/+1
| | | | | | POST support for sample lwmon board was removed in commit e5d3078622. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>B
* Common: SPL: spl_nand: Fixed debug correct NAND ECC type.Ahmed Samir Khalil2016-04-01-0/+4
| | | | | | | | | | In case of #define DEBUG 1 (fordebugging SPL). A bug in spl_nand_load_image() will be triggered, because it prints using hw ecc regardless of soft ecc configurations and initializations. Signed-off-by: Ahmed Samir <engkhalil86@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* rpi: BCM2837 and Raspberry Pi 3 32-bit supportStephen Warren2016-04-01-2/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Raspberry Pi 3 contains a BCM2837 SoC. The BCM2837 is a BCM2836 with the CPU complex swapped out for a quad-core ARMv8. This can operate in 32- or 64-bit mode. 32-bit mode is the current default selected by the VideoCore firmware on the Raspberry Pi 3. This patch adds a 32-bit port of U-Boot for the Raspberry Pi 3. >From U-Boot's perspective, the only delta between the RPi 2 and RPi 3 is a change in usage of the SoC UARTs. On all previous Pis, the PL011 was the only UART in use. The Raspberry Pi 3 adds a Bluetooth module which uses a UART to connect to the SoC. By default, the PL011 is used for this purpose since it has larger FIFOs than the other "mini" UART. However, this can be configured via the VideoCore firmware's config.txt file. This patch hard-codes use of the mini UART in the RPi 3 port. If your system uses the PL011 UART for the console even on the RPi 3, please use the RPi 2 U-Boot port instead. A future change might determine which UART to use at run-time, thus allowing the RPi 2 and RPi 3 (32-bit) ports to be squashed together. The mini UART has some limitations. One externally visible issue in the BCM2837 integration is that the UART divides the SoC's "core clock" to generate the baud rate. The core clock is typically variable, and under control of the VideoCore firmware for thermal management reasons. If the VC FW does modify the core clock rate, UART communication will be corrupted since the baud rate will vary from the expected value. This was not an issue for the PL011 UART, since it is fed by a fixed 3MHz clock. To work around this, the VideoCore firmware can be told not to modify the SoC core clock. However, the only way this can happen and be thermally safe is to limit the core clock to a low/minimum frequency. This leaves performance on the table for use-cases that don't care about a UART console. Consequently, use of the mini UART console must be explicitly requested by entering the following line into config.txt: enable_uart=1 A recent version of the VC firmware is required to ensure that the mini UART is fully and correctly initialized by the VC FW; at least firmware.git 046effa13ebc "firmware: arm_loader: emmc clock depends on core clock See: https://github.com/raspberrypi/firmware/issues/572". Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: bcm2835: expand Kconfig target descriptionsStephen Warren2016-04-01-1/+27
| | | | | | | | This adds an explanation of which Raspberry Pi models each target option supports. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* rpi: add Raspberry Pi 3 board IDStephen Warren2016-04-01-0/+5
| | | | | | | | | | | | | | | | | | | | | | This allows U-Boot to known the name of the board. The existing rpi_2_defconfig can operate correctly on the Raspberry Pi 3 in 32-bit mode /if/ you have configured the firmware to use the PL011 UART as the console UART (the default is the mini UART). This requires two things: a) config.txt should contain dtoverlay=pi3-miniuart-bt b) You should run the following to tell the VC FW to process DT when booting, and copy u-boot.bin.img (rather than u-boot.bin) to the SD card as the kernel image: path/to/kernel/scripts/mkknlimg --dtok u-boot.bin u-boot.bin.img This works as of firmware.git commit 046effa13ebc "firmware: arm_loader: emmc clock depends on core clock See: https://github.com/raspberrypi/firmware/issues/572". Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* rpi: use constant "unknown board" DT filenameStephen Warren2016-04-01-5/+1
| | | | | | | | | | | To simplify support for new SoCs, just use a constant filename for the unknown case. In practice this case shouldn't be hit anyway, so the filename isn't relevant, and certainly doesn't need to differentiate between SoCs. If a user has an as-yet-unknown board, they can override this value in the environment anyway. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: bcm2835: move CONFIG_BCM283* to KconfigStephen Warren2016-04-01-3/+11
| | | | | Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* doc: clarify openssl-based key and certificate generation processAndreas Dannenberg2016-04-01-4/+4
| | | | | | | | Add some basic clarification that the dev.key file generated by OpenSSL contains both the public and private key, and further highlight that the certificate generated here contains the public key only. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
* doc: fix file extension for flattened image tree blobAndreas Dannenberg2016-04-01-1/+1
| | | | | | | | Different sections in the document suggest flattened image tree blob files have a file name extension of .itb. Fix the list of file extensions to reflect that. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
generated by cgit v1.1 at 2024-12-18 12:46:15 +0000