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* omap3: enable GP9 timer and UART2Albert ARIBAUD \(3ADEV\)2015-01-29-0/+9
| | | | | | These are needed for the upcoming Cairo board support. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* Nokia RX-51: Use generic boardPali Rohár2015-01-29-0/+1
| | | | | | | | Generic board with #define CONFIG_SYS_GENERIC_BOARD is working fine. There is no visible difference between legacy and generic board code. Signed-off-by: Pali Rohár <pali.rohar@gmail.com> Acked-by: Pavel Machek <pavel@ucw.cz>
* am335x_evm: Enable CONFIG_NAND_OMAP_GPMC_PREFETCHTom Rini2015-01-29-0/+1
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* ARM: OMAP5: DRA7xx: Add support for power rail groupingLubomir Popov2015-01-29-28/+118
| | | | | | | | | | | | | | | | | | | | | | On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC core rails. This concept of using one SMPS to supply multiple core domains (in various, although limited combinations, per primary device use case) has now become common and is used by many customer J6/J6Eco designs; it is supported by a number of corresponding PMIC OTP versions. This patch implements correct operation of the core voltages scaling routine by ensuring that each SMPS that is supplying more than one domain shall be written only once, and with the highest voltage of those fused in the SoC (or of those defined in the corresponding header if fuse read is disabled or fails) for the power rails belonging to the group. The patch also replaces some PMIC-related magic numbers with the appropriate definitions. The default OPP_NOM voltages for the DRA7xx SoCs are updated as well, per the latest DMs. Signed-off-by: Lubomir Popov <l-popov@ti.com>
* lcd: fix console address is not initializedBo Shen2015-01-28-0/+1
| | | | | | | | | | This commit 904672e (lcd: refactor lcd console stuff into its own file), which cause lcd console address is not initialized. This patch initialize the lcd console use the default value, will be update when splash screen is enabled. Signed-off-by: Bo Shen <voice.shen@atmel.com>
* Makefile: clean boot.binBo Shen2015-01-28-1/+1
| | | | | | | | | When build for Atmel related boards which support SPL, it will generate boot.bin, also clean when it when do "make clean" operation. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* spl: Change printf to puts for "Unsupported boot-device"Stefan Roese2015-01-28-1/+1
| | | | | | | | | | | | | | Microblaze currently doesn't use printf in SPL. So this one line was the only reference to it and resulted in the printf functionality to be pulled in. Exceeding the 4k size limit. Lets change the printf back to puts so that Microblaze is fixed again. The only drawback is that the detected boot-device number will not be printed. But this message alone should be helpful enough to get an idea where the boot process is broken. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2015-01-26-288/+1078
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| * x86: config: chromebook_link: Enable environmentSimon Glass2015-01-24-0/+7
| | | | | | | | | | | | | | Enable an environment area. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: ivybridge: Drop the Kconfig MRC cache informationSimon Glass2015-01-24-28/+0
| | | | | | | | | | | | This is now stored in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: config: Enable hook for saving MRC configurationSimon Glass2015-01-24-0/+6
| | | | | | | | | | | | | | Add a hook to ensure that this information is saved. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Implement a cache for Memory Reference Code parametersSimon Glass2015-01-24-0/+464
| | | | | | | | | | | | | | | | | | | | | | The memory reference code takes a very long time to 'train' its SDRAM interface, around half a second. To avoid this delay on every boot we can store the parameters from the last training sessions to speed up the next. Add an implementation of this, storing the training data in CMOS RAM and SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: dts: Add SPI flash MRC details for chromebook_linkSimon Glass2015-01-24-1/+14
| | | | | | | | | | | | | | | | Correct the SPI flash compatible string, add an alias and specify the position of the MRC cache, used to store SDRAM training settings for the Memory Reference Code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * Allow architecture-specific memory reservationSimon Glass2015-01-24-0/+7
| | | | | | | | | | | | | | All memory to be reserved for use after relocation by adding a new call to perform this reservation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: spi: Add device tree supportSimon Glass2015-01-24-0/+8
| | | | | | | | | | | | | | As a temporary measure before the ICH driver moves over to driver model, add device tree support to the driver. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: rtc: mc146818: Add helpers to read/write CMOS RAMSimon Glass2015-01-24-48/+105
| | | | | | | | | | | | | | On x86 we use CMOS RAM to read and write some settings. Add basic support for this, including access to registers 128-255. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Use ipchecksum from net/Simon Glass2015-01-24-97/+4
| | | | | | | | | | | | | | The existing IP checksum function is only accessible to the 'coreboot' cpu. Drop it in favour of the new code in the network subsystem. Signed-off-by: Simon Glass <sjg@chromium.org>
| * net: Add a separate file for IP checksummingSimon Glass2015-01-23-0/+91
| | | | | | | | | | | | | | | | Move the checksum code out into its own file so it can be used elsewhere. Also use a new version which supports a length which is not a multiple of 2 and add a new function to add two checksums. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: dts: Add compatible string for Intel ICH9 SPI controllerSimon Glass2015-01-23-0/+2
| | | | | | | | | | | | | | Add this to the enum so that we can use the various fdtdec functions. A later commit will move this driver to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
| * pci: tegra: Fix port information parsingSjoerd Simons2015-01-23-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | commit a62e84d7b1824a202dd incorrectly changed the tegra pci code to the new fdtdec pci helpers. To get the device index of the root port, the "reg" property should be parsed from the dtb (as was previously the case). With this patch i can successfully network boot my jetson tk1 Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * x86: Fix various code format issues in start16.SBin Meng2015-01-23-10/+10
| | | | | | | | | | | | | | | | | | | | | | Various minor code format issues are fixed in start16.S: - U-boot -> U-Boot - 32bit -> 32-bit - Use TAB instead of SPACE to indent - Move the indention location of the GDT comment block Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Test mtrr support flag before accessing mtrr msrBin Meng2015-01-23-2/+19
| | | | | | | | | | | | | | | | | | | | On some x86 processors (like Intel Quark) the MTRR registers are not supported. This is reflected by the CPUID (EAX 01H) result EDX[12]. Accessing the MTRR registers on such processors will cause #GP so we must test the support flag before accessing MTRR MSRs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Save mtrr support flag in global dataBin Meng2015-01-23-6/+14
| | | | | | | | | | | | | | | | CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this flag in x86_cpu_init_f() and save it in global data. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add missing DECLARE_GLOBAL_DATA_PTR for mtrr.cBin Meng2015-01-23-0/+2
| | | | | | | | | | | | | | | | arch/x86/cpu/mtrr.c has access to the U-Boot global data thus DECLARE_GLOBAL_DATA_PTR is needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: config: Always scroll the display by 5 lines, for speedSimon Glass2015-01-23-0/+1
| | | | | | | | | | | | | | | | Scrolling a line at a time is very slow for reasons that I don't understand. It seems to take about 100ms to copy 4MB of RAM in the frame buffer. To cope with this, scroll 5 lines each time. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: video: Add support for CONFIG_CONSOLE_SCROLL_LINESSimon Glass2015-01-23-9/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | Some machines are very slow to scroll their displays. To cope with this, support the CONFIG_CONSOLE_SCROLL_LINES option. Setting this to 5 allows the display to operate at an acceptable speed by scrolling 5 lines at a time. This same option is available for LCDs so when these systems are unified this code can be unified also. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
| * x86: Access the VGA ROM when neededSimon Glass2015-01-23-2/+42
| | | | | | | | | | | | | | Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Fix out of bounds irq handlers accessSebastien Ronsse2015-01-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using coreboot-x86_defconfig, the following error occurred prior to this modification: CC arch/x86/lib/interrupts arch/x86/lib/interrupts.c: In function ‘do_irqinfo’: arch/x86/lib/interrupts.c:134:24: error: iteration 16u invokes undefined behavior [-Werror=aggressive-loop-optimizations] if (irq_handlers[irq].handler != NULL) { ^ arch/x86/lib/interrupts.c:133:2: note: containing loop for (irq = 0; irq <= CONFIG_SYS_NUM_IRQS; irq++) { ^ cc1: all warnings being treated as errors scripts/Makefile.build:275: recipe for target 'arch/x86/lib/interrupts.o' failed make[1]: *** [arch/x86/lib/interrupts.o] Error 1 Makefile:1093: recipe for target 'arch/x86/lib' failed make: *** [arch/x86/lib] Error 2 Change-Id: I3572a822081b72ab760f1eb99442e1161d3d167e Signed-off-by: Sebastien Ronsse <sronsse@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: ahci: Make sure interface is not busy after enabling the portBin Meng2015-01-23-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each time U-Boot boots on Intel Crown Bay board, the displayed hard drive information is wrong. It could be either wrong capacity or just a 'Capacity: not available' message. After enabling the debug switch, we can see the scsi inquiry command did not execute successfully. However, doing a 'scsi scan' in the U-Boot shell does not expose this issue. SCSI: Target spinup took 0 ms. SATA link 1 timeout. AHCI 0001.0100 32 slots 2 ports 3 Gbps 0x3 impl SATA mode flags: ncq stag pm led clo only pmp pio slum part ccc apst scanning bus for devices... ahci_device_data_io: 0 byte transferred. <--- scsi inquiry fails ahci_device_data_io: 512 byte transferred. ahci_device_data_io: 512 byte transferred. ahci_device_data_io: 512 byte transferred. Device 0: (0:0) Vendor: ATA Prod.: Rev: ?8 Type: Hard Disk Capacity: 912968.3 MB = 891.5 GB (1869759264 x 512) Found 1 device(s). So uninitialized contents on the stack were passed to dev_print() to display those wrong information. The symptom were observed on two hard drives (one is Seagate, the other one is Western Digital). The fix is to make sure the AHCI interface is not busy by checking the error and status information from task file register after enabling the port in ahci_port_start() before proceeding other operations like scsi_scan(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: Drop the x86_fb driverSimon Glass2015-01-23-49/+1
| | | | | | | | | | | | | | | | Now that we have a full VESA driver we may as well use that. We need to support the VESA layer being set up by early start-up code or by running a VGA ROM. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Add a VESA video driverSimon Glass2015-01-23-0/+75
| | | | | | | | | | | | | | | | | | Add a driver intended to cope with any VESA-compatible x86 graphics adapter. It will not support ROMs which use OpenFirmware (Forth) since there is no support for that in U-Boot. This means that MAC OS cards will not work. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: pci: Don't stop when we get a vendor/device mismatchSimon Glass2015-01-23-1/+1
| | | | | | | | | | | | | | These are quite common and we may as well press on and not be so picky. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * bios_emulator: Add some VESA interface debuggingSimon Glass2015-01-23-22/+148
| | | | | | | | | | | | Allow the supported modes to be listed when in debug mode. Signed-off-by: Simon Glass <sjg@chromium.org>
| * bios_emulator: Don't display error when emulator terminatesSimon Glass2015-01-23-1/+1
| | | | | | | | | | | | As it turns out this is a normal condition, so suppress the error. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Support ROMs on other archsSimon Glass2015-01-23-1/+8
| | | | | | | | | | | | | | | | We shouldn't assume that the VGA ROM can always be loaded at c0000. This is only true on x86 machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Correct endianness isues in pci_romSimon Glass2015-01-23-11/+14
| | | | | | | | | | | | | | | | This code is too x86-dependent at present. Correct it so that it can run on big-endian machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * bios_emulator: Fix an #ifdef typo in the header fileSimon Glass2015-01-23-1/+1
| | | | | | | | | | | | | | This stops the debug mode from working properly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-01-26-21/+109
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| * | ARM: atmel: sama5d4_xplained: enable usb ethernet gadgetBo Shen2015-01-19-0/+8
| | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5d4_xplained: add option for usb ethernet gadgetBo Shen2015-01-19-0/+11
| | | | | | | | | | | | | | | | | | | | | Add the option for USB Ethernet gadget based on atmel usb device. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5d4ek: enable usb ethernet gadgetBo Shen2015-01-19-0/+8
| | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5d4ek: add option for usb ethernet gadgetBo Shen2015-01-19-0/+11
| | | | | | | | | | | | | | | | | | | | | Add the option for USB Ethernet gadget based on atmel usb device. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5d4: add usb device initial codeBo Shen2015-01-19-0/+16
| | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5d4: add usb platform dataBo Shen2015-01-19-1/+1
| | | | | | | | | | | | | | | | | | The SAMA5D4 has the same usb platform data with SAMA5D3 SoC. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | arm: at91: snapper9260: Drop invalid CONFIG_SKIP_RELOCATE_UBOOTSimon Glass2015-01-19-1/+0
| | | | | | | | | | | | | | | | | | This config is not valid, so drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | ARM: at91: sama5d3_xplained: spl: enable PMECC header generationWu, Josh2015-01-19-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | As sama5d3 xplained support the PMECC. So add the PMECC header for spl binary. That make ROM loader can use PMECC to avoid error flips in spl code in nandflash. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com>
| * | arm, at91, axm: add SPL support for axmHeiko Schocher2015-01-19-2/+3
| | | | | | | | | | | | | | | | | | add SPL support also for the axm board. Signed-off-by: Heiko Schocher <hs@denx.de>
| * | arm, at91: corvus board updatesHeiko Schocher2015-01-19-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - corvus board fix problems with toshiba nand chips on the corvus board problems with toshiba chips Manufacturer ID: 0x98 Chip ID: 0xdc encounterd. Solve this in the following way: - set other nand timings - enable CONFIG_SYS_NAND_READY_PIN - correct the MACH_TYPE setting Signed-off-by: Heiko Schocher <hs@denx.de>
| * | taurus, spl: erase also spi flash if recovery button is pressedHeiko Schocher2015-01-19-10/+32
| | | | | | | | | | | | | | | | | | | | | if in SPL mode recovery button is pressed, erase also spi flash from offset 0 to CONFIG_SYS_NAND_U_BOOT_SIZE on the taurus board. Signed-off-by: Heiko Schocher <hs@denx.de>
| * | arm, at91: enable thumb mode for taurus board in SPLHeiko Schocher2015-01-19-0/+5
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
generated by cgit v1.1 at 2024-11-30 00:33:20 +0000