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* MLK-13645 mx7ulp: Modify FDT file to disable SD3.0 for mfgtoolimx_v2016.03_4.1.30_7ulp_alphaYe Li2016-12-23-0/+40
| | | | | | | | | | Since the SD3.0 kernel driver needs M4 image support, this causes problem to mfgtool. To decouple the relationship, we modify the FDT file in u-boot to disable SD3.0 when booting for mfgtool. So the kernel won't depend on M4 image. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Fugang Duan <fugang.duan@nxp.com> (cherry picked from commit 1826d6e4dc732521190c742f812193be95eea211)
* MLK-13624 configs: imx7ulp_evk: add net args for USB NFS bootAndy Duan2016-12-16-1/+1
| | | | | | | | i.MX7ULP has no ENET controller, and kernel enable wlan0 and USB eth0 interface by default, set the net args interface to eth0 to force kernel NFS boot from USB ethernet. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
* MLK-13602-3 mx6ullevk/arm2: Enable module fuse checking for mx6ull boardsYe Li2016-12-14-0/+17
| | | | | | | | Enable the module disable fuse checking configurations, and ENET fuse checking during ENET setup. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Bai Ping <ping.bai@nxp.com>
* MLK-13602-2 epdc: Add disable fuse checkingYe Li2016-12-14-0/+20
| | | | | | | | Add fuse checking for EPDC module. Once the fused is programmed, the EPDC module is disabled, can't to access it. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Bai Ping <ping.bai@nxp.com>
* MLK-13602-1 mx6: Add i.MX6ULL fused modules checking supportYe Li2016-12-14-1/+44
| | | | | | | Add the modules disable fuses mapping with FDT nodes and devices name. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Bai Ping <ping.bai@nxp.com>
* MLK-13586-2 mx7d_arm2/sabresd: Update ddr3 script to V2.0 for Bank interleaveYe Li2016-12-12-109/+155
| | | | | | | | | | | | | | | | | | | | | | To improve the performance, enable the bank interleave for DDR3. Update the DDR3 settings to new script IMX7D_DDR3_533MHz_1GB_32bit_V2.0.ds Changes: 1. Enable bank interleave 2. Improve the drive strength for non-TO1.1 chips. 3. Updates ZQ_CON0 settings. 4. For 19x19 DDR3 ARM2 and 12x12 DDR3 ARM2, they are using old version scripts which were not upgrade with SABRESD script. According to DDR owner suggestion, to use same version script for all of them. File: http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153&objAction=browse&sort=name&viewType=1 Test: Passed stress test on one TO1.2 SABRESD, one TO1.1 SABRESD and one TO1.0 SABRESD. Passed stress test on one 12x12 ddr3 ARM2. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13586-1 mx7d_arm2: Update lpddr3 script to V2.0 for Bank interleaveYe Li2016-12-12-60/+88
| | | | | | | | | | | | | | | | | | | | To improve the performance, enable the bank interleave for LPDDR3. Update the LPDDR3 settings to new script IMX7D_LPDDR3_533MHz_2GB_32bit_V2.0.ds5. Changes: 1. Enable bank interleave 2. Improve the drive strength for non-TO1.1 chips. 3. Updates ZQ_CON0 settings. 4. Change to 0 for reserved bits. File: http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153&objAction=browse&sort=name&viewType=1 Test: Passed stress test on one 19x19 lpddr3 arm2 and one 12x12 lpddr3 arm2. Passed LPSR test on one 12x12 lpddr3 arm2. Signed-off-by: Ye Li <ye.li@nxp.com>
* MXSCM-237 mx6dqscm: qwks: add support for qwks rev3Juan Gutierrez2016-12-08-1/+32
| | | | | | | | | | | Support for the i.MX SX SCM QWKS rev3. The new revision has support for ov5642 camera, bluetooth and wifi support. Providing configuration files for: - Regular 1gb board - spinor Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-236 mx6dqscm: adjust some ddr calibration parametersJuan Gutierrez2016-12-08-13/+16
| | | | | | | | | | | Some adjustment to the ddr configuration like: - Precharge all commands per JEDEC - Fix the space partition values for 2Gb - Fix other values that reduce yield of scm parts per testing perfomed Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MLK-13584 configs: imx7ulp/imx6sll: enable Realtek usb-net dongle supportAndy Duan2016-12-08-0/+3
| | | | | | | | | | Enable Realtek usb-net dongle support in default for below platforms that have no Ethernet controller: - mx7ulp evk - mx6sll evk - mx6sll arm2 Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
* MLK-13582 net: usb: r8152: allocate cache-aligned buffer for usb transfer ↵Andy Duan2016-12-08-5/+15
| | | | | | | | buffers Transfer the cache-aligned buffer for usb transfer buffer. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
* MLK-13546 mx7ulp_arm2: Add validation board supportYe Li2016-12-02-0/+980
| | | | | | | | | | | | | This patch addes board level codes for MX7ULP ARM2 board. Since only 14x14 ARM2 board is ready, we only support this board. 10x10 board will support in future. eMMC/SD1/UART are ready in this patch. Other modules need board rework to test. Build target: mx7ulp_14x14_arm2_config Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13551: mx6ull: evk: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+3
| | | | | | | | | | | | LPDDR2 script IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.2.inc Updated to add precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13451-2: mx6ul: arm2: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+3
| | | | | | | | | | | | LPDDR2 script IMX6UL_LPDDR2_400MHz_16bit_V1.1.inc Updated to add precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13451-1: mx6ul: evk: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+3
| | | | | | | | | | | | LPDDR2 script IMX6UL_LPDDR2_400MHz_16bit_V1.1.inc Updated to add precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13540-2: mx6sx: arm2: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+6
| | | | | | | | | | | | LPDDR2 script MX6SX_19x19_LPDDR2_JEDEC.inc Updated to add Precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13540-1: mx6sx: arm2: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+6
| | | | | | | | | | | | | LPDDR2 script MX6SX_19x19_LPDDR2_JEDEC.inc Updated to add Precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13539: mx6sl: evk: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+3
| | | | | | | | | | | | LPDDR2 script MX6SL_MMDC_LPDDR2_register_programming_aid_v0.9.inc Updated to add Precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MXSCM-222 usb: fix swbst_mode to properly power usbJuan Gutierrez2016-12-01-1/+1
| | | | | | | | | | The definition of the SWBST_MODE_AUTO at the pfuze100_pmic.h file changed between uboot versions. On the previous version the shift to the proper bit field was part of the macro. In the uboot v2016 this macro does not include the shift and needs to be performed explicitly to properly modify the SWBST_MODE bit field. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-213: remove dmfc from boot arguments for mx6scm boardsJuan Gutierrez2016-12-01-5/+2
| | | | | | | | | | | | Intially this parameter was added to fix a video stuttering but with L4.1 the video issue is not present so we can safely get rid of this parameter. When using both ldb interfaces in separate mode and passing the dmfc argument as boot parameter to the kernel, a distortion on both displays is observed when rendering to the secondary display. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-212: mx6dqscm: usb: fix usb_otg_id iomux pad settingsJuan Gutierrez2016-12-01-0/+8
| | | | | | | | | | USB_OTG_ID iomux pad was missconfigured and not selecting the GPIO1 Alternative for QWKS and the ENET_RX_ERR for EVB, as a consequence when connecting a USB device the PWR_EN was disabled. So usb function like "usb start" was not working as it should. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MLK-13545 mx7ulp: Add HAB boot supportYe Li2016-12-01-0/+30
| | | | | | | | | | Add CAAM clock functions, SEC_CONFIG[1] fuse checking, and default CSF size for HAB support boot on mx7ulp. Users need to uncomment the CONFIG_SECURE_BOOT in mx7ulp_evk.h to build secure uboot. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13544 mx7ulp: Modify MX7ULP arch codes to use imx-commonYe Li2016-12-01-39/+24
| | | | | | | | This patch modifies MX7ULP arch codes to reuse some functions already in imx-common, like cache and HAB. To do this, we need to add a dummy SOC type and chip type for MX7ULP and its relevant checking. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13547 configs: mx7ulp_evk: enable ethernet boot supportPeter Chen2016-11-30-0/+29
| | | | | | | | Since we can use USB ethernet instead of local ethernet, add ethernet support for it. To use USB ethernet function at u-boot, just plug in Micro-AB cable at USBOTG1 port with USB2Ethernet adapter connected. Signed-off-by: Peter Chen <peter.chen@nxp.com>
* MLK-13532 misc: ocotp: ulp: fix fuse readPeng Fan2016-11-29-1/+2
| | | | | | | There is no hole in i.MX7ULP1 OCOTP space, so the phy_index is the same one with index. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13525-2 mx7ulp_evk: Add plugin boot supportYe Li2016-11-25-2/+232
| | | | | | | Add plugin boot support for EVK board. The DDR init codes are updated to v1.2 DDR script. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13525-1 mx7ulp: Add common plugin codes for mx7ulpYe Li2016-11-25-0/+105
| | | | | | | Add common plugin codes to call ROM's hwcnfg_setup and generate IVT2 header. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13509 mx7ulp_evk: Update DDR script to v1.2Ye Li2016-11-25-1/+4
| | | | | | | | | | | | | | | | | | | | DDR script is updated to v1.2 for EVK board to fix DQS gating issue and add pre-charge .That DQS sampling may have problem after we enabling the SDE_0/SDE_1 in MDCTL. Changes: -Issue a Precharge-All command prior to the MRW Reset command. setmem /32 0x40AB001C = 0x00008050 // [MMDC_MDSCR] precharge all to CS0 -Based on V1.1, move the "Read DQS Gating Disable" to the step after "MR setting", to avoid potential DDR initializaiton failures (especially in Plugin Mode). File: EVK_IMX7ULP1_LPDDR3_320MHz_1GB_32bit_V1.2.inc Test: Passed stress test on 1 board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13508-2 mx6sllarm2: Update DDR script to v2.3Ye Li2016-11-24-9/+11
| | | | | | | | | | | | | | | | | | | DDR scripts are updated to fix DQS gating issue commonly for LPDDR2 and LPDDR3. That DQS sampling may have problem after enabling the SDE_0/SDE_1 in MDCTL. Changes: -Based on V2.2, move the "Read DQS Gating Disable" to the step after "MR setting", to avoid potential DDR initializaiton failures (especially in Plugin Mode). File: http://compass.freescale.net/livelink/livelink?func=ll&objid=235701297&objAction=browse&sort=name&viewType=1 Test: Passed stress test on 1 LPDDR2 ARM2 board and 1 LPDDR3 ARM2 board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13508-1 mx6sllevk: Update DDR script to v2.2Ye Li2016-11-24-4/+5
| | | | | | | | | | | | | | | | | | DDR script is updated to v2.2 to fix potential DQS gating issue. That DQS sampling may have problem after enabling the SDE_0/SDE_1 in MDCTL. Changes: -Based on V2.1.1, move the "Read DQS Gating Disable" to the step after "MR setting", to avoid potential DDR initializaiton failures (especially in Plugin Mode). File: http://compass.freescale.net/livelink/livelink?func=ll&objid=235701297&objAction=browse&sort=name&viewType=1 Test: Passed stress test on two boards. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-19 imx: mx7ulp_evk: Add EVK boards support codesYe Li2016-11-22-0/+729
| | | | | | | | | | | | | | Add basic support for i.MX7ULP EVK board. I2C, SD/eMMC, UART, QSPI and USB are added. Use target mx7ulp_evk_config to select the configuration. Use mx7ulp_evk_emmc_config for eMMC boot. Use mx7ulp_evk_m4boot_config for binding and booting m4 image in single boot mode. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-18 wdog: Add the watchdog driver for MX7ULP.Ye Li2016-11-22-0/+93
| | | | | | | | | | | | This driver implements the HW WATCHDOG functions. Which needs to set CONFIG_HW_WATCHDOG to use them. This is disabled by default for mx7ulp. We will use watchdog for reset cpu. Implement this in the driver. Need to define CONFIG_ULP_WATCHDOG to build it. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-17 sf: Add Macronix MX25R6435F SPI NOR flash to flash parameters arrayYe Li2016-11-22-0/+1
| | | | | | | On mx7ulp EVK board, we use MX25R6435F NOR flash, add its parameters and IDs to flash parameter array. Otherwise, the flash probe will fails. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-16 fsl_qspi: Update changes for mx7ulpYe Li2016-11-22-1/+16
| | | | | | | | | | | | | The mx7ulp has small TX/RX FIFO (64Bytes) and AHB buffer size (128Bytes) than other i.MX. Change some parameters for it. Also found when the DDR_EN bit is set, sometime the page programming will fail during large data programming. The 64 bytes data is not programmed into flash. But when DDR_EN is clear, there is no such issue. Suspect this is a IC issue. We have disable the DDR_EN for mx7ulp. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13450-15 ehci-mx6: Add powerup_fixup implementationYe Li2016-11-22-0/+25
| | | | | | | | | | | | | | | | | | | | When doing port reset, the PR bit of PORTSC1 will be automatically cleared by our IP, but standard EHCI needs explicit clear by software. The EHCI-HCD driver follow the EHCI specification, so after 50ms wait, it clear the PR bit by writting to the PORTSC1 register with value loaded before setting PR. This sequence is ok for our IP when the delay time is exact. But when the timer is slower, some bits like PE, PSPD have been set by controller automatically after the PR is automatically cleared. So the writing to the PORTSC1 will overwrite these bits set by controller. And eventually the driver gets wrong status. We implement the powerup_fixup operation which delays 50ms and will check the PR until it is cleared by controller. And will update the reg value which is written to PORTSC register by EHCI-HCD driver. This is much safer than depending on the delay time to be accurate and aligining with controller's behaiver. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-14 ehci-mx6: Update EHCI driver to support OTG0 on i.MX7ULPYe Li2016-11-22-5/+33
| | | | | | | | | | | The ULP has two USB controllers. These two controllers have similar NC registers layout as i.MX7D. But OTG0 uses UTMI PHY simliar as i.MX6, not the integrated PHY on i.MX7D. The OTG1 needs off-chip HSIC PHY or ULPI PHY to work. This patch only supports OTG0 with UTMI PHY. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-13 mxc_ocotp: Update driver to support OCOTP controller on i.MX7ULPYe Li2016-11-22-0/+50
| | | | | | | | Update the mxc_ocotp driver to support i.MX7ULP. The read/write sequence has some changes due to PDN and OUT_STATUS registers added and TIME register is removed. Also update the bank size and number. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-12 gpio: Add Rapid GPIO2P driver for i.MX7ULPYe Li2016-11-22-0/+255
| | | | | | | | | | | | | | Add the imx_rgpio2p driver for Rapid GPIO2P controllers on i.MX7ULP. Have added all ports on RGPIO2P_0 and RGPIO2P_1. The configurations CONFIG_IMX_RGPIO2P and CONFIG_DM_GPIO must be set to y to enable the drivers. To use the GPIO function, the IBE and OBE needs to set in IOMUXC. We did not set the bits in driver, but leave them to IOMUXC settings of the GPIO pins. User should use IMX_GPIO_NR to generate the GPIO number for gpio APIs access. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-11 mx7ulp: Implement the clock functions for i2c driverYe Li2016-11-22-0/+44
| | | | | | | Implement the i2c clock enable and get function for mx7ulp. These functions are required by imx_lpi2c driver. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-10 lpi2c: Add I2C driver for lpi2c module on i.MX7ULPYe Li2016-11-22-0/+1037
| | | | | | | | | | | | The i.MX7ULP uses LPI2C as i2c module. It has 8 instances and A7 core domain owns the LPI2C4 to LPI2C7. Add this driver working for the LPI2C module. Users need to define CONFIG_SYS_I2C_IMX to enable the driver and define CONFIG_SYS_I2C_IMX_LPI2Cx for the i2c instance. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
* MLK-13450-9 mx7ulp: Add lpuart DM device and clock supportYe Li2016-11-22-3/+45
| | | | | | | Add the DM device and re-implement the imx_get_uartclk according to the LPUART_BASE configuration. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-8 serial_lpuart: Add 32LE support for i.MX7ULPYe Li2016-11-22-3/+219
| | | | | | | | | | | | | Modify the lpuart to support the register access in little endian way with 32bits for i.MX7ULP. Need to enable CONFIG_LPUART_32LE_REG for the using. Also add the lpuart_fsl register structure and registers bits definitions in registers header file. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Teo Hall <teo.hall@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
* MLK-13450-7 mx7ulp: Add M4 core boot support when using single boot modeYe Li2016-11-22-0/+46
| | | | | | | | | | | | | | | | | | The single boot mode in MX7ULP will only boot up A7, the M4 is running in ROM by checking entry from SIM0 GP register. In this patch, We bind M4 image with u-boot.bin before attaching the imx header. So the whole image (included M4 image) will be loaded by A7 ROM into DDR. Then when u-boot is up, it will try to load M4 image into TCML and boot it there. Since M4 image will not be relocated in u-boot codes, we must load it during board_f. Current implementation put it in arch_cpu_init to get M4 booted as quick as possible. We requires the M4 image with IVT head and padding embedded, not a RAW binary. The image should be same as what is used for M4 QSPI boot in dual boot mode. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-6 mx7ulp: Add soc level initialization codes and functionsYe Li2016-11-22-1/+322
| | | | | | | | | | | | Implement soc level functions to get cpu rev, reset cause, enable cache, etc. We will disable the wdog and init clocks in s_init at very early u-boot phase. Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev is hard coded to a fixed value. This may change in future. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-5 mx7ulp: Add clock framework and functionsYe Li2016-11-22-1/+2391
| | | | | | | | | | | | | | | | | Add a clock framework to support SCG1/PCC2/PCC3 for A7 to support get/set clock source, divider, clock rate and parent source. Users need to include pcc.h to use the APIs to for peripherals clock. Each peripheral clock is defined in enum pcc_clk type. SCG relevants APIs are defined in scg.h which supports clock rate get, PLL/PFD enablement and settings, and all SCG clock initialization. User need use enum scg_clk to access each clock source. In clock.c, we initialize necessary clocks at u-boot s_init and implement the clock functions used by driver modules to operate clocks dynamically. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-4 mx7ulp: Add iomux pins header fileYe Li2016-11-22-0/+910
| | | | | | | | | | | | Add the iomux pins header file from iomux tool team. Change the IOMUXC0 pins to add IOMUX_CONFIG_MPORTS flags. Note: The IOMUXC0 offset provided in this file is from 0xD000, this is not aligned with IOMUXC0 base address. We have adjusted the IOMUXC0 base address to aligin with it. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-3 mx7ulp: Add iomux driver to support IOMUXC0 and IOMUXC1Ye Li2016-11-22-0/+170
| | | | | | | | | | Add a new driver under ULP directory to support its IOMUXC controllers. The ULP has two IOMUXC, the IOMUXC0 is used for M4 domain, while IOMUXC1 is for A7. We set IOMUXC1 as the default IOMUX in this driver. Any pins in IOMUXC0 needs to configure with IOMUX_CONFIG_MPORTS in its mux_mode field. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-2 mx7ulp: Add registers address header fileYe Li2016-11-22-0/+1151
| | | | | | | | Add imx-regs.h for i.MX7ULP registers addresses definitions and some registers structures. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-1 mx7ulp: Add new i.MX series mx7ulp to KconfigYe Li2016-11-22-1/+19
| | | | | | | | | Since mx7ulp is a new series which have different architecture as previous i.MX platforms. We create a new cpu folder for it. This patch addes it to Kconfig. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13486: imx: logos: use NXP logoPeng Fan2016-11-22-0/+0
| | | | | | | | Use NXP logo. The vendor and board dir not changed, only replace the contents of freescale.bmp. Signed-off-by: Peng Fan <peng.fan@nxp.com>
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