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* MLK-13124 ARM: imx: update the REFTOP_VBGADJ settingBai Ping2016-08-25-6/+32
| | | | | | | | | | | | | | | | | Per to design team, we need to set REFTOP_VBGADJ in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the actually table is as below: '000' - set REFTOP_VBGADJ[2:0] to 3b'110 '110' - set REFTOP_VBGADJ[2:0] to 3b'000 '001' - set REFTOP_VBGADJ[2:0] to 3b'001 '010' - set REFTOP_VBGADJ[2:0] to 3b'010 '011' - set REFTOP_VBGADJ[2:0] to 3b'011 '100' - set REFTOP_VBGADJ[2:0] to 3b'100 '101' - set REFTOP_VBGADJ[2:0] to 3b'101 '111' - set REFTOP_VBGADJ[2:0] to 3b'111 Signed-off-by: Bai Ping <ping.bai@nxp.com>
* MLK-13115 imx: mx6ullevk: Update LPDDR2 script for i.MX6ULL 9x9 EVKYe Li2016-08-23-4/+4
| | | | | | | | | | | | | | | | | | Update the LPDDR2 script to 1.2 rev with delay line settings changed. File: IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.2.inc https://nxp1.sharepoint.com/teams/123/IMX6ULL/SitePages/Documents.aspx Changes: Update Delay Line Settings based on the delay line calibration results of more boards. MMDC_MPRDDLCTL = 0x40403439 MMDC_MPWRDLCTL = 0X4040342D Test: One 9x9 EVK board pass stress memtester. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13070 imx: mx6ullevk: Add 9x9 EVK supportYe Li2016-08-12-21/+27
| | | | | | | | | | | | | | | | Add two build configs for i.MX6ULL 9X9 EVK. And update lpddr2 script for the board to version 1.0. DDR script: IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.0.inc Changes: Initial version Test: Passed memtester overnight test on 1 board. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12929 imx6ull: support splash screen for epdcRobby Cai2016-07-29-1/+322
| | | | | | | add splash screen feature for epdc. it's tested on imx6ull arm2 board. Signed-off-by: Robby Cai <robby.cai@nxp.com>
* MLK-12996 imx: mx6dqp/dq: Fix SATA read/write fail after booting from SATAYe Li2016-07-29-4/+14
| | | | | | | | | | | | | | We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET ref clock will impact the SATA ref 100Mhz clock. If SATA is initialized before this changing, SATA read/write can't work after it. And we have to re-init SATA. The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing. This patch is an work around that moves the ENET clock setting (enable_fec_anatop_clock) from ethernet init to board_init which is prior than SATA initialization. So there is no PLL6 change after SATA init. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12998 imx: mx6ullevk: Add build targets for boot devicesYe Li2016-07-26-0/+15
| | | | | | Add build targets for eMMC, NAND and QSPI NOR. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12964 imx: enlarge mux width to 4Peng Fan2016-07-22-8/+7
| | | | | | For i.MX6, the mux width is 4, not 3. So enlarge the width. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12988 imx: mx6ull Add board support for i.MX6ULL EVKYe Li2016-07-19-0/+2088
| | | | | | | | | | | | | | | | | | | | | Add configs and board level codes for i.MX6ULL 14x14 EVK. Very similar board from i.MX6UL EVK. I2C, UART, USB, QSPI, SD, ENET and LCD are ok to work. The codes for i.MX6ULL 9x9 EVK is kept. We will add 9x9 build target when it is needed. The DDR3 script is using version 1.2: File: EVK_IMX6ULL_DDR3L_400MHz_512MB_16bit_V1.2_NewDRAM.inc Test: 3 boards passed memtester. Build target: mx6ull_14x14_evk_defconfig Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12985 imx: mx6sx: Disable ENET clock before switching clock parentYe.Li2016-07-15-0/+5
| | | | | | | Need to gate ENET clock when switching to a new clock parent, because the mux is not glitchless. Signed-off-by: Ye.Li <ye.li@nxp.com>
* dfu: avoid memory leakPeng Fan2016-07-01-1/+3
| | | | | | | | | | | | | | | | When dfu_fill_entity fail, need to free dfu to avoid memory leak. Reported by Coverity: " Resource leak (RESOURCE_LEAK) leaked_storage: Variable dfu going out of scope leaks the storage it points to. " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: "Łukasz Majewski" <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> (cherry picked from commit 5d8fae79163e94671956c99654abf48cf49757ba)
* MLK-12894 imx6ull: adjust the ldo 1.2v bandgap voltage on i.mx6ullBai Ping2016-06-08-0/+7
| | | | | | | | Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop MISC0 bit[6:4]) setting to 2b'110. Signed-off-by: Bai Ping <ping.bai@nxp.com>
* MLK-12889 mx6ullarm2: Update DDR script to version 2.2Ye Li2016-06-08-2/+2
| | | | | | | | | | | | | | File: IMX6ULL_DDR3L_400MHz_1GB_16bit_V2.2.inc Changes: Change MMDC_MDMISC.WALAT to 1 setmem /32 0x021B0018 = 0x00211740 Test: Passed memtester on two mx6ull ddr3 arm2 boards Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12888 usb: ehci: only shutdown opened controllerPeng Fan2016-06-06-0/+4
| | | | | | | | | | | | | | | | If the usb controller is not running, no need to shutdown it, otherwise `usb stop` complains about: "EHCI failed to shut down host controller". To i.MX7D SDB, there are two usb ports, one Host, one OTG. If we only plug one udisk to the Host port and then `usb start`, the OTG controller for OTG port does not run actually. Then, if `usb stop`, the OTG controller for OTG port will also be shutdown, but it is not running. This patch adds a check that only shutdown the running controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12883 usb: limit USB_MAX_XFER_BLK to 256Peng Fan2016-06-06-1/+3
| | | | | | | | | | | | | | | | | | | For Some USB mass storage devices, such as: " - Kingston DataTraveler 2.0 001D7D06CF09B04199C7B3EA - Class: (from Interface) Mass Storage - PacketSize: 64 Configurations: 1 - Vendor: 0x0930 Product 0x6545 Version 1.16 " When `usb read 0x80000000 0 0x2000`, we met "EHCI timed out on TD - token=0x80008d80". The devices does not support scsi VPD page, we are not able to get the maximum transfer length for READ(10)/WRITE(10). So we limit this to 256 blocks as READ(6). Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12884 mx7dsabresd: Fix LCD_PWR_EN output settingYe Li2016-06-06-1/+1
| | | | | | | | | LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3 is actually 1.2V. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 28eb616b6c49de492cc0cdb3ad5b618bed77960f)
* MLK-12852 ocotp: mxc: mx6ull: fix GP3/GP4 progPeng Fan2016-06-03-1/+7
| | | | | | | | | | | | Bank 7 and Bank 8 only supports 4 words each. 'bank << 3 | word' is not correct when program bank 8, since ocotp controller actully use word index. For example: fuse prog 8 3 1; The word index is (8 << 3 | 3) --> 67. But actully it should be (7 << 3 | 7) ---> 63. So fix it. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12865 Nand: Fix BCH debug1 register access issueYe Li2016-05-31-1/+1
| | | | | | Should have "&" to access the register address, otherwise uboot will hang. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12848: mx6ull_14x14_ddr3_arm2: add new TSC configHaibo Chen2016-05-24-0/+21
| | | | | | | | Due to TSC pin conflict with I2C1 bus, and PMIC is this I2C1 bus's slave, this patch add new TSC config for i.mx6ull_14x14_ddr3_arm2 board, disable PMIC and ldo bypass check. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
* MLK-12845 imx: mx6sabre_common: fix mmcargsPeng Fan2016-05-23-2/+2
| | | | | | | A space should be added after ${smp}. If not, bootargs is wrong, when CONFIG_SYS_NOSMP defined. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12815: mx6ul_14x14_evk: add new NAND config for i.MX6UL 14x14 EVK boardHan Xu2016-05-23-0/+9
| | | | | | | | add new NAND config for i.MX6UL 14x14 EVK board, and disable USDHC2 when NAND enabled due to pin conflict. Signed-off-by: Han Xu <han.xu@nxp.com> (cherry picked from commit 81e175bcc07792fab6010761daf6576bd600edda)
* MLK-12798 imx6ull: fix snvs tamper pin usagePeng Fan2016-05-16-16/+30
| | | | | | | | | | | | | SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module, not in IOMUXC, so correct the related registers' offset. Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate them from iomuxc pins. Define CONFIG_IOMUX_LPSR for mx6ull_ddr3_arm2 board to enable using these pins. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12800 imx: mx7dsabresd: support revCPeng Fan2016-05-16-4/+13
| | | | | | Add revC board support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12791 mx6qpsabresd: Change ENET TXCLK clock from PLLYe Li2016-05-16-0/+10
| | | | | | | | | | | | In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY, While kernel uses the clock from internal PLL by setting GPR5 bit 9. When doing warm reset in kernel, the GPR regigster is not reset, so the clock source still is the PLL. This causes ENET in u-boot can't work. In this patch, we change the u-boot to use internal PLL to align with kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12775 mx6ullarm2: Add package size info to the build target and dtb fileYe Li2016-05-11-1/+1
| | | | | | | | To align with i.MX6UL, add the chip package size info to the i.MX6ULL ARM2 board build target and loading dtb file name. So that mfgtool and yocto can follow i.MX6UL naming rule to process i.MX6ULL. Signed-off-by: Ye Li <ye.li@nxp.com>
* imx: iomux-v3: fix UART input selectsStefan Agner2016-05-10-4/+4
| | | | | | | | | | | | | | | Several UART input selects are missing. The fourth input select for UART2_TX_DATA_ALT0 is actually also missing in the documentation. (at least in Rev. B of the i.MX 7Dual Reference Manual). However, when looking at the tables of other input selects, it is very natural that there must be an input select for the UART2_TX_DATA_ALT0 pad. The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and it was required to set that particular input select register to get a working UART2. From https://www.mail-archive.com/u-boot@lists.denx.de/msg211942.html Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12767 imx6ull: fix runtime checking for i.MX6ULLPeng Fan2016-05-09-24/+34
| | | | | | | Fix runtime checking for i.MX6ULL. Add is_cpu_type(MXC_CPU_MX6ULL) to avoid using wrong code path. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12766 net: fec: do not access reserved register for i.MX6ULLPeng Fan2016-05-09-1/+1
| | | | | | | | | The MIB RAM and FIFO receive start register does not exist on i.MX6ULL. Accessing these register will cause enet not work well or cause system report fault. Reported-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12748-3 imx: adjust imx7d lpddr3 lpsr exit flowAnson Huang2016-05-09-1/+13
| | | | | | | | | | | | On i.MX7D lpddr3, retention mode exit flow should restore more registers to make sure the ddr controller and ddr phy settings restored properly, otherwise, some of the boards can NOT pass memtester after retention mode exited. For LPSR mode, ddr resume flow is same as retention mode, just adjust it accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12748-2 imx: remove IOMUXC GPR setting for i.mx7d retention modeAnson Huang2016-05-09-3/+3
| | | | | | | | i.MX7D TO1.2 removes the DDR PADs retention mode setting in IOMUXC GPR, it is same as TO1.0, so only apply the IOMUXC GPR setting for TO1.1. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12748-1 imx: adjust i.mx7d standby voltage settingAnson Huang2016-05-09-14/+14
| | | | | | | i.MX7D VDD_ARM/SOC standby voltage should be 0.95V, adding 25mV margin, so set it to 0.975V; Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12693-2 nand: mxs: correct bitflip for erased NAND pagePeng Fan2016-05-07-2/+22
| | | | | | | | | | | | | | | | | | This patch is a porting of http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38 " i.MX6QP and i.MX7D BCH module integrated a new feature to detect the bitflip number for erased NAND page. So for these two platform, set the erase threshold to gf/2 and if bitflip detected, GPMI driver will correct the data to all 0xFF. Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q with the one for i.MX6QP. " In this patch, i.MX6UL is added and threshold changed to use ecc_strength. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12693-1 nand: mxs: fix the bitflips for erased page when uncorrectable errorPeng Fan2016-05-06-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is porting from linux: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=3d42fcece496224fde59f9343763fb2dfc5b0768 " We may meet the bitflips in reading an erased page(contains all 0xFF), this may causes the UBIFS corrupt, please see the log from Elie: ----------------------------------------------------------------- [ 3.831323] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry [ 3.845026] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry [ 3.858710] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry [ 3.872408] UBI error: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read 16384 bytes ... [ 4.011529] UBIFS error (pid 36): ubifs_recover_leb: corrupt empty space LEB 27:237568, corruption starts at 9815 [ 4.021897] UBIFS error (pid 36): ubifs_scanned_corruption: corruption at LEB 27:247383 [ 4.030000] UBIFS error (pid 36): ubifs_scanned_corruption: first 6569 bytes from LEB 27:247383 ----------------------------------------------------------------- This patch does a check for the uncorrectable failure in the following steps: [0] set the threshold. The threshold is set based on the truth: "A single 0 bit will lead to gf_len(13 or 14) bits 0 after the BCH do the ECC." For the sake of safe, we will set the threshold with half the gf_len, and do not make it bigger the ECC strength. [1] count the bitflips of the current ECC chunk, assume it is N. [2] if the (N <= threshold) is true, we continue to read out the page with ECC disabled. and we count the bitflips again, assume it is N2. (We read out the whole page, not just a chunk, this makes the check more strictly, and make the code more simple.) [3] if the (N2 <= threshold) is true again, we can regard this is a erased page. This is because a real erased page is full of 0xFF(maybe also has several bitflips), while a page contains the 0xFF data will definitely has many bitflips in the ECC parity areas. [4] if the [3] fails, we can regard this is a page filled with the '0xFF' data. " Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: imx7d: fix ahb clock mux 1Stefan Agner2016-05-06-1/+1
| | | | | | | | | | | | | | The clock parent of the AHB root clock when using mux option 1 is the SYS PLL 270MHz clock. This is specified in Table 5-11 Clock Root Table of the i.MX 7Dual Applications Processor Reference Manual. While it could be a documentation error, the 270MHz parent is also mentioned in the boot ROM configuration in Table 6-28: The clock is by default at 135MHz due to a POST_PODF value of 1 (=> divider of 2). Signed-off-by: Stefan Agner <stefan@agner.ch>
* MLK-12723 imx: Change the env offset on NAND to 60MYe Li2016-05-06-8/+8
| | | | | | | | | | | | | | | Current environment offset on NAND is 37MB, this will cause a alignment issue when erasing if nand erase block is 2MB. The saveenv is failed. => saveenv Saving Environment to NAND... Erasing NAND... Attempt to erase non block-aligned data Since the max erase block we supported is 4MB, adjust the env offset to 60MB, where is the last 4MB in 64MB reserved area for boot. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12629-2: i.MX6QP: update pluginPeng Fan2016-05-04-0/+12
| | | | | | For i.MX6QP, the QoS settings is different from others. Align with DCD. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12629-1: imx6: cache: disable L2 before touching Auxiliary Control RegisterPeng Fan2016-05-04-3/+6
| | | | | | | | | | | | | | | | | | | | According PL310 TRM, Auxiliary Control Register " The register must be written to using a secure access, and it can be read using either a secure or a NS access. If you write to this register with a NS access, it results in a write response with a DECERR response, and the register is not updated. Writing to this register with the L2 cache enabled, that is, bit[0] of L2 Control Register set to 1, results in a SLVERR. " So If L2 cache is already enabled, chaning value of ACR will cause SLVERR, uboot hangs. In some cases, such as plugin, L2 Cache enabled bit is not cleared, then "Set bit 22 in the auxiliary control register" cause uboot hangs. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12739: imx: tools: imximage: fix CLR bit commandAdrian Alonso2016-05-03-1/+1
| | | | | | | | Fix incorrect parametr in CMD_CHECK_BITS_CLR command Pass CLR parameter to DCD header for CMD_CHECK_BITS_CLR Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12737 mx6qp/mx6dp: Fix runtime CPU type checking issueYe Li2016-05-03-9/+33
| | | | | | | | | | | 2016 u-boot added dummy CPU types for the i.MX6QP and i.MX6DP. When doing runtime cpu type checking, we can't use CPU type of i.MX6Q and i.MX6D for them more, which is ok in 2015 u-boot. This patch adds the MXC_CPU_MX6QP and MXC_CPU_MX6DP at some places missed to do the checking. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12736 mx6ulevk: Delete obsoleted android build targetYe Li2016-04-29-14/+0
| | | | | | | The build target mx6ul_14x14_evk_android_defconfig is obsoleted. It is replaced by mx6ul_14x14_evk_brillo_defconfig. So remove this old file. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12735 mx6qpsabresd: Update DDR script to version 1.14Ye Li2016-04-29-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR script file: arik_r2_sdb_ddr3_528_1.14.inc Compass link: http://compass.freescale.net/livelink/livelink?func=ll&objid=235302593&objAction=browse&sort=name&viewType=1 Update: setmem /32 0x020e0534 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 (SDQS0_B_TRIM=01, SDQS0_TRIM=10) setmem /32 0x020e0538 = 0x00008000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 (SDQS1_B_TRIM=00, SDQS1_TRIM=00) setmem /32 0x020e053C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 (SDQS2_B_TRIM=01, SDQS2_TRIM=10) setmem /32 0x020e0540 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 (SDQS3_B_TRIM=01, SDQS3_TRIM=10) setmem /32 0x020e0544 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 (SDQS4_B_TRIM=01, SDQS4_TRIM=10) setmem /32 0x020e0548 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 (SDQS5_B_TRIM=01, SDQS5_TRIM=10) setmem /32 0x020e054C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 (SDQS6_B_TRIM=01, SDQS6_TRIM=10) setmem /32 0x020e0550 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 (SDQS7_B_TRIM=01, SDQS7_TRIM=10) setmem /32 0x021b08c0 = 0x24912489 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6 setmem /32 0x021b48c0 = 0x24914452 setmem /32 0x021b0018 = 0x00011740 // MMDC0_MDMISC, RALAT=0x5, WALAT=0x1 Test: Passed stress memtester on one board. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit b7f43f47a78c9d0c14fe104daf22efab13709ab1)
* MLK-12705-2 imx7d: add build target for TO1.1Anson Huang2016-04-29-6/+6
| | | | | | | Default build target supports TO1.0 and TO1.2, TO1.1 uses its own defconfig. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* MLK-12705-1 ARM: imx: add support for i.MX7D TO1.2Anson Huang2016-04-29-59/+59
| | | | | | | | i.MX7D TO1.2 uses same DDR script as TO1.0, TO1.1 uses dedicated DDR script. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 527d57e02b05eb0166dcaa1929e46dd2357a8720)
* MLK-12711 imx: correct speed grading info for i.MX6ULPeng Fan2016-04-28-0/+15
| | | | | | Correct speed grading info for i.MX6UL Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-12694 mx6ullarm2: Remove the CD detection of SD2Ye Li2016-04-22-3/+1
| | | | | | | | | | Since the CD pin of SD2 is DNP on the mx6ull arm2 board, this will cause SD2 access problem even the card is inserted. Hard code the CD result to 1 to assume the card is always on. The SD driver will return other errors if the card does not exist. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 47efe2fda62297ab1da8594828cd7bd928ecbda7)
* MLK-12691-2 mx6ullarm2: Add build targets for various boot devicesYe Li2016-04-21-0/+20
| | | | | | Four build targets added for eMMC, NAND, QSPIA and SPINOR boot. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12691-1 mx6ullarm2: Update config file to remove unnecessary settingsYe Li2016-04-21-6/+3
| | | | | | | To align with other i.mx6 platforms, update config file to remove some unnecessary settings. Also enable the GPIO command. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-12687 mx6ullarm2: Clean up macro usage for pins conflict devicesYe Li2016-04-21-8/+11
| | | | | | | | | | | | | | | 1. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK to eMMC 8 bits rework, which conflicts with QSPIA and NAND, that we have to disable them at same time. 2. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK to QSPI B port rework, which conflicts with SD2 and NAND, that we have to disable them at same time. 3. Fix a typo issue of CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK 4. Enable QSPI support for default SD boot case. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 00f36b3e9445ff47ed68262ef2d656e410cd8fcd)
* MLK-12690 imx: mx6ull: fix build error for pluginPeng Fan2016-04-21-1/+1
| | | | | | | | | Fix build error for Plugin "Can't stat board/freescale/mx6ul_14x14_ddr3_arm2/plugin.bin: Bad file descriptor" Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 95860f1213c038ef2e5900d1874ff5398ac0be2a)
* MLK-12677 mx6ullarm2: Update DDR script to version 2.1Ye Li2016-04-20-5/+6
| | | | | | | | | | | | | | | | | | | File: IMX6ULL_DDR3L_400MHz_1GB_16bit_V2.1.inc Changes: Change ZQ_OFFSET to the default value:00 setmem /32 0x021B0890 = 0x00400000 Change IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET.DDR_SEL to 11 setmem /32 0x020E0288 = 0x000C0030 Change duty cycle fine tune cell for SDCLK and SDQS setmem /32 0x021B08C0 = 0x00944009 Test: One mx6ull ARM2 board passed memtest. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 8128b2f3b419a1d15a0489a91e56a4ac82eaf0c4)
* MLK-12658 imx: adjust POR_B setting on i.MX6ULLAnson Huang2016-04-15-0/+14
| | | | | | | | | | | | Adjust POR_B settings on i.MX6ULL according to design team's suggestion: 2'b00 : always PUP100K 2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL 2'b10 : always disable PUP100K 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended setting Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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