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* MLK-14707 fsl_esdhc: Fix eMMC 1.8v setting issuerel_imx_4.1.15_2.1.0_gaimx_v2016.03_4.1.15_2.0.0_gaYe Li2017-05-02-4/+4
| | | | | | | | | | | | Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init, then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has already set VSELECT to 1.8v before running the u-boot. This reset in USDHC driver causes a short 2.2v pulse on CMD pin. Fix this issue by not reset VSELECT to 0 when 1.8v flag is set. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit f01ebfdaa57b4c74ede32a6a40cf9cf9184ce049)
* MLK-13508-2 mx6sllarm2: Update DDR script to v2.3Ye Li2017-04-19-9/+11
| | | | | | | | | | | | | | | | | | | | DDR scripts are updated to fix DQS gating issue commonly for LPDDR2 and LPDDR3. That DQS sampling may have problem after enabling the SDE_0/SDE_1 in MDCTL. Changes: -Based on V2.2, move the "Read DQS Gating Disable" to the step after "MR setting", to avoid potential DDR initializaiton failures (especially in Plugin Mode). File: http://compass.freescale.net/livelink/livelink?func=ll&objid=235701297&objAction=browse&sort=name&viewType=1 Test: Passed stress test on 1 LPDDR2 ARM2 board and 1 LPDDR3 ARM2 board. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 8e0351e7d524a1d53b596710972e074487d9d1fe)
* MLK-13508-1 mx6sllevk: Update DDR script to v2.2Ye Li2017-04-19-4/+5
| | | | | | | | | | | | | | | | | | | DDR script is updated to v2.2 to fix potential DQS gating issue. That DQS sampling may have problem after enabling the SDE_0/SDE_1 in MDCTL. Changes: -Based on V2.1.1, move the "Read DQS Gating Disable" to the step after "MR setting", to avoid potential DDR initializaiton failures (especially in Plugin Mode). File: http://compass.freescale.net/livelink/livelink?func=ll&objid=235701297&objAction=browse&sort=name&viewType=1 Test: Passed stress test on two boards. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 8adb838b9d9b7109cd50965c624f279aa6a74673)
* MXSCM-267 mx6dqscm: set hdmi as primary display for qwks boardJuan Gutierrez2017-03-10-2/+8
| | | | | | | For the out of the box experience, the primary display for the QWKS board is set to HDMI. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-266 mx6dqscm: increase lpddr2 voltage to 1.25VJuan Gutierrez2017-03-10-2/+2
| | | | | | | From testing the performance is better when the voltage for lpddr2 is set to 1.25V instead of 1.2V. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-237 mx6dqscm: qwks: add support for qwks rev3Juan Gutierrez2016-12-08-1/+32
| | | | | | | | | | | Support for the i.MX SX SCM QWKS rev3. The new revision has support for ov5642 camera, bluetooth and wifi support. Providing configuration files for: - Regular 1gb board - spinor Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-236 mx6dqscm: adjust some ddr calibration parametersJuan Gutierrez2016-12-08-13/+16
| | | | | | | | | | | Some adjustment to the ddr configuration like: - Precharge all commands per JEDEC - Fix the space partition values for 2Gb - Fix other values that reduce yield of scm parts per testing perfomed Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MLK-13551: mx6ull: evk: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+3
| | | | | | | | | | | | | LPDDR2 script IMX6ULL_9X9_LPDDR2_400MHz_16bit_V1.2.inc Updated to add precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> (Cherry pick from commit 977a06025b97569fdd43781961b3f90344eab737)
* MLK-13451-2: mx6ul: arm2: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+3
| | | | | | | | | | | | | LPDDR2 script IMX6UL_LPDDR2_400MHz_16bit_V1.1.inc Updated to add precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> (Cherry pick from commit c9483905bc4ef6d912f96a4324fc60fd6aabcca6)
* MLK-13451-1: mx6ul: evk: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+3
| | | | | | | | | | | | | LPDDR2 script IMX6UL_LPDDR2_400MHz_16bit_V1.1.inc Updated to add precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> (Cherry pick from commit 97e63e7c3dac2e2012f174198a4ced7d1437a7c9)
* MLK-13540-2: mx6sx: arm2: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+6
| | | | | | | | | | | | | LPDDR2 script MX6SX_19x19_LPDDR2_JEDEC.inc Updated to add Precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> (Cherry pick from commit fac0991970b49ecae83129ecc355b71d8d54a1fb)
* MLK-13540-1: mx6sx: arm2: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+6
| | | | | | | | | | | | | | LPDDR2 script MX6SX_19x19_LPDDR2_JEDEC.inc Updated to add Precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> (Cherry pick from commit 73ff17548cb04733a50dd6c753b3931a8b772e9d)
* MLK-13539: mx6sl: evk: lpddr2: add pre charge command allAdrian Alonso2016-12-01-0/+3
| | | | | | | | | | | | | LPDDR2 script MX6SL_MMDC_LPDDR2_register_programming_aid_v0.9.inc Updated to add Precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> (Cherry pick from commit 498f4a791593069220213c6d777527f4d899fb8a)
* MXSCM-222 usb: fix swbst_mode to properly power usbJuan Gutierrez2016-11-30-1/+1
| | | | | | | | | | The definition of the SWBST_MODE_AUTO at the pfuze100_pmic.h file changed between uboot versions. On the previous version the shift to the proper bit field was part of the macro. In the uboot v2016 this macro does not include the shift and needs to be performed explicitly to properly modify the SWBST_MODE bit field. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-213: remove dmfc from boot arguments for mx6scm boardsJuan Gutierrez2016-11-30-5/+2
| | | | | | | | | | | | Intially this parameter was added to fix a video stuttering but with L4.1 the video issue is not present so we can safely get rid of this parameter. When using both ldb interfaces in separate mode and passing the dmfc argument as boot parameter to the kernel, a distortion on both displays is observed when rendering to the secondary display. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MXSCM-212: mx6dqscm: usb: fix usb_otg_id iomux pad settingsJuan Gutierrez2016-11-30-0/+8
| | | | | | | | | | USB_OTG_ID iomux pad was missconfigured and not selecting the GPIO1 Alternative for QWKS and the ENET_RX_ERR for EVB, as a consequence when connecting a USB device the PWR_EN was disabled. So usb function like "usb start" was not working as it should. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
* MLK-13486: imx: logos: use NXP logoPeng Fan2016-11-22-0/+0
| | | | | | | | | Use NXP logo. The vendor and board dir not changed, only replace the contents of freescale.bmp. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 0b381fdf1a45cb06a057724e708ce0bbeee67f4d)
* MLK-13499 imx6sll: add epdc splash screen supportRobby Cai2016-11-21-4/+458
| | | | | | | | add splash screen feature for epdc. it's tested on imx6sll arm2 board and evk board. Signed-off-by: Robby Cai <robby.cai@nxp.com> (cherry picked from commit c85c6f2a0f08dfc6c2859fe969b2021ab32b9370)
* MLK-13440-5 fsl_usdhc: Remove the CONFIG_SYS_FSL_ESDHC_FORCE_VSELECTYe Li2016-11-16-4/+0
| | | | | | | | | | Since we have added the "vs18_enable" parameter for fixed 1.8v I/O, remove the CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT. This configuration can only work with one MMC device. If more devices are supported, this will set 1.8v to all controllers, so will cause problem to 3.3v devices. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit c1de6a58e44f4770b32a41e3689884abf7449e1b)
* MLK-13440-4 warp: Replace CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT by using ↵Ye Li2016-11-16-2/+1
| | | | | | | | | | vs18_enable parameter Change to use the new way to set the vs18_enable field to 1 for fixed 1.8v I/O eMMC. Don't use CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT any longer. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit c1bf2d975be66597f8fc25c9eef0f02bda3c5050)
* MLK-13440-3 mx6sll_arm2: Update USDHC2 parameter for using 1.8V I/OYe Li2016-11-16-6/+2
| | | | | | | | | Set the vs18_enable field to 1 for USDHC2 controller which connects to eMMC. Also remove the explicit USDCH2 vendorspec register settings in board codes, since the driver will take charge of it. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 0c56b6814333f2ac1c2462d8a1aed8df07ad403d)
* MLK-13440-2 mx6sllevk: Update USDHC2 parameter for using 1.8V I/OYe Li2016-11-16-6/+2
| | | | | | | | | Set the vs18_enable field to 1 for USDHC2 controller which connects to eMMC. Also remove the explicit USDCH2 vendorspec register settings in board codes, since the driver will take charge of it. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 03b2d94b925cf12d627527af2cd08054bb15dd4e)
* MLK-13440-1: fsl_usdhc: Add configuration parameter for using fixed 1.8V I/OYe Li2016-11-16-0/+6
| | | | | | | | | | | | | | | When using eMMC with 1.8V I/O, we have to set the VSELECT bit at this USDHC controller setup and init. The CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT has problem that it will apply to all USDHC controllers and it only set the 1.8V at init phase. So if user does not select to the eMMC device, the voltage on the I/O pins are not correct. This patch adds a parameter "vs18_enable" in fsl_esdhc_cfg structure, so each controller can have different settings. The default value is 0 for 3.3V, which is compatible with current codes. When setting this value to 1, at USDHC setup and init phase the driver will set the VSELECT bit. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit ebd872f491af27c38a0698d226222ea5093c563c)
* MLK-13405-4 mx6sll-arm2: change the eMMC reset pad to 1.8vHaibo Chen2016-11-16-2/+6
| | | | | | | | | | | eMMC is connected fixed to 1.8v, so need to set the LVE of pad sd2_rst. Also need to set the VSELECT to change all the eMMC pad (cmd, clk, data) I/O voltage to 1.8v. Otherwise, the current leak will pull up the VCCQ from 1.8v to 2.6v, which will impact SD1 and SD3 voltage switch. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> (cherry picked from commit 07abbd4e5c5006ab7adc6a4f3655e9a0817c7cb1)
* MLK-13405-3 mx6sll-evk: change the eMMC reset pad to 1.8vHaibo Chen2016-11-16-2/+6
| | | | | | | | | | | eMMC is connected fixed to 1.8v, so need to set the LVE of pad sd2_rst. Also need to set the VSELECT to change all the eMMC pad (cmd, clk, data) I/O voltage to 1.8v. Otherwise, the current leak will pull up the VCCQ from 1.8v to 2.6v, which will impact SD1 and SD3 voltage switch. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> (cherry picked from commit 0df1d6537bef13c1846c6762e78938a304e083b0)
* MLK-13410 Android: Change to set mfgtool only for none android u-bootYe Li2016-11-16-2/+2
| | | | | | | | | | | The mfgtool environments only can set in BSP u-boot image, not for android u-boot. Since android u-boot may go into fastboot in board_r phase which is earlier than mfgtool environment check. The USB status from android fastboot will cause u-boot to configure mfgtool environment. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 066f001a19bdc51b0fc0d65bcb87081b01f957c2) (cherry picked from commit 03f995630f92462081e98412a0fbc86bb5106f10)
* MLK-13392 configs: add extra misc NAND partition for AndroidHan Xu2016-11-16-25/+25
| | | | | | | | add one more extra NAND partition in u-boot environment setting to support Android. Signed-off-by: Han Xu <han.xu@nxp.com> (cherry picked from commit 38bd0d6428f3059f616c4da3ce40722ae664f8b5)
* MLK-13373 mx6sll: update ddr script to 2.1.1Peng Fan2016-11-16-4/+4
| | | | | | | | | | | | | | | | | Update ddr script to 2.1.1 Script: http://compass.freescale.net/livelink/livelink/235732623/EVK_IMX6SLL_LPDDR3_400MHz_512MB_32bit_V2.1.1.txt?func=doc.Fetch&nodeid=235732623 Version 2.1.1: -Update [MMDC_MPRDDLCTL] and [MMDC_MPWRDLCTL] based on calibration results -setmem /32 0x021B0848 = 0x3F393B3C // [MMDC_MPRDDLCTL] MMDC PHY Read delay-lines Configuration Register -setmem /32 0x021B0850 = 0x262C3826 // [MMDC_MPWRDLCTL] MMDC PHY Write delay-lines Configuration Register Tested on two boards. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit a3e5ebaa772e7ab1fe54615a47656b796cf5723e)
* MLK-13352 imx: mx6sll: support mx6sllevk boardPeng Fan2016-11-16-0/+1043
| | | | | | | | | | | Add mx6sll evk board support. USB/LCDIF/I2C/SD/EMMC/WDOG supported. The ddr script is from mx6sll lpddr3 arm2 board. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 74054cc9eb8077b375f41235b081f1a1596fa4a6)
* MLK-13360 mx6sll_arm2: Fix typo issue in mx6sll LPDDR2 ARM2 defconfigYe Li2016-11-16-1/+1
| | | | | | | Change the 'kONFIG' to 'CONFIG', otherwise will get build warning: unexpected data Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 4deeb82446def7ac7b74c6fec61cefe7893eae06)
* mmc: sd: optimize erasePeng Fan2016-11-16-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | To SD, there is no erase group, then the value erase_grp_size will be default 1. When erasing SD blocks, the blocks will be erased one by one, which is time consuming. We use AU_SIZE as a group to speed up the erasing. Erasing 4MB with a SD2.0 Card with AU_SIZE 4MB. `time mmc erase 0x100000 0x2000` time: 44.856 seconds (before optimization) time: 0.335 seconds (after optimization) Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Eric Nelson <eric@nelint.com> Cc: Stephen Warren <swarren@nvidia.com> (cherry picked from commit e492dbb41e025ac1a7d7934b1df52b2f0485f8dd) (cherry picked from commit a9beae5f9be6358036ef328c75bf5b40eaf94581)
* mmc: sd: extracting erase related information from sd statusPeng Fan2016-11-16-0/+77
| | | | | | | | | | | | | | | | | | Add function to read SD_STATUS information. According to the information, get erase_timeout/erase_size/erase_offset. Add a structure sd_ssr to include the erase related information. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Eric Nelson <eric@nelint.com> Cc: Stephen Warren <swarren@nvidia.com> (cherry picked from commit 3697e5992f89c923aca17d7d9174739da28cb3cd) (cherry picked from commit be950ab9d0625ae1a23c7a5e03dde8e5a676ea80)
* MLK-13336 mx6sll_arm2: Update LPDDR2 script to v2.1Ye Li2016-11-16-3/+10
| | | | | | | | | | | | | | | | | | | | | Changes: Version 2.1 -Issue a Precharge-All command prior to the MRW Reset command. setmem /32 0x021B001C = 0x00008050 // [MMDC_MDSCR] precharge all to CS0 setmem /32 0x021B001C = 0x00008058 // [MMDC_MDSCR] precharge all to CS1 -Update MMDC PHY Read/Write delay-lines Configuration Register according to calibration results setmem /32 0x021B0848 = 0x3A383C40 // [MMDC_MPRDDLCTL] setmem /32 0x021B0850 = 0x242C3020 // [MMDC_MPWRDLCTL] File: http://compass.freescale.net/livelink/livelink?func=ll&objId=235701297&objAction=browse&viewType=1 Test: Passed overnight memtester on one i.MX6SLL LPDDR2 ARM2 board. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 5ad998cbb8698052315d29bffaa4e264ebe4aad4)
* MLK-13335 mx6sl: Fix build break for all i.MX6SL boardsYe Li2016-11-16-2/+2
| | | | | | | | | Since the UART1 register base name is changed from UART1_IPS_BASE_ADDR to UART1_BASE to align with other i.MX6 chips. Should update the board configuration header file with the new name. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 18019b8f4b65d3261db6488e416eae66a6500316)
* MLK-13331 mx6sll_arm2: Output WDOG_B signal to reset PMICYe Li2016-11-16-0/+8
| | | | | | | | Since the LPDDR2/3 does not have reset pin, to keep safe reset, we need to use WDOG_B to reset PMIC. Add pinmux and relevant settings. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit be0b2d9cb2969725d0231bc9836a3e2c39f84dee)
* MLK-13330 mx6sll_arm2: Update LPDDR3 script to v2.2Ye Li2016-11-16-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | Changes from v1.2 to v2.2: Version 2.2 -Issue a Precharge-All command prior to the MRW Reset command. -setmem /32 0x021B001C = 0x00008050 // [MMDC_MDSCR] precharge all to CS0 -setmem /32 0x021B001C = 0x00008058 // [MMDC_MDSCR] precharge all to CS1 Version 2.1 -Update MMDC PHY Read/Write delay-lines Configuration Register according to calibration results -setmem /32 0x021B0848 = 0x3C3A3C3C // [MMDC_MPRDDLCTL] -setmem /32 0x021B0850 = 0x24293625 // [MMDC_MPWRDLCTL] Version 1.2.1 -Fix a typo. setmem /32 0x020E052C = 0x00000030 -Fix a typo. setmem /32 0x021B0800 = 0xA1390003 File: http://compass.freescale.net/livelink/livelink?func=ll&objId=235701297&objAction=browse&viewType=1 Test: Overnight memtester passed on two i.MX6SLL LPDDR3 ARM2 boards. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 92946cba62d23e6ace547a90a0debb1916fa0add)
* MLK-13311 configs: mx6sll_lpddr3_arm2: Enable network functionPeter Chen2016-11-16-0/+5
| | | | | | | | Since mx6sll has no ethernet controller, we take USB ethernet device as network device by default. Signed-off-by: Peter Chen <peter.chen@nxp.com> (cherry picked from commit f6c75d019afb2b4a59b10649b95bde8b7723a30b)
* MLK-13307-15 imx: mx6sll: add mx6sll arm2 supportPeng Fan2016-11-16-0/+1352
| | | | | | | | | | | | Add mx6sll lpddr3/lpddr2 arm2 support. LCDIF/SPI/USB/PMIC supported. LPDDR3 DDR version: 1.2 LPDDR2 DDR version: initial version. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com> (cherry picked from commit 497134af4819241d49bbc22f1849756c7c06eb2e)
* MLK-13307-14 imx-common: lcdif: update lcdif regs for i.MX6SLLPeng Fan2016-11-16-4/+5
| | | | | | | | Update lcdif regs for i.MX6SLL Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit a0b0849142d475a01816f0a5d7221251cdbd2f76)
* MLK-13307-13 OCOTP: Update OCOTP driver to support i.MX6SLLYe Li2016-11-16-8/+10
| | | | | | | | | The i.MX6SLL reuses the i.MX6ULL fuse, and has same fuse bank map. Add the i.MX6SLL support to OCOTP driver. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 45e47b225911cda368519953d834aca3976dc70d)
* MLK-13307-12 imx: mx6: update ccm macro settings for i.MX6SLLPeng Fan2016-11-16-6/+71
| | | | | | | | Update CCM macros for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com> (cherry picked from commit f735f8ac328aa49759f6db524f7c2ba32622f711)
* MLK-13307-11 imx: mx6sll: disable LDOPeng Fan2016-11-16-0/+2
| | | | | | | There is no LDO for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit a7ea01a7ac6d45c9df72980cb3067c8e65678d11)
* MLK-13307-10 mx6_common: correct loadaddr and text base for i.MX6SLLPeng Fan2016-11-16-1/+1
| | | | | | | Correct loadaddr and text base for i.MX6SLL Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit b62d502aba4682abfaa3c0a16018f1461a62f217)
* MLK-13307-9 imx: mx6sll: add Kconfig entry for i.MX6SLLPeng Fan2016-11-16-0/+4
| | | | | | | add Kconfig entry for i.MX6SLL Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 1966356b05ab6e9ea886deaf1c6e60c5afceca57)
* MLK-13307-8 imx-common: cache: configure L2 Cache for i.MX6SLLPeng Fan2016-11-16-1/+1
| | | | | | | Configure L2 Cache for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit fc68bec5fb3163381d552d115f4b90882b83c10b)
* MLK-13307-7 imx: mx6sll: update soc settingsPeng Fan2016-11-16-5/+16
| | | | | | | Update soc settings for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit afa2d78f2b799337eae3dc67c0ed702d5520eee6)
* MLK-13307-6 imx: mx6sll: add clock support for i.MX6SLLPeng Fan2016-11-16-36/+158
| | | | | | | | Update clock settings for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com> (cherry picked from commit 37fd99776ef70325b8250c39fbc3b6a5933732bc)
* MLK-13307-5 imx: mx6sll: add iomux settingsPeng Fan2016-11-16-4/+10
| | | | | | | | Add iomux settings for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com> (cherry picked from commit e54356eb1374fe6b59f4dd4b4b60790dbe8bbad9)
* MLK-13307-4 imx-common: timer: add i.MX6SLL supportPeng Fan2016-11-16-2/+4
| | | | | | | Add i.MX6 SLL GPT timer support. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit d03cc466a5dbd94c1d9bcbdc574ad31512d8b24f)
* MLK-13307-3 imx: mx6sll: update register addressPeng Fan2016-11-16-41/+52
| | | | | | | Update register address for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit d541108c2134abfc2a3159a3609e1cf405793843)
generated by cgit v1.1 at 2024-11-21 13:00:34 +0000