| Commit message (Collapse) | Author | Age | Lines |
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We can't use config.h directly as some platforms include headers that
aren't safe to use in normal Linux userland.
Signed-off-by: Tom Rini <trini@ti.com>
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This patch fixes the following compilation warning for maxbcm:
Building maxbcm board...
text data bss dec hex filename
160075 6596 38240 204911 3206f ./u-boot
board/maxbcm/maxbcm.c: In function 'reset_phy':
board/maxbcm/maxbcm.c:68:6: warning: unused variable 'reg' [-Wunused-variable]
u16 reg;
^
board/maxbcm/maxbcm.c:66:6: warning: unused variable 'devadr' [-Wunused-variable]
u16 devadr = CONFIG_PHY_BASE_ADDR;
^
Additionally support Spansion SPI NOR flash is added. With larger SPI device
support via the CONFIG_SPI_FLASH_BAR define.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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This patch adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr)
into the AXP boot image. Not linked with the main U-Boot. With this code
addition and the following serdes/PHY setup code, the Armada-XP support
in mainline U-Boot is finally self-contained. So the complete image
for booting can be built from mainline U-Boot. Without any additional
external inclusion. Hopefully other MVEBU SoC's will follow here.
Support for some SoC's has been removed in this version. This is:
MV_MSYS:
The code referred to by the MV_MSYS define is currently unused. And its
not really planned to support this in mainline. So lets remove it to
make the code clearer and increase the readability.
MV88F68XX (A38x):
The code referred to by the MV88F68XX define (A38x) is currently unused.
And its partial and not sufficient for this device in this stage.
So lets remove it to make the code clearer and increase the readability.
MV88F66XX (ALP):
The code referred to by the MV88F66XX define is currently unused. And its
not really planned to support this in mainline. So lets remove it to
make the code clearer and increase the readability.
MV88F78X60_Z1:
The code referred to by the MV88F78X60_Z1 define is currently unused. As the
Z1 revision of the AXP is not supported in mainline anymore.
So lets remove it to make the code clearer and increase the readability.
Remove support for Z1 & A0 AXP revisions (steppings). The current stepping
is B0 and this is the only one that is actively supported in this code
version.
Tested on AXP using a SPD DIMM setup on the Marvell DB-MV784MP-GP board and
on a custom fixed DDR configuration board (maxbcm).
Note:
This code has undergone many hours of coding-style cleanup and refactoring.
It still is not checkpatch clean though, I'm afraid. As the factoring of the
code has so many levels of indentation that many lines are longer than 80
chars. This might be some task to tackly later on.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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This code is ported from the Marvell bin_hdr code into mainline
SPL U-Boot. It needs to be executed very early so that the devices
connected to the serdes PHY are configured correctly.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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This patch adds SPL support to the Marvell Armada-XP. With this addition
the bin_hdr integration is not needed any more. The SPL will first
initialize the serdes/PHY and the call the DDR setup and training code
now integrated into mainline U-Boot.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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This is used on the AXP boards, to pad u-boot.img to the desired offset in
SPI flash (only this boot target supported right now). This offset is
used by the SPL then to load u-boot.img into SDRAM and execute it there.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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This build target now includes the SPL binary as the bin_hdr into the
kwb image. Its used on the AXP port with the mainlined DDR training code.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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This patch adds SPL support to the db-mv784mp-gp eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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This patch adds SPL support to the maxbcm MV78460 based board. Including
the fixed DDR configuratrion needed for the DDR training code. And the
the serdes PHY init code.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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With this patchset the Marvell bin_hdr (DDR training) code is intergrated
into mainline U-Boot. We can remove the placeholder file again, which was
only introduced to make U-Boot compile and link again.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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LIBFDT feature is required to support new kernels.
Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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Signed-off-by: Gérald Kerma <drEagle@doukki.net>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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Checking if the pointer is NULL would be easier to know the tail
of the boot_device_table[] array.
For clarification, add the /* sentinel */ comment.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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The return value of get_boot_mode_sel() is used as the index of
the boot_device_table[] array. Its type should be "int" rather
than "u32".
Use only the iterator "i" for the loop in do_pinmon().
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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To use I2C controllers on PH1-sLD8, the bit 10 (SCL0/SDA0)
and bit 11 (SCL1/SDA1) of IECTRL register must be set.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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It is true that unused functions are removed from the ELF image
by the compiler's garbage collection but relying on it too much
does not look nice.
Currently, the build is taking more than it should.
Refactor the makefiles to compile only files that are really needed.
CONFIG_SOC_INIT and CONFIG_DRAM_INIT are no longer needed by the
optimization.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Since commit 0365ffcc0bd6 (generic-board: show model name in
board_init_f() too), checkboard() is invoked only when
show_board_info() fails to get the model name from Device Tree.
It never happens because UniPhier SoCs now only work with
CONFIG_OF_CONTROL and all the root nodes of UniPhier device trees
have the "model" property.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Since commit 0365ffcc0bd6 (generic-board: show model name in
board_init_f() too), the support card information has not been
displayed because check_support_card() is invoked only when
show_board_info() fails to get the model name from Device Tree.
This commit adds misc_init_f() function to call check_support_card()
from there.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Now init functions called from board_postclk_init() and dram_init()
are only necessary for SPL.
Move them to spl_board_init() for clean-up.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Currently, I/O pin settings are not necessary for SPL.
The board_early_init_f() seems a suitable place to call pin_init().
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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The EEPROM chips on UniPhier reference daughter boards expect 2-byte
offset address.
Since 7132b9fd68a1 (dm: i2c: dts: Support an offset-len device tree
property), I2C sub-nodes can have "u-boot,i2c-offset-len" property.
It is convenient to set the default I2C offset address length in
Device Tree, so that we do not have to set it on the command line.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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This EEPROM chip is installed on the expansion board commonly used
on UniPhier platform. To avoid duplicated description, move the
EEPROM node to a separate file and include it from other device tree
sources.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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The pattern "N: uniphier" can cover
- drivers/serial/serial_uniphier.c
- drivers/i2c/i2c-uniphier.c
- drivers/i2c/i2c-uniphier-f.c
- arch/arm/dts/uniphier-*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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To boot UniPhier boards with the NAND boot mode, two images
(u-boot-spl.bin and u-boot-dtb.img) must be written at the correct
offset addresses.
TFTP downloading is useful to update such images in the NAND device.
We generally do:
=> nand erase 0 0x100000
=> tftpboot u-boot-spl.bin
=> nand write $loadaddr 0 0x10000
=> tftpboot u-boot-dtb.img
=> nand write $loadaddr 0x10000 0xf0000
It is a tedious and error-prone operation.
This commit provides the shorthand:
=> run nandupdate
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Run the next command only when the previous one succeeded.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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This dummy header was introduced by commit 630bf80ebb34 (ARM:
UniPhier: add dummy gpio.h to enable CONFIG_OF_CONTROL).
Thanks to commit a08d643dbd85 (dm: Drop gpio.h header from
fdtdec.c), such an ugly workaround is no longer needed.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Enable ubifs_replay_journal during mount_ubifs, which was
disabled before.
This commit fix an issue with unrecoverable ubifs volumes
after power cut.
Therefor the gc.c is imported now from 1860e37 Linux 3.15
hs: added SPDX-License-Identifier for fs/ubifs/gc.c
Signed-off-by: Anton Habegger <anton.habegger@gmail.com>
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This commit is a preperation for a subsequent UBIFS commit
which needs atomic_long operations.
Therefor "include/asm-generic/atomic-long.h" is imported
from 1860e37 Linux 3.15
Signed-off-by: Anton Habegger <anton.habegger@gmail.com>
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if "ubi part" fails, reset also mtd_devs to 0, as
further "ubi part" would use wrong mtd_devs.
Signed-off-by: Heiko Schocher <hs@denx.de>
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Signed-off-by: Tom Rini <trini@ti.com>
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Use the STATUS_LED APIs for indicating a boot progress instead of
show_boot_progress.
This patch also fixes a problem introduced with commit b3f4ca1135 (dm: omap3:
Move to driver model for GPIO and serial). After that commit the board doesn't
boot. Looks like the problem is the gpio_request call inside the function
show_boot_progress.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
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In f0c3a6c we stopped setting gd in board_init_f, but later had to
revert to due problems on certain platforms. As davinci does not look
to have these problems, we can drop the setting here and rely upon
crt0.S to do it.
Cc: Peter Howard <pjh@northern-ridge.com.au>
Signed-off-by: Tom Rini <trini@ti.com>
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Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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These are needed for the upcoming Cairo board support.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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Generic board with #define CONFIG_SYS_GENERIC_BOARD is working fine.
There is no visible difference between legacy and generic board code.
Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
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Signed-off-by: Tom Rini <trini@ti.com>
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On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC
core rails. This concept of using one SMPS to supply multiple
core domains (in various, although limited combinations, per
primary device use case) has now become common and is used by
many customer J6/J6Eco designs; it is supported by a number of
corresponding PMIC OTP versions.
This patch implements correct operation of the core voltages
scaling routine by ensuring that each SMPS that is supplying
more than one domain shall be written only once, and with the
highest voltage of those fused in the SoC (or of those defined
in the corresponding header if fuse read is disabled or fails)
for the power rails belonging to the group.
The patch also replaces some PMIC-related magic numbers with
the appropriate definitions. The default OPP_NOM voltages for
the DRA7xx SoCs are updated as well, per the latest DMs.
Signed-off-by: Lubomir Popov <l-popov@ti.com>
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Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
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Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
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